| .. | .. |
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| 54 | 54 | * idle before writing to some registers. |
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| 55 | 55 | */ |
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| 56 | 56 | #define TMIO_MMC_HAS_IDLE_WAIT BIT(4) |
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| 57 | | -/* |
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| 58 | | - * A GPIO is used for card hotplug detection. We need an extra flag for this, |
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| 59 | | - * because 0 is a valid GPIO number too, and requiring users to specify |
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| 60 | | - * cd_gpio < 0 to disable GPIO hotplug would break backwards compatibility. |
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| 61 | | - */ |
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| 62 | | -#define TMIO_MMC_USE_GPIO_CD BIT(5) |
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| 63 | 57 | |
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| 64 | | -/* |
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| 65 | | - * Some controllers doesn't have over 0x100 register. |
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| 66 | | - * it is used to checking accessibility of |
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| 67 | | - * CTL_SD_CARD_CLK_CTL / CTL_CLK_AND_WAIT_CTL |
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| 68 | | - */ |
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| 69 | | -#define TMIO_MMC_HAVE_HIGH_REG BIT(6) |
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| 58 | +/* BIT(5) is unused */ |
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| 70 | 59 | |
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| 71 | 60 | /* |
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| 72 | 61 | * Some controllers have CMD12 automatically |
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| .. | .. |
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| 90 | 79 | /* Some controllers have a CBSY bit */ |
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| 91 | 80 | #define TMIO_MMC_HAVE_CBSY BIT(11) |
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| 92 | 81 | |
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| 93 | | -/* Some controllers that support HS400 use use 4 taps while others use 8. */ |
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| 94 | | -#define TMIO_MMC_HAVE_4TAP_HS400 BIT(13) |
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| 95 | | - |
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| 96 | 82 | int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base); |
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| 97 | 83 | int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base); |
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| 98 | 84 | void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state); |
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| .. | .. |
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| 111 | 97 | unsigned long capabilities2; |
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| 112 | 98 | unsigned long flags; |
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| 113 | 99 | u32 ocr_mask; /* available voltages */ |
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| 114 | | - unsigned int cd_gpio; |
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| 115 | 100 | int alignment_shift; |
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| 116 | 101 | dma_addr_t dma_rx_offset; |
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| 117 | 102 | unsigned int max_blk_count; |
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