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| 86 | 86 | /* 2 values for divider stage reset, others for "testing purposes only" */ |
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| 87 | 87 | # define RTC_DIV_RESET1 0x60 |
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| 88 | 88 | # define RTC_DIV_RESET2 0x70 |
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| 89 | + /* In AMD BKDG bit 5 and 6 are reserved, bit 4 is for select dv0 bank */ |
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| 90 | +# define RTC_AMD_BANK_SELECT 0x10 |
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| 89 | 91 | /* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */ |
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| 90 | 92 | # define RTC_RATE_SELECT 0x0F |
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| 91 | 93 | |
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| .. | .. |
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| 123 | 125 | #define RTC_IO_EXTENT_USED RTC_IO_EXTENT |
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| 124 | 126 | #endif /* ARCH_RTC_LOCATION */ |
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| 125 | 127 | |
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| 126 | | -unsigned int mc146818_get_time(struct rtc_time *time); |
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| 128 | +bool mc146818_does_rtc_work(void); |
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| 129 | +int mc146818_get_time(struct rtc_time *time); |
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| 127 | 130 | int mc146818_set_time(struct rtc_time *time); |
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| 128 | 131 | |
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| 132 | +bool mc146818_avoid_UIP(void (*callback)(unsigned char seconds, void *param), |
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| 133 | + void *param); |
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| 134 | + |
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| 129 | 135 | #endif /* _MC146818RTC_H */ |
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