| .. | .. |
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| 27 | 27 | struct seq_file; |
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| 28 | 28 | struct module; |
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| 29 | 29 | struct msi_msg; |
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| 30 | +struct irq_affinity_desc; |
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| 30 | 31 | enum irqchip_irq_state; |
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| 31 | 32 | |
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| 32 | 33 | /* |
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| .. | .. |
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| 69 | 70 | * IRQ_IS_POLLED - Always polled by another interrupt. Exclude |
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| 70 | 71 | * it from the spurious interrupt detection |
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| 71 | 72 | * mechanism and from core side polling. |
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| 72 | | - * IRQ_NO_SOFTIRQ_CALL - No softirq processing in the irq thread context (RT) |
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| 73 | 73 | * IRQ_DISABLE_UNLAZY - Disable lazy irq disable |
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| 74 | + * IRQ_HIDDEN - Don't show up in /proc/interrupts |
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| 75 | + * IRQ_RAW - Skip tick management and irqtime accounting |
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| 74 | 76 | */ |
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| 75 | 77 | enum { |
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| 76 | 78 | IRQ_TYPE_NONE = 0x00000000, |
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| .. | .. |
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| 97 | 99 | IRQ_PER_CPU_DEVID = (1 << 17), |
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| 98 | 100 | IRQ_IS_POLLED = (1 << 18), |
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| 99 | 101 | IRQ_DISABLE_UNLAZY = (1 << 19), |
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| 100 | | - IRQ_NO_SOFTIRQ_CALL = (1 << 20), |
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| 102 | + IRQ_HIDDEN = (1 << 20), |
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| 103 | + IRQ_RAW = (1 << 21), |
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| 101 | 104 | }; |
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| 102 | 105 | |
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| 103 | 106 | #define IRQF_MODIFY_MASK \ |
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| 104 | 107 | (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \ |
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| 105 | 108 | IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \ |
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| 106 | 109 | IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \ |
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| 107 | | - IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY | IRQ_NO_SOFTIRQ_CALL) |
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| 110 | + IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY | IRQ_HIDDEN) |
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| 108 | 111 | |
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| 109 | 112 | #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING) |
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| 110 | 113 | |
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| .. | .. |
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| 115 | 118 | * IRQ_SET_MASK_NOCPY - OK, chip did update irq_common_data.affinity |
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| 116 | 119 | * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to |
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| 117 | 120 | * support stacked irqchips, which indicates skipping |
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| 118 | | - * all descendent irqchips. |
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| 121 | + * all descendant irqchips. |
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| 119 | 122 | */ |
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| 120 | 123 | enum { |
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| 121 | 124 | IRQ_SET_MASK_OK = 0, |
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| .. | .. |
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| 196 | 199 | * IRQD_LEVEL - Interrupt is level triggered |
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| 197 | 200 | * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup |
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| 198 | 201 | * from suspend |
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| 199 | | - * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process |
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| 202 | + * IRQD_MOVE_PCNTXT - Interrupt can be moved in process |
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| 200 | 203 | * context |
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| 201 | 204 | * IRQD_IRQ_DISABLED - Disabled state of the interrupt |
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| 202 | 205 | * IRQD_IRQ_MASKED - Masked state of the interrupt |
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| .. | .. |
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| 212 | 215 | * IRQD_CAN_RESERVE - Can use reservation mode |
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| 213 | 216 | * IRQD_MSI_NOMASK_QUIRK - Non-maskable MSI quirk for affinity change |
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| 214 | 217 | * required |
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| 218 | + * IRQD_HANDLE_ENFORCE_IRQCTX - Enforce that handle_irq_*() is only invoked |
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| 219 | + * from actual interrupt context. |
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| 215 | 220 | * IRQD_AFFINITY_ON_ACTIVATE - Affinity is set on activation. Don't call |
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| 216 | 221 | * irq_chip::irq_set_affinity() when deactivated. |
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| 222 | + * IRQD_IRQ_ENABLED_ON_SUSPEND - Interrupt is enabled on suspend by irq pm if |
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| 223 | + * irqchip have flag IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND set. |
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| 217 | 224 | */ |
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| 218 | 225 | enum { |
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| 219 | 226 | IRQD_TRIGGER_MASK = 0xf, |
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| .. | .. |
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| 237 | 244 | IRQD_DEFAULT_TRIGGER_SET = (1 << 25), |
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| 238 | 245 | IRQD_CAN_RESERVE = (1 << 26), |
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| 239 | 246 | IRQD_MSI_NOMASK_QUIRK = (1 << 27), |
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| 247 | + IRQD_HANDLE_ENFORCE_IRQCTX = (1 << 28), |
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| 240 | 248 | IRQD_AFFINITY_ON_ACTIVATE = (1 << 29), |
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| 249 | + IRQD_IRQ_ENABLED_ON_SUSPEND = (1 << 30), |
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| 241 | 250 | }; |
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| 242 | 251 | |
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| 243 | 252 | #define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors) |
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| .. | .. |
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| 295 | 304 | |
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| 296 | 305 | /* |
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| 297 | 306 | * Must only be called of irqchip.irq_set_affinity() or low level |
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| 298 | | - * hieararchy domain allocation functions. |
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| 307 | + * hierarchy domain allocation functions. |
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| 299 | 308 | */ |
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| 300 | 309 | static inline void irqd_set_single_target(struct irq_data *d) |
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| 301 | 310 | { |
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| .. | .. |
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| 305 | 314 | static inline bool irqd_is_single_target(struct irq_data *d) |
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| 306 | 315 | { |
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| 307 | 316 | return __irqd_to_state(d) & IRQD_SINGLE_TARGET; |
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| 317 | +} |
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| 318 | + |
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| 319 | +static inline void irqd_set_handle_enforce_irqctx(struct irq_data *d) |
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| 320 | +{ |
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| 321 | + __irqd_to_state(d) |= IRQD_HANDLE_ENFORCE_IRQCTX; |
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| 322 | +} |
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| 323 | + |
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| 324 | +static inline bool irqd_is_handle_enforce_irqctx(struct irq_data *d) |
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| 325 | +{ |
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| 326 | + return __irqd_to_state(d) & IRQD_HANDLE_ENFORCE_IRQCTX; |
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| 327 | +} |
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| 328 | + |
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| 329 | +static inline bool irqd_is_enabled_on_suspend(struct irq_data *d) |
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| 330 | +{ |
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| 331 | + return __irqd_to_state(d) & IRQD_IRQ_ENABLED_ON_SUSPEND; |
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| 308 | 332 | } |
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| 309 | 333 | |
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| 310 | 334 | static inline bool irqd_is_wakeup_set(struct irq_data *d) |
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| .. | .. |
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| 474 | 498 | * @irq_set_vcpu_affinity: optional to target a vCPU in a virtual machine |
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| 475 | 499 | * @ipi_send_single: send a single IPI to destination cpus |
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| 476 | 500 | * @ipi_send_mask: send an IPI to destination cpus in cpumask |
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| 501 | + * @irq_nmi_setup: function called from core code before enabling an NMI |
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| 502 | + * @irq_nmi_teardown: function called from core code after disabling an NMI |
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| 477 | 503 | * @flags: chip specific flags |
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| 478 | 504 | */ |
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| 479 | 505 | struct irq_chip { |
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| .. | .. |
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| 522 | 548 | void (*ipi_send_single)(struct irq_data *data, unsigned int cpu); |
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| 523 | 549 | void (*ipi_send_mask)(struct irq_data *data, const struct cpumask *dest); |
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| 524 | 550 | |
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| 551 | + int (*irq_nmi_setup)(struct irq_data *data); |
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| 552 | + void (*irq_nmi_teardown)(struct irq_data *data); |
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| 553 | + |
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| 525 | 554 | unsigned long flags; |
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| 526 | 555 | }; |
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| 527 | 556 | |
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| 528 | 557 | /* |
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| 529 | 558 | * irq_chip specific flags |
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| 530 | 559 | * |
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| 531 | | - * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type() |
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| 532 | | - * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled |
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| 533 | | - * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path |
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| 534 | | - * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks |
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| 535 | | - * when irq enabled |
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| 536 | | - * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip |
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| 537 | | - * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask |
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| 538 | | - * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode |
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| 539 | | - * IRQCHIP_SUPPORTS_LEVEL_MSI Chip can provide two doorbells for Level MSIs |
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| 560 | + * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type() |
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| 561 | + * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled |
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| 562 | + * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path |
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| 563 | + * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks |
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| 564 | + * when irq enabled |
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| 565 | + * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip |
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| 566 | + * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask |
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| 567 | + * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode |
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| 568 | + * IRQCHIP_SUPPORTS_LEVEL_MSI: Chip can provide two doorbells for Level MSIs |
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| 569 | + * IRQCHIP_SUPPORTS_NMI: Chip can deliver NMIs, only for root irqchips |
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| 570 | + * IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND: Invokes __enable_irq()/__disable_irq() for wake irqs |
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| 571 | + * in the suspend path if they are in disabled state |
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| 540 | 572 | * IRQCHIP_AFFINITY_PRE_STARTUP: Default affinity update before startup |
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| 541 | 573 | */ |
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| 542 | 574 | enum { |
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| 543 | | - IRQCHIP_SET_TYPE_MASKED = (1 << 0), |
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| 544 | | - IRQCHIP_EOI_IF_HANDLED = (1 << 1), |
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| 545 | | - IRQCHIP_MASK_ON_SUSPEND = (1 << 2), |
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| 546 | | - IRQCHIP_ONOFFLINE_ENABLED = (1 << 3), |
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| 547 | | - IRQCHIP_SKIP_SET_WAKE = (1 << 4), |
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| 548 | | - IRQCHIP_ONESHOT_SAFE = (1 << 5), |
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| 549 | | - IRQCHIP_EOI_THREADED = (1 << 6), |
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| 550 | | - IRQCHIP_SUPPORTS_LEVEL_MSI = (1 << 7), |
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| 551 | | - IRQCHIP_AFFINITY_PRE_STARTUP = (1 << 10), |
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| 575 | + IRQCHIP_SET_TYPE_MASKED = (1 << 0), |
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| 576 | + IRQCHIP_EOI_IF_HANDLED = (1 << 1), |
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| 577 | + IRQCHIP_MASK_ON_SUSPEND = (1 << 2), |
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| 578 | + IRQCHIP_ONOFFLINE_ENABLED = (1 << 3), |
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| 579 | + IRQCHIP_SKIP_SET_WAKE = (1 << 4), |
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| 580 | + IRQCHIP_ONESHOT_SAFE = (1 << 5), |
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| 581 | + IRQCHIP_EOI_THREADED = (1 << 6), |
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| 582 | + IRQCHIP_SUPPORTS_LEVEL_MSI = (1 << 7), |
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| 583 | + IRQCHIP_SUPPORTS_NMI = (1 << 8), |
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| 584 | + IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND = (1 << 9), |
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| 585 | + IRQCHIP_AFFINITY_PRE_STARTUP = (1 << 10), |
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| 552 | 586 | }; |
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| 553 | 587 | |
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| 554 | 588 | #include <linux/irqdesc.h> |
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| .. | .. |
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| 569 | 603 | #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS |
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| 570 | 604 | |
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| 571 | 605 | struct irqaction; |
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| 572 | | -extern int setup_irq(unsigned int irq, struct irqaction *new); |
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| 573 | | -extern void remove_irq(unsigned int irq, struct irqaction *act); |
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| 574 | 606 | extern int setup_percpu_irq(unsigned int irq, struct irqaction *new); |
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| 575 | 607 | extern void remove_percpu_irq(unsigned int irq, struct irqaction *act); |
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| 576 | 608 | |
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| .. | .. |
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| 619 | 651 | */ |
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| 620 | 652 | extern void handle_level_irq(struct irq_desc *desc); |
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| 621 | 653 | extern void handle_fasteoi_irq(struct irq_desc *desc); |
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| 654 | +extern void handle_percpu_devid_fasteoi_ipi(struct irq_desc *desc); |
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| 622 | 655 | extern void handle_edge_irq(struct irq_desc *desc); |
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| 623 | 656 | extern void handle_edge_eoi_irq(struct irq_desc *desc); |
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| 624 | 657 | extern void handle_simple_irq(struct irq_desc *desc); |
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| .. | .. |
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| 627 | 660 | extern void handle_percpu_devid_irq(struct irq_desc *desc); |
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| 628 | 661 | extern void handle_bad_irq(struct irq_desc *desc); |
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| 629 | 662 | extern void handle_nested_irq(unsigned int irq); |
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| 663 | + |
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| 664 | +extern void handle_fasteoi_nmi(struct irq_desc *desc); |
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| 665 | +extern void handle_percpu_devid_fasteoi_nmi(struct irq_desc *desc); |
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| 630 | 666 | |
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| 631 | 667 | extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg); |
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| 632 | 668 | extern int irq_chip_pm_get(struct irq_data *data); |
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| .. | .. |
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| 645 | 681 | extern void irq_chip_ack_parent(struct irq_data *data); |
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| 646 | 682 | extern int irq_chip_retrigger_hierarchy(struct irq_data *data); |
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| 647 | 683 | extern void irq_chip_mask_parent(struct irq_data *data); |
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| 684 | +extern void irq_chip_mask_ack_parent(struct irq_data *data); |
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| 648 | 685 | extern void irq_chip_unmask_parent(struct irq_data *data); |
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| 649 | 686 | extern void irq_chip_eoi_parent(struct irq_data *data); |
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| 650 | 687 | extern int irq_chip_set_affinity_parent(struct irq_data *data, |
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| .. | .. |
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| 654 | 691 | extern int irq_chip_set_vcpu_affinity_parent(struct irq_data *data, |
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| 655 | 692 | void *vcpu_info); |
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| 656 | 693 | extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type); |
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| 694 | +extern int irq_chip_request_resources_parent(struct irq_data *data); |
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| 695 | +extern void irq_chip_release_resources_parent(struct irq_data *data); |
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| 657 | 696 | #endif |
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| 658 | 697 | |
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| 659 | 698 | /* Handling of unhandled and spurious interrupts: */ |
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| .. | .. |
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| 715 | 754 | void |
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| 716 | 755 | irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle, |
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| 717 | 756 | void *data); |
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| 757 | + |
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| 758 | +void __irq_modify_status(unsigned int irq, unsigned long clr, |
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| 759 | + unsigned long set, unsigned long mask); |
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| 718 | 760 | |
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| 719 | 761 | void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set); |
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| 720 | 762 | |
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| .. | .. |
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| 875 | 917 | unsigned int arch_dynirq_lower_bound(unsigned int from); |
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| 876 | 918 | |
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| 877 | 919 | int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node, |
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| 878 | | - struct module *owner, const struct cpumask *affinity); |
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| 920 | + struct module *owner, |
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| 921 | + const struct irq_affinity_desc *affinity); |
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| 879 | 922 | |
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| 880 | 923 | int __devm_irq_alloc_descs(struct device *dev, int irq, unsigned int from, |
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| 881 | 924 | unsigned int cnt, int node, struct module *owner, |
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| 882 | | - const struct cpumask *affinity); |
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| 925 | + const struct irq_affinity_desc *affinity); |
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| 883 | 926 | |
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| 884 | 927 | /* use macros to avoid needing export.h for THIS_MODULE */ |
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| 885 | 928 | #define irq_alloc_descs(irq, from, cnt, node) \ |
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| 886 | 929 | __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE, NULL) |
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| 887 | 930 | |
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| 888 | 931 | #define irq_alloc_desc(node) \ |
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| 889 | | - irq_alloc_descs(-1, 0, 1, node) |
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| 932 | + irq_alloc_descs(-1, 1, 1, node) |
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| 890 | 933 | |
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| 891 | 934 | #define irq_alloc_desc_at(at, node) \ |
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| 892 | 935 | irq_alloc_descs(at, at, 1, node) |
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| .. | .. |
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| 901 | 944 | __devm_irq_alloc_descs(dev, irq, from, cnt, node, THIS_MODULE, NULL) |
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| 902 | 945 | |
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| 903 | 946 | #define devm_irq_alloc_desc(dev, node) \ |
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| 904 | | - devm_irq_alloc_descs(dev, -1, 0, 1, node) |
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| 947 | + devm_irq_alloc_descs(dev, -1, 1, 1, node) |
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| 905 | 948 | |
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| 906 | 949 | #define devm_irq_alloc_desc_at(dev, at, node) \ |
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| 907 | 950 | devm_irq_alloc_descs(dev, at, at, 1, node) |
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| .. | .. |
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| 1032 | 1075 | unsigned long unused; |
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| 1033 | 1076 | struct irq_domain *domain; |
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| 1034 | 1077 | struct list_head list; |
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| 1035 | | - struct irq_chip_type chip_types[0]; |
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| 1078 | + struct irq_chip_type chip_types[]; |
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| 1036 | 1079 | }; |
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| 1037 | 1080 | |
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| 1038 | 1081 | /** |
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| .. | .. |
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| 1068 | 1111 | unsigned int irq_flags_to_clear; |
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| 1069 | 1112 | unsigned int irq_flags_to_set; |
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| 1070 | 1113 | enum irq_gc_flags gc_flags; |
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| 1071 | | - struct irq_chip_generic *gc[0]; |
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| 1114 | + struct irq_chip_generic *gc[]; |
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| 1072 | 1115 | }; |
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| 1073 | 1116 | |
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| 1074 | 1117 | /* Generic chip callback functions */ |
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| .. | .. |
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| 1230 | 1273 | * top-level IRQ handler. |
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| 1231 | 1274 | */ |
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| 1232 | 1275 | extern void (*handle_arch_irq)(struct pt_regs *) __ro_after_init; |
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| 1276 | +#else |
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| 1277 | +#define set_handle_irq(handle_irq) \ |
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| 1278 | + do { \ |
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| 1279 | + (void)handle_irq; \ |
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| 1280 | + WARN_ON(1); \ |
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| 1281 | + } while (0) |
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| 1233 | 1282 | #endif |
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| 1234 | 1283 | |
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| 1235 | 1284 | #endif /* _LINUX_IRQ_H */ |
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