| .. | .. |
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| 153 | 153 | u8 fixed_div; |
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| 154 | 154 | struct clk_omap_reg enable_reg; |
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| 155 | 155 | u8 enable_bit; |
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| 156 | | - u8 flags; |
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| 156 | + unsigned long flags; |
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| 157 | 157 | struct clk_omap_reg clksel_reg; |
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| 158 | 158 | struct dpll_data *dpll_data; |
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| 159 | 159 | const char *clkdm_name; |
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| 160 | 160 | struct clockdomain *clkdm; |
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| 161 | 161 | const struct clk_hw_omap_ops *ops; |
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| 162 | + u32 context; |
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| 163 | + int autoidle_count; |
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| 162 | 164 | }; |
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| 163 | 165 | |
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| 164 | 166 | /* |
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| .. | .. |
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| 241 | 243 | |
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| 242 | 244 | #define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw) |
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| 243 | 245 | |
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| 246 | +bool omap2_clk_is_hw_omap(struct clk_hw *hw); |
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| 244 | 247 | int omap2_clk_disable_autoidle_all(void); |
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| 245 | 248 | int omap2_clk_enable_autoidle_all(void); |
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| 246 | 249 | int omap2_clk_allow_idle(struct clk *clk); |
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| .. | .. |
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| 290 | 293 | #define TI_CLK_DPLL4_DENY_REPROGRAM BIT(1) |
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| 291 | 294 | #define TI_CLK_DISABLE_CLKDM_CONTROL BIT(2) |
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| 292 | 295 | #define TI_CLK_ERRATA_I810 BIT(3) |
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| 296 | +#define TI_CLK_CLKCTRL_COMPAT BIT(4) |
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| 297 | +#define TI_CLK_DEVICE_TYPE_GP BIT(5) |
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| 293 | 298 | |
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| 294 | 299 | void ti_clk_setup_features(struct ti_clk_features *features); |
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| 295 | 300 | const struct ti_clk_features *ti_clk_get_features(void); |
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| 301 | +bool ti_clk_is_in_standby(struct clk *clk); |
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| 302 | +int omap3_noncore_dpll_save_context(struct clk_hw *hw); |
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| 303 | +void omap3_noncore_dpll_restore_context(struct clk_hw *hw); |
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| 304 | + |
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| 305 | +int omap3_core_dpll_save_context(struct clk_hw *hw); |
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| 306 | +void omap3_core_dpll_restore_context(struct clk_hw *hw); |
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| 296 | 307 | |
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| 297 | 308 | extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll; |
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| 298 | 309 | |
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