disable kernel build waring

hc

2024-05-10 093a6c67005148ae32a5c9e4553491b9f5c2457b

 kernel/drivers/net/can/sja1000/plx_pci.c
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@@ -1,3 +1,4 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright (C) 2008-2010 Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>
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  *
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@@ -5,18 +6,6 @@
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  *	Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com>
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  *	Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com>
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  *	Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com>
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the version 2 of the GNU General Public License
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- * as published by the Free Software Foundation
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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- * GNU General Public License for more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program; if not, see <http://www.gnu.org/licenses/>.
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  */
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10
 
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 #include <linux/kernel.h>
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@@ -46,7 +35,8 @@
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 			"esd CAN-PCIe/2000, "
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 			"Connect Tech Inc. CANpro/104-Plus Opto (CRG001), "
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 			"IXXAT PC-I 04/PCI, "
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-			"ELCUS CAN-200-PCI")
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+			"ELCUS CAN-200-PCI, "
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+			"ASEM DUAL CAN-RAW")
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 MODULE_LICENSE("GPL v2");
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41
 
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 #define PLX_PCI_MAX_CHAN 2
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@@ -70,7 +60,9 @@
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 					 */
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61
 
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 #define PLX_LINT1_EN	0x1		/* Local interrupt 1 enable */
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+#define PLX_LINT1_POL	(1 << 1)	/* Local interrupt 1 polarity */
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 #define PLX_LINT2_EN	(1 << 3)	/* Local interrupt 2 enable */
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+#define PLX_LINT2_POL	(1 << 4)	/* Local interrupt 2 polarity */
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 #define PLX_PCI_INT_EN	(1 << 6)	/* PCI Interrupt Enable */
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 #define PLX_PCI_RESET	(1 << 30)	/* PCI Adapter Software Reset */
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68
 
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@@ -91,6 +83,9 @@
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  * This means normal output mode, push-pull and the correct polarity.
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  */
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 #define PLX_PCI_OCR	(OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL)
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+
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+/* OCR setting for ASEM Dual CAN raw */
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+#define ASEM_PCI_OCR	0xfe
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 /*
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  * In the CDR register, you should set CBP to 1.
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@@ -145,10 +140,20 @@
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 #define MOXA_PCI_VENDOR_ID		0x1393
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 #define MOXA_PCI_DEVICE_ID		0x0100
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+#define ASEM_RAW_CAN_VENDOR_ID		0x10b5
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+#define ASEM_RAW_CAN_DEVICE_ID		0x9030
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+#define ASEM_RAW_CAN_SUB_VENDOR_ID	0x3000
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+#define ASEM_RAW_CAN_SUB_DEVICE_ID	0x1001
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+#define ASEM_RAW_CAN_SUB_DEVICE_ID_BIS	0x1002
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+#define ASEM_RAW_CAN_RST_REGISTER	0x54
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+#define ASEM_RAW_CAN_RST_MASK_CAN1	0x20
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+#define ASEM_RAW_CAN_RST_MASK_CAN2	0x04
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+
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 static void plx_pci_reset_common(struct pci_dev *pdev);
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 static void plx9056_pci_reset_common(struct pci_dev *pdev);
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 static void plx_pci_reset_marathon_pci(struct pci_dev *pdev);
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 static void plx_pci_reset_marathon_pcie(struct pci_dev *pdev);
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+static void plx_pci_reset_asem_dual_can_raw(struct pci_dev *pdev);
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 struct plx_pci_channel_map {
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 	u32 bar;
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@@ -269,6 +274,14 @@
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 	 /* based on PLX9052 */
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 };
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+static struct plx_pci_card_info plx_pci_card_info_asem_dual_can = {
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+	"ASEM Dual CAN raw PCI", 2,
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+	PLX_PCI_CAN_CLOCK, ASEM_PCI_OCR, PLX_PCI_CDR,
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+	{0, 0x00, 0x00}, { {2, 0x00, 0x00}, {4, 0x00, 0x00} },
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+	&plx_pci_reset_asem_dual_can_raw
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+	/* based on PLX9030 */
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+};
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+
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 static const struct pci_device_id plx_pci_tbl[] = {
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 	{
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 		/* Adlink PCI-7841/cPCI-7841 */
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@@ -374,6 +387,20 @@
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 		PCI_ANY_ID, PCI_ANY_ID,
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 		0, 0,
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 		(kernel_ulong_t)&plx_pci_card_info_moxa
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+	},
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+	{
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+		/* ASEM Dual CAN raw */
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+		ASEM_RAW_CAN_VENDOR_ID, ASEM_RAW_CAN_DEVICE_ID,
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+		ASEM_RAW_CAN_SUB_VENDOR_ID, ASEM_RAW_CAN_SUB_DEVICE_ID,
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+		0, 0,
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+		(kernel_ulong_t)&plx_pci_card_info_asem_dual_can
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+	},
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+	{
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+		/* ASEM Dual CAN raw -new model */
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+		ASEM_RAW_CAN_VENDOR_ID, ASEM_RAW_CAN_DEVICE_ID,
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+		ASEM_RAW_CAN_SUB_VENDOR_ID, ASEM_RAW_CAN_SUB_DEVICE_ID_BIS,
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+		0, 0,
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+		(kernel_ulong_t)&plx_pci_card_info_asem_dual_can
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 	},
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 	{ 0,}
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 };
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@@ -524,6 +551,31 @@
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 	}
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 }
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+/* Special reset function for ASEM Dual CAN raw card */
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+static void plx_pci_reset_asem_dual_can_raw(struct pci_dev *pdev)
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+{
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+	void __iomem *bar0_addr;
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+	u8 tmpval;
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+
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+	plx_pci_reset_common(pdev);
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+
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+	bar0_addr = pci_iomap(pdev, 0, 0);
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+	if (!bar0_addr) {
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+		dev_err(&pdev->dev, "Failed to remap reset space 0 (BAR0)\n");
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+		return;
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+	}
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+
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+	/* reset the two SJA1000 chips */
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+	tmpval = ioread8(bar0_addr + ASEM_RAW_CAN_RST_REGISTER);
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+	tmpval &= ~(ASEM_RAW_CAN_RST_MASK_CAN1 | ASEM_RAW_CAN_RST_MASK_CAN2);
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+	iowrite8(tmpval, bar0_addr + ASEM_RAW_CAN_RST_REGISTER);
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+	usleep_range(300, 400);
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+	tmpval |= ASEM_RAW_CAN_RST_MASK_CAN1 | ASEM_RAW_CAN_RST_MASK_CAN2;
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+	iowrite8(tmpval, bar0_addr + ASEM_RAW_CAN_RST_REGISTER);
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+	usleep_range(300, 400);
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+	pci_iounmap(pdev, bar0_addr);
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+}
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+
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 static void plx_pci_del_card(struct pci_dev *pdev)
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 {
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 	struct plx_pci_card *card = pci_get_drvdata(pdev);