~hc/RK356X_SDK_RELEASE.git

..	..	@@ -4,7 +4,7 @@
4	4	*
5	5	* High-speed serial driver for NVIDIA Tegra SoCs
6	6	*
7		- * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
	7	+ * Copyright (c) 2012-2019, NVIDIA CORPORATION. All rights reserved.
8	8	*
9	9	* Author: Laxman Dewangan <ldewangan@nvidia.com>
10	10	*/
..	..	@@ -62,7 +62,7 @@
62	62	#define TEGRA_UART_TX_TRIG_4B 0x20
63	63	#define TEGRA_UART_TX_TRIG_1B 0x30
64	64
65		-#define TEGRA_UART_MAXIMUM 5
	65	+#define TEGRA_UART_MAXIMUM 8
66	66
67	67	/* Default UART setting when started: 115200 no parity, stop, 8 data bits */
68	68	#define TEGRA_UART_DEFAULT_BAUD 115200
..	..	@@ -71,6 +71,8 @@
71	71	/* Tx transfer mode */
72	72	#define TEGRA_TX_PIO 1
73	73	#define TEGRA_TX_DMA 2
	74	+
	75	+#define TEGRA_UART_FCR_IIR_FIFO_EN 0x40
74	76
75	77	/**
76	78	* tegra_uart_chip_data: SOC specific data.
..	..	@@ -84,6 +86,17 @@
84	86	bool tx_fifo_full_status;
85	87	bool allow_txfifo_reset_fifo_mode;
86	88	bool support_clk_src_div;
	89	+ bool fifo_mode_enable_status;
	90	+ int uart_max_port;
	91	+ int max_dma_burst_bytes;
	92	+ int error_tolerance_low_range;
	93	+ int error_tolerance_high_range;
	94	+};
	95	+
	96	+struct tegra_baud_tolerance {
	97	+ u32 lower_range_baud;
	98	+ u32 upper_range_baud;
	99	+ s32 tolerance;
87	100	};
88	101
89	102	struct tegra_uart_port {
..	..	@@ -122,10 +135,19 @@
122	135	dma_cookie_t rx_cookie;
123	136	unsigned int tx_bytes_requested;
124	137	unsigned int rx_bytes_requested;
	138	+ struct tegra_baud_tolerance *baud_tolerance;
	139	+ int n_adjustable_baud_rates;
	140	+ int required_rate;
	141	+ int configured_rate;
	142	+ bool use_rx_pio;
	143	+ bool use_tx_pio;
	144	+ bool rx_dma_active;
125	145	};
126	146
127	147	static void tegra_uart_start_next_tx(struct tegra_uart_port *tup);
128	148	static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup);
	149	+static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup,
	150	+ bool dma_to_memory);
129	151
130	152	static inline unsigned long tegra_uart_read(struct tegra_uart_port *tup,
131	153	unsigned long reg)
..	..	@@ -192,16 +214,34 @@
192	214	}
193	215	}
194	216
	217	+static void set_loopbk(struct tegra_uart_port *tup, bool active)
	218	+{
	219	+ unsigned long mcr = tup->mcr_shadow;
	220	+
	221	+ if (active)
	222	+ mcr \|= UART_MCR_LOOP;
	223	+ else
	224	+ mcr &= ~UART_MCR_LOOP;
	225	+
	226	+ if (mcr != tup->mcr_shadow) {
	227	+ tegra_uart_write(tup, mcr, UART_MCR);
	228	+ tup->mcr_shadow = mcr;
	229	+ }
	230	+}
	231	+
195	232	static void tegra_uart_set_mctrl(struct uart_port *u, unsigned int mctrl)
196	233	{
197	234	struct tegra_uart_port *tup = to_tegra_uport(u);
198		- int dtr_enable;
	235	+ int enable;
199	236
200	237	tup->rts_active = !!(mctrl & TIOCM_RTS);
201	238	set_rts(tup, tup->rts_active);
202	239
203		- dtr_enable = !!(mctrl & TIOCM_DTR);
204		- set_dtr(tup, dtr_enable);
	240	+ enable = !!(mctrl & TIOCM_DTR);
	241	+ set_dtr(tup, enable);
	242	+
	243	+ enable = !!(mctrl & TIOCM_LOOP);
	244	+ set_loopbk(tup, enable);
205	245	}
206	246
207	247	static void tegra_uart_break_ctl(struct uart_port *u, int break_ctl)
..	..	@@ -243,9 +283,28 @@
243	283	tup->current_baud));
244	284	}
245	285
	286	+static int tegra_uart_wait_fifo_mode_enabled(struct tegra_uart_port *tup)
	287	+{
	288	+ unsigned long iir;
	289	+ unsigned int tmout = 100;
	290	+
	291	+ do {
	292	+ iir = tegra_uart_read(tup, UART_IIR);
	293	+ if (iir & TEGRA_UART_FCR_IIR_FIFO_EN)
	294	+ return 0;
	295	+ udelay(1);
	296	+ } while (--tmout);
	297	+
	298	+ return -ETIMEDOUT;
	299	+}
	300	+
246	301	static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits)
247	302	{
248	303	unsigned long fcr = tup->fcr_shadow;
	304	+ unsigned int lsr, tmout = 10000;
	305	+
	306	+ if (tup->rts_active)
	307	+ set_rts(tup, false);
249	308
250	309	if (tup->cdata->allow_txfifo_reset_fifo_mode) {
251	310	fcr \|= fcr_bits & (UART_FCR_CLEAR_RCVR \| UART_FCR_CLEAR_XMIT);
..	..	@@ -258,6 +317,8 @@
258	317	tegra_uart_write(tup, fcr, UART_FCR);
259	318	fcr \|= UART_FCR_ENABLE_FIFO;
260	319	tegra_uart_write(tup, fcr, UART_FCR);
	320	+ if (tup->cdata->fifo_mode_enable_status)
	321	+ tegra_uart_wait_fifo_mode_enabled(tup);
261	322	}
262	323
263	324	/* Dummy read to ensure the write is posted */
..	..	@@ -269,6 +330,47 @@
269	330	* to propagate, otherwise data could be lost.
270	331	*/
271	332	tegra_uart_wait_cycle_time(tup, 32);
	333	+
	334	+ do {
	335	+ lsr = tegra_uart_read(tup, UART_LSR);
	336	+ if ((lsr & UART_LSR_TEMT) && !(lsr & UART_LSR_DR))
	337	+ break;
	338	+ udelay(1);
	339	+ } while (--tmout);
	340	+
	341	+ if (tup->rts_active)
	342	+ set_rts(tup, true);
	343	+}
	344	+
	345	+static long tegra_get_tolerance_rate(struct tegra_uart_port *tup,
	346	+ unsigned int baud, long rate)
	347	+{
	348	+ int i;
	349	+
	350	+ for (i = 0; i < tup->n_adjustable_baud_rates; ++i) {
	351	+ if (baud >= tup->baud_tolerance[i].lower_range_baud &&
	352	+ baud <= tup->baud_tolerance[i].upper_range_baud)
	353	+ return (rate + (rate *
	354	+ tup->baud_tolerance[i].tolerance) / 10000);
	355	+ }
	356	+
	357	+ return rate;
	358	+}
	359	+
	360	+static int tegra_check_rate_in_range(struct tegra_uart_port *tup)
	361	+{
	362	+ long diff;
	363	+
	364	+ diff = ((long)(tup->configured_rate - tup->required_rate) * 10000)
	365	+ / tup->required_rate;
	366	+ if (diff < (tup->cdata->error_tolerance_low_range * 100) \|\|
	367	+ diff > (tup->cdata->error_tolerance_high_range * 100)) {
	368	+ dev_err(tup->uport.dev,
	369	+ "configured baud rate is out of range by %ld", diff);
	370	+ return -EIO;
	371	+ }
	372	+
	373	+ return 0;
272	374	}
273	375
274	376	static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud)
..	..	@@ -276,6 +378,7 @@
276	378	unsigned long rate;
277	379	unsigned int divisor;
278	380	unsigned long lcr;
	381	+ unsigned long flags;
279	382	int ret;
280	383
281	384	if (tup->current_baud == baud)
..	..	@@ -283,18 +386,28 @@
283	386
284	387	if (tup->cdata->support_clk_src_div) {
285	388	rate = baud * 16;
	389	+ tup->required_rate = rate;
	390	+
	391	+ if (tup->n_adjustable_baud_rates)
	392	+ rate = tegra_get_tolerance_rate(tup, baud, rate);
	393	+
286	394	ret = clk_set_rate(tup->uart_clk, rate);
287	395	if (ret < 0) {
288	396	dev_err(tup->uport.dev,
289	397	"clk_set_rate() failed for rate %lu\n", rate);
290	398	return ret;
291	399	}
	400	+ tup->configured_rate = clk_get_rate(tup->uart_clk);
292	401	divisor = 1;
	402	+ ret = tegra_check_rate_in_range(tup);
	403	+ if (ret < 0)
	404	+ return ret;
293	405	} else {
294	406	rate = clk_get_rate(tup->uart_clk);
295	407	divisor = DIV_ROUND_CLOSEST(rate, baud * 16);
296	408	}
297	409
	410	+ spin_lock_irqsave(&tup->uport.lock, flags);
298	411	lcr = tup->lcr_shadow;
299	412	lcr \|= UART_LCR_DLAB;
300	413	tegra_uart_write(tup, lcr, UART_LCR);
..	..	@@ -307,6 +420,7 @@
307	420
308	421	/* Dummy read to ensure the write is posted */
309	422	tegra_uart_read(tup, UART_SCR);
	423	+ spin_unlock_irqrestore(&tup->uport.lock, flags);
310	424
311	425	tup->current_baud = baud;
312	426
..	..	@@ -325,24 +439,32 @@
325	439	/* Overrrun error */
326	440	flag = TTY_OVERRUN;
327	441	tup->uport.icount.overrun++;
328		- dev_err(tup->uport.dev, "Got overrun errors\n");
	442	+ dev_dbg(tup->uport.dev, "Got overrun errors\n");
329	443	} else if (lsr & UART_LSR_PE) {
330	444	/* Parity error */
331	445	flag = TTY_PARITY;
332	446	tup->uport.icount.parity++;
333		- dev_err(tup->uport.dev, "Got Parity errors\n");
	447	+ dev_dbg(tup->uport.dev, "Got Parity errors\n");
334	448	} else if (lsr & UART_LSR_FE) {
335	449	flag = TTY_FRAME;
336	450	tup->uport.icount.frame++;
337		- dev_err(tup->uport.dev, "Got frame errors\n");
	451	+ dev_dbg(tup->uport.dev, "Got frame errors\n");
338	452	} else if (lsr & UART_LSR_BI) {
339		- dev_err(tup->uport.dev, "Got Break\n");
340		- tup->uport.icount.brk++;
341		- /* If FIFO read error without any data, reset Rx FIFO */
	453	+ /*
	454	+ * Break error
	455	+ * If FIFO read error without any data, reset Rx FIFO
	456	+ */
342	457	if (!(lsr & UART_LSR_DR) && (lsr & UART_LSR_FIFOE))
343	458	tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_RCVR);
	459	+ if (tup->uport.ignore_status_mask & UART_LSR_BI)
	460	+ return TTY_BREAK;
	461	+ flag = TTY_BREAK;
	462	+ tup->uport.icount.brk++;
	463	+ dev_dbg(tup->uport.dev, "Got Break\n");
344	464	}
	465	+ uart_insert_char(&tup->uport, lsr, UART_LSR_OE, 0, flag);
345	466	}
	467	+
346	468	return flag;
347	469	}
348	470
..	..	@@ -398,7 +520,7 @@
398	520	count = tup->tx_bytes_requested - state.residue;
399	521	async_tx_ack(tup->tx_dma_desc);
400	522	spin_lock_irqsave(&tup->uport.lock, flags);
401		- xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
	523	+ uart_xmit_advance(&tup->uport, count);
402	524	tup->tx_in_progress = 0;
403	525	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
404	526	uart_write_wakeup(&tup->uport);
..	..	@@ -412,11 +534,12 @@
412	534	struct circ_buf *xmit = &tup->uport.state->xmit;
413	535	dma_addr_t tx_phys_addr;
414	536
415		- dma_sync_single_for_device(tup->uport.dev, tup->tx_dma_buf_phys,
416		- UART_XMIT_SIZE, DMA_TO_DEVICE);
417		-
418	537	tup->tx_bytes = count & ~(0xF);
419	538	tx_phys_addr = tup->tx_dma_buf_phys + xmit->tail;
	539	+
	540	+ dma_sync_single_for_device(tup->uport.dev, tx_phys_addr,
	541	+ tup->tx_bytes, DMA_TO_DEVICE);
	542	+
420	543	tup->tx_dma_desc = dmaengine_prep_slave_single(tup->tx_dma_chan,
421	544	tx_phys_addr, tup->tx_bytes, DMA_MEM_TO_DEV,
422	545	DMA_PREP_INTERRUPT);
..	..	@@ -440,12 +563,15 @@
440	563	unsigned long count;
441	564	struct circ_buf *xmit = &tup->uport.state->xmit;
442	565
	566	+ if (!tup->current_baud)
	567	+ return;
	568	+
443	569	tail = (unsigned long)&xmit->buf[xmit->tail];
444	570	count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
445	571	if (!count)
446	572	return;
447	573
448		- if (count < TEGRA_UART_MIN_DMA)
	574	+ if (tup->use_tx_pio \|\| count < TEGRA_UART_MIN_DMA)
449	575	tegra_uart_start_pio_tx(tup, count);
450	576	else if (BYTES_TO_ALIGN(tail) > 0)
451	577	tegra_uart_start_pio_tx(tup, BYTES_TO_ALIGN(tail));
..	..	@@ -482,7 +608,6 @@
482	608	static void tegra_uart_stop_tx(struct uart_port *u)
483	609	{
484	610	struct tegra_uart_port *tup = to_tegra_uport(u);
485		- struct circ_buf *xmit = &tup->uport.state->xmit;
486	611	struct dma_tx_state state;
487	612	unsigned int count;
488	613
..	..	@@ -493,7 +618,7 @@
493	618	dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state);
494	619	count = tup->tx_bytes_requested - state.residue;
495	620	async_tx_ack(tup->tx_dma_desc);
496		- xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
	621	+ uart_xmit_advance(&tup->uport, count);
497	622	tup->tx_in_progress = 0;
498	623	}
499	624
..	..	@@ -509,7 +634,7 @@
509	634	}
510	635
511	636	static void tegra_uart_handle_rx_pio(struct tegra_uart_port *tup,
512		- struct tty_port *tty)
	637	+ struct tty_port *port)
513	638	{
514	639	do {
515	640	char flag = TTY_NORMAL;
..	..	@@ -521,16 +646,24 @@
521	646	break;
522	647
523	648	flag = tegra_uart_decode_rx_error(tup, lsr);
	649	+ if (flag != TTY_NORMAL)
	650	+ continue;
	651	+
524	652	ch = (unsigned char) tegra_uart_read(tup, UART_RX);
525	653	tup->uport.icount.rx++;
526	654
527		- if (!uart_handle_sysrq_char(&tup->uport, ch) && tty)
528		- tty_insert_flip_char(tty, ch, flag);
	655	+ if (uart_handle_sysrq_char(&tup->uport, ch))
	656	+ continue;
	657	+
	658	+ if (tup->uport.ignore_status_mask & UART_LSR_DR)
	659	+ continue;
	660	+
	661	+ tty_insert_flip_char(port, ch, flag);
529	662	} while (1);
530	663	}
531	664
532	665	static void tegra_uart_copy_rx_to_tty(struct tegra_uart_port *tup,
533		- struct tty_port *tty,
	666	+ struct tty_port *port,
534	667	unsigned int count)
535	668	{
536	669	int copied;
..	..	@@ -540,27 +673,38 @@
540	673	return;
541	674
542	675	tup->uport.icount.rx += count;
543		- if (!tty) {
544		- dev_err(tup->uport.dev, "No tty port\n");
	676	+
	677	+ if (tup->uport.ignore_status_mask & UART_LSR_DR)
545	678	return;
546		- }
	679	+
547	680	dma_sync_single_for_cpu(tup->uport.dev, tup->rx_dma_buf_phys,
548		- TEGRA_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
549		- copied = tty_insert_flip_string(tty,
	681	+ count, DMA_FROM_DEVICE);
	682	+ copied = tty_insert_flip_string(port,
550	683	((unsigned char *)(tup->rx_dma_buf_virt)), count);
551	684	if (copied != count) {
552	685	WARN_ON(1);
553	686	dev_err(tup->uport.dev, "RxData copy to tty layer failed\n");
554	687	}
555	688	dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys,
556		- TEGRA_UART_RX_DMA_BUFFER_SIZE, DMA_TO_DEVICE);
	689	+ count, DMA_TO_DEVICE);
	690	+}
	691	+
	692	+static void do_handle_rx_pio(struct tegra_uart_port *tup)
	693	+{
	694	+ struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port);
	695	+ struct tty_port *port = &tup->uport.state->port;
	696	+
	697	+ tegra_uart_handle_rx_pio(tup, port);
	698	+ if (tty) {
	699	+ tty_flip_buffer_push(port);
	700	+ tty_kref_put(tty);
	701	+ }
557	702	}
558	703
559	704	static void tegra_uart_rx_buffer_push(struct tegra_uart_port *tup,
560	705	unsigned int residue)
561	706	{
562	707	struct tty_port *port = &tup->uport.state->port;
563		- struct tty_struct *tty = tty_port_tty_get(port);
564	708	unsigned int count;
565	709
566	710	async_tx_ack(tup->rx_dma_desc);
..	..	@@ -569,11 +713,7 @@
569	713	/* If we are here, DMA is stopped */
570	714	tegra_uart_copy_rx_to_tty(tup, port, count);
571	715
572		- tegra_uart_handle_rx_pio(tup, port);
573		- if (tty) {
574		- tty_flip_buffer_push(port);
575		- tty_kref_put(tty);
576		- }
	716	+ do_handle_rx_pio(tup);
577	717	}
578	718
579	719	static void tegra_uart_rx_dma_complete(void *args)
..	..	@@ -597,6 +737,7 @@
597	737	if (tup->rts_active)
598	738	set_rts(tup, false);
599	739
	740	+ tup->rx_dma_active = false;
600	741	tegra_uart_rx_buffer_push(tup, 0);
601	742	tegra_uart_start_rx_dma(tup);
602	743
..	..	@@ -608,18 +749,29 @@
608	749	spin_unlock_irqrestore(&u->lock, flags);
609	750	}
610	751
611		-static void tegra_uart_handle_rx_dma(struct tegra_uart_port *tup)
	752	+static void tegra_uart_terminate_rx_dma(struct tegra_uart_port *tup)
612	753	{
613	754	struct dma_tx_state state;
614	755
	756	+ if (!tup->rx_dma_active) {
	757	+ do_handle_rx_pio(tup);
	758	+ return;
	759	+ }
	760	+
	761	+ dmaengine_terminate_all(tup->rx_dma_chan);
	762	+ dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
	763	+
	764	+ tegra_uart_rx_buffer_push(tup, state.residue);
	765	+ tup->rx_dma_active = false;
	766	+}
	767	+
	768	+static void tegra_uart_handle_rx_dma(struct tegra_uart_port *tup)
	769	+{
615	770	/* Deactivate flow control to stop sender */
616	771	if (tup->rts_active)
617	772	set_rts(tup, false);
618	773
619		- dmaengine_terminate_all(tup->rx_dma_chan);
620		- dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
621		- tegra_uart_rx_buffer_push(tup, state.residue);
622		- tegra_uart_start_rx_dma(tup);
	774	+ tegra_uart_terminate_rx_dma(tup);
623	775
624	776	if (tup->rts_active)
625	777	set_rts(tup, true);
..	..	@@ -629,6 +781,9 @@
629	781	{
630	782	unsigned int count = TEGRA_UART_RX_DMA_BUFFER_SIZE;
631	783
	784	+ if (tup->rx_dma_active)
	785	+ return 0;
	786	+
632	787	tup->rx_dma_desc = dmaengine_prep_slave_single(tup->rx_dma_chan,
633	788	tup->rx_dma_buf_phys, count, DMA_DEV_TO_MEM,
634	789	DMA_PREP_INTERRUPT);
..	..	@@ -637,10 +792,9 @@
637	792	return -EIO;
638	793	}
639	794
	795	+ tup->rx_dma_active = true;
640	796	tup->rx_dma_desc->callback = tegra_uart_rx_dma_complete;
641	797	tup->rx_dma_desc->callback_param = tup;
642		- dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys,
643		- count, DMA_TO_DEVICE);
644	798	tup->rx_bytes_requested = count;
645	799	tup->rx_cookie = dmaengine_submit(tup->rx_dma_desc);
646	800	dma_async_issue_pending(tup->rx_dma_chan);
..	..	@@ -674,6 +828,7 @@
674	828	struct uart_port *u = &tup->uport;
675	829	unsigned long iir;
676	830	unsigned long ier;
	831	+ bool is_rx_start = false;
677	832	bool is_rx_int = false;
678	833	unsigned long flags;
679	834
..	..	@@ -681,15 +836,17 @@
681	836	while (1) {
682	837	iir = tegra_uart_read(tup, UART_IIR);
683	838	if (iir & UART_IIR_NO_INT) {
684		- if (is_rx_int) {
	839	+ if (!tup->use_rx_pio && is_rx_int) {
685	840	tegra_uart_handle_rx_dma(tup);
686	841	if (tup->rx_in_progress) {
687	842	ier = tup->ier_shadow;
688	843	ier \|= (UART_IER_RLSI \| UART_IER_RTOIE \|
689		- TEGRA_UART_IER_EORD);
	844	+ TEGRA_UART_IER_EORD \| UART_IER_RDI);
690	845	tup->ier_shadow = ier;
691	846	tegra_uart_write(tup, ier, UART_IER);
692	847	}
	848	+ } else if (is_rx_start) {
	849	+ tegra_uart_start_rx_dma(tup);
693	850	}
694	851	spin_unlock_irqrestore(&u->lock, flags);
695	852	return IRQ_HANDLED;
..	..	@@ -708,17 +865,25 @@
708	865
709	866	case 4: /* End of data */
710	867	case 6: /* Rx timeout */
711		- case 2: /* Receive */
712		- if (!is_rx_int) {
713		- is_rx_int = true;
	868	+ if (!tup->use_rx_pio) {
	869	+ is_rx_int = tup->rx_in_progress;
714	870	/* Disable Rx interrupts */
715	871	ier = tup->ier_shadow;
716		- ier \|= UART_IER_RDI;
717		- tegra_uart_write(tup, ier, UART_IER);
718	872	ier &= ~(UART_IER_RDI \| UART_IER_RLSI \|
719	873	UART_IER_RTOIE \| TEGRA_UART_IER_EORD);
720	874	tup->ier_shadow = ier;
721	875	tegra_uart_write(tup, ier, UART_IER);
	876	+ break;
	877	+ }
	878	+ fallthrough;
	879	+ case 2: /* Receive */
	880	+ if (!tup->use_rx_pio) {
	881	+ is_rx_start = tup->rx_in_progress;
	882	+ tup->ier_shadow &= ~UART_IER_RDI;
	883	+ tegra_uart_write(tup, tup->ier_shadow,
	884	+ UART_IER);
	885	+ } else {
	886	+ do_handle_rx_pio(tup);
722	887	}
723	888	break;
724	889
..	..	@@ -737,7 +902,7 @@
737	902	static void tegra_uart_stop_rx(struct uart_port *u)
738	903	{
739	904	struct tegra_uart_port *tup = to_tegra_uport(u);
740		- struct dma_tx_state state;
	905	+ struct tty_port *port = &tup->uport.state->port;
741	906	unsigned long ier;
742	907
743	908	if (tup->rts_active)
..	..	@@ -746,7 +911,7 @@
746	911	if (!tup->rx_in_progress)
747	912	return;
748	913
749		- tegra_uart_wait_sym_time(tup, 1); /* wait a character interval */
	914	+ tegra_uart_wait_sym_time(tup, 1); /* wait one character interval */
750	915
751	916	ier = tup->ier_shadow;
752	917	ier &= ~(UART_IER_RDI \| UART_IER_RLSI \| UART_IER_RTOIE \|
..	..	@@ -754,9 +919,11 @@
754	919	tup->ier_shadow = ier;
755	920	tegra_uart_write(tup, ier, UART_IER);
756	921	tup->rx_in_progress = 0;
757		- dmaengine_terminate_all(tup->rx_dma_chan);
758		- dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
759		- tegra_uart_rx_buffer_push(tup, state.residue);
	922	+
	923	+ if (!tup->use_rx_pio)
	924	+ tegra_uart_terminate_rx_dma(tup);
	925	+ else
	926	+ tegra_uart_handle_rx_pio(tup, port);
760	927	}
761	928
762	929	static void tegra_uart_hw_deinit(struct tegra_uart_port *tup)
..	..	@@ -804,6 +971,14 @@
804	971	tup->current_baud = 0;
805	972	spin_unlock_irqrestore(&tup->uport.lock, flags);
806	973
	974	+ tup->rx_in_progress = 0;
	975	+ tup->tx_in_progress = 0;
	976	+
	977	+ if (!tup->use_rx_pio)
	978	+ tegra_uart_dma_channel_free(tup, true);
	979	+ if (!tup->use_tx_pio)
	980	+ tegra_uart_dma_channel_free(tup, false);
	981	+
807	982	clk_disable_unprepare(tup->uart_clk);
808	983	}
809	984
..	..	@@ -846,34 +1021,55 @@
846	1021	* programmed in the DMA registers.
847	1022	*/
848	1023	tup->fcr_shadow = UART_FCR_ENABLE_FIFO;
849		- tup->fcr_shadow \|= UART_FCR_R_TRIG_01;
	1024	+
	1025	+ if (tup->use_rx_pio) {
	1026	+ tup->fcr_shadow \|= UART_FCR_R_TRIG_11;
	1027	+ } else {
	1028	+ if (tup->cdata->max_dma_burst_bytes == 8)
	1029	+ tup->fcr_shadow \|= UART_FCR_R_TRIG_10;
	1030	+ else
	1031	+ tup->fcr_shadow \|= UART_FCR_R_TRIG_01;
	1032	+ }
	1033	+
850	1034	tup->fcr_shadow \|= TEGRA_UART_TX_TRIG_16B;
851	1035	tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
852	1036
853	1037	/* Dummy read to ensure the write is posted */
854	1038	tegra_uart_read(tup, UART_SCR);
855	1039
856		- /*
857		- * For all tegra devices (up to t210), there is a hardware issue that
858		- * requires software to wait for 3 UART clock periods after enabling
859		- * the TX fifo, otherwise data could be lost.
860		- */
861		- tegra_uart_wait_cycle_time(tup, 3);
	1040	+ if (tup->cdata->fifo_mode_enable_status) {
	1041	+ ret = tegra_uart_wait_fifo_mode_enabled(tup);
	1042	+ if (ret < 0) {
	1043	+ dev_err(tup->uport.dev,
	1044	+ "Failed to enable FIFO mode: %d\n", ret);
	1045	+ return ret;
	1046	+ }
	1047	+ } else {
	1048	+ /*
	1049	+ * For all tegra devices (up to t210), there is a hardware
	1050	+ * issue that requires software to wait for 3 UART clock
	1051	+ * periods after enabling the TX fifo, otherwise data could
	1052	+ * be lost.
	1053	+ */
	1054	+ tegra_uart_wait_cycle_time(tup, 3);
	1055	+ }
862	1056
863	1057	/*
864	1058	* Initialize the UART with default configuration
865	1059	* (115200, N, 8, 1) so that the receive DMA buffer may be
866	1060	* enqueued
867	1061	*/
868		- tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR;
869		- tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD);
870		- tup->fcr_shadow \|= UART_FCR_DMA_SELECT;
871		- tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
872		-
873		- ret = tegra_uart_start_rx_dma(tup);
	1062	+ ret = tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD);
874	1063	if (ret < 0) {
875		- dev_err(tup->uport.dev, "Not able to start Rx DMA\n");
	1064	+ dev_err(tup->uport.dev, "Failed to set baud rate\n");
876	1065	return ret;
	1066	+ }
	1067	+ if (!tup->use_rx_pio) {
	1068	+ tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR;
	1069	+ tup->fcr_shadow \|= UART_FCR_DMA_SELECT;
	1070	+ tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
	1071	+ } else {
	1072	+ tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
877	1073	}
878	1074	tup->rx_in_progress = 1;
879	1075
..	..	@@ -881,13 +1077,9 @@
881	1077	* Enable IE_RXS for the receive status interrupts like line errros.
882	1078	* Enable IE_RX_TIMEOUT to get the bytes which cannot be DMA'd.
883	1079	*
884		- * If using DMA mode, enable EORD instead of receive interrupt which
885		- * will interrupt after the UART is done with the receive instead of
886		- * the interrupt when the FIFO "threshold" is reached.
887		- *
888	1080	* EORD is different interrupt than RX_TIMEOUT - RX_TIMEOUT occurs when
889	1081	* the DATA is sitting in the FIFO and couldn't be transferred to the
890		- * DMA as the DMA size alignment(4 bytes) is not met. EORD will be
	1082	+ * DMA as the DMA size alignment (4 bytes) is not met. EORD will be
891	1083	* triggered when there is a pause of the incomming data stream for 4
892	1084	* characters long.
893	1085	*
..	..	@@ -895,7 +1087,15 @@
895	1087	* both the EORD as well as RX_TIMEOUT - SW sees RX_TIMEOUT first
896	1088	* then the EORD.
897	1089	*/
898		- tup->ier_shadow = UART_IER_RLSI \| UART_IER_RTOIE \| TEGRA_UART_IER_EORD;
	1090	+ tup->ier_shadow = UART_IER_RLSI \| UART_IER_RTOIE \| UART_IER_RDI;
	1091	+
	1092	+ /*
	1093	+ * If using DMA mode, enable EORD interrupt to notify about RX
	1094	+ * completion.
	1095	+ */
	1096	+ if (!tup->use_rx_pio)
	1097	+ tup->ier_shadow \|= TEGRA_UART_IER_EORD;
	1098	+
899	1099	tegra_uart_write(tup, tup->ier_shadow, UART_IER);
900	1100	return 0;
901	1101	}
..	..	@@ -931,8 +1131,7 @@
931	1131	int ret;
932	1132	struct dma_slave_config dma_sconfig;
933	1133
934		- dma_chan = dma_request_slave_channel_reason(tup->uport.dev,
935		- dma_to_memory ? "rx" : "tx");
	1134	+ dma_chan = dma_request_chan(tup->uport.dev, dma_to_memory ? "rx" : "tx");
936	1135	if (IS_ERR(dma_chan)) {
937	1136	ret = PTR_ERR(dma_chan);
938	1137	dev_err(tup->uport.dev,
..	..	@@ -950,9 +1149,12 @@
950	1149	dma_release_channel(dma_chan);
951	1150	return -ENOMEM;
952	1151	}
	1152	+ dma_sync_single_for_device(tup->uport.dev, dma_phys,
	1153	+ TEGRA_UART_RX_DMA_BUFFER_SIZE,
	1154	+ DMA_TO_DEVICE);
953	1155	dma_sconfig.src_addr = tup->uport.mapbase;
954	1156	dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
955		- dma_sconfig.src_maxburst = 4;
	1157	+ dma_sconfig.src_maxburst = tup->cdata->max_dma_burst_bytes;
956	1158	tup->rx_dma_chan = dma_chan;
957	1159	tup->rx_dma_buf_virt = dma_buf;
958	1160	tup->rx_dma_buf_phys = dma_phys;
..	..	@@ -990,16 +1192,22 @@
990	1192	struct tegra_uart_port *tup = to_tegra_uport(u);
991	1193	int ret;
992	1194
993		- ret = tegra_uart_dma_channel_allocate(tup, false);
994		- if (ret < 0) {
995		- dev_err(u->dev, "Tx Dma allocation failed, err = %d\n", ret);
996		- return ret;
	1195	+ if (!tup->use_tx_pio) {
	1196	+ ret = tegra_uart_dma_channel_allocate(tup, false);
	1197	+ if (ret < 0) {
	1198	+ dev_err(u->dev, "Tx Dma allocation failed, err = %d\n",
	1199	+ ret);
	1200	+ return ret;
	1201	+ }
997	1202	}
998	1203
999		- ret = tegra_uart_dma_channel_allocate(tup, true);
1000		- if (ret < 0) {
1001		- dev_err(u->dev, "Rx Dma allocation failed, err = %d\n", ret);
1002		- goto fail_rx_dma;
	1204	+ if (!tup->use_rx_pio) {
	1205	+ ret = tegra_uart_dma_channel_allocate(tup, true);
	1206	+ if (ret < 0) {
	1207	+ dev_err(u->dev, "Rx Dma allocation failed, err = %d\n",
	1208	+ ret);
	1209	+ goto fail_rx_dma;
	1210	+ }
1003	1211	}
1004	1212
1005	1213	ret = tegra_uart_hw_init(tup);
..	..	@@ -1017,9 +1225,11 @@
1017	1225	return 0;
1018	1226
1019	1227	fail_hw_init:
1020		- tegra_uart_dma_channel_free(tup, true);
	1228	+ if (!tup->use_rx_pio)
	1229	+ tegra_uart_dma_channel_free(tup, true);
1021	1230	fail_rx_dma:
1022		- tegra_uart_dma_channel_free(tup, false);
	1231	+ if (!tup->use_tx_pio)
	1232	+ tegra_uart_dma_channel_free(tup, false);
1023	1233	return ret;
1024	1234	}
1025	1235
..	..	@@ -1041,12 +1251,6 @@
1041	1251	struct tegra_uart_port *tup = to_tegra_uport(u);
1042	1252
1043	1253	tegra_uart_hw_deinit(tup);
1044		-
1045		- tup->rx_in_progress = 0;
1046		- tup->tx_in_progress = 0;
1047		-
1048		- tegra_uart_dma_channel_free(tup, true);
1049		- tegra_uart_dma_channel_free(tup, false);
1050	1254	free_irq(u->irq, tup);
1051	1255	}
1052	1256
..	..	@@ -1071,6 +1275,7 @@
1071	1275	struct clk *parent_clk = clk_get_parent(tup->uart_clk);
1072	1276	unsigned long parent_clk_rate = clk_get_rate(parent_clk);
1073	1277	int max_divider = (tup->cdata->support_clk_src_div) ? 0x7FFF : 0xFFFF;
	1278	+ int ret;
1074	1279
1075	1280	max_divider *= 16;
1076	1281	spin_lock_irqsave(&u->lock, flags);
..	..	@@ -1079,7 +1284,7 @@
1079	1284	if (tup->rts_active)
1080	1285	set_rts(tup, false);
1081	1286
1082		- /* Clear all interrupts as configuration is going to be change */
	1287	+ /* Clear all interrupts as configuration is going to be changed */
1083	1288	tegra_uart_write(tup, tup->ier_shadow \| UART_IER_RDI, UART_IER);
1084	1289	tegra_uart_read(tup, UART_IER);
1085	1290	tegra_uart_write(tup, 0, UART_IER);
..	..	@@ -1143,7 +1348,11 @@
1143	1348	parent_clk_rate/max_divider,
1144	1349	parent_clk_rate/16);
1145	1350	spin_unlock_irqrestore(&u->lock, flags);
1146		- tegra_set_baudrate(tup, baud);
	1351	+ ret = tegra_set_baudrate(tup, baud);
	1352	+ if (ret < 0) {
	1353	+ dev_err(tup->uport.dev, "Failed to set baud rate\n");
	1354	+ return;
	1355	+ }
1147	1356	if (tty_termios_baud_rate(termios))
1148	1357	tty_termios_encode_baud_rate(termios, baud, baud);
1149	1358	spin_lock_irqsave(&u->lock, flags);
..	..	@@ -1165,12 +1374,19 @@
1165	1374	/* update the port timeout based on new settings */
1166	1375	uart_update_timeout(u, termios->c_cflag, baud);
1167	1376
1168		- /* Make sure all write has completed */
	1377	+ /* Make sure all writes have completed */
1169	1378	tegra_uart_read(tup, UART_IER);
1170	1379
1171		- /* Reenable interrupt */
	1380	+ /* Re-enable interrupt */
1172	1381	tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1173	1382	tegra_uart_read(tup, UART_IER);
	1383	+
	1384	+ tup->uport.ignore_status_mask = 0;
	1385	+ /* Ignore all characters if CREAD is not set */
	1386	+ if ((termios->c_cflag & CREAD) == 0)
	1387	+ tup->uport.ignore_status_mask \|= UART_LSR_DR;
	1388	+ if (termios->c_iflag & IGNBRK)
	1389	+ tup->uport.ignore_status_mask \|= UART_LSR_BI;
1174	1390
1175	1391	spin_unlock_irqrestore(&u->lock, flags);
1176	1392	}
..	..	@@ -1211,6 +1427,11 @@
1211	1427	{
1212	1428	struct device_node *np = pdev->dev.of_node;
1213	1429	int port;
	1430	+ int ret;
	1431	+ int index;
	1432	+ u32 pval;
	1433	+ int count;
	1434	+ int n_entries;
1214	1435
1215	1436	port = of_alias_get_id(np, "serial");
1216	1437	if (port < 0) {
..	..	@@ -1221,6 +1442,54 @@
1221	1442
1222	1443	tup->enable_modem_interrupt = of_property_read_bool(np,
1223	1444	"nvidia,enable-modem-interrupt");
	1445	+
	1446	+ index = of_property_match_string(np, "dma-names", "rx");
	1447	+ if (index < 0) {
	1448	+ tup->use_rx_pio = true;
	1449	+ dev_info(&pdev->dev, "RX in PIO mode\n");
	1450	+ }
	1451	+ index = of_property_match_string(np, "dma-names", "tx");
	1452	+ if (index < 0) {
	1453	+ tup->use_tx_pio = true;
	1454	+ dev_info(&pdev->dev, "TX in PIO mode\n");
	1455	+ }
	1456	+
	1457	+ n_entries = of_property_count_u32_elems(np, "nvidia,adjust-baud-rates");
	1458	+ if (n_entries > 0) {
	1459	+ tup->n_adjustable_baud_rates = n_entries / 3;
	1460	+ tup->baud_tolerance =
	1461	+ devm_kzalloc(&pdev->dev, (tup->n_adjustable_baud_rates) *
	1462	+ sizeof(*tup->baud_tolerance), GFP_KERNEL);
	1463	+ if (!tup->baud_tolerance)
	1464	+ return -ENOMEM;
	1465	+ for (count = 0, index = 0; count < n_entries; count += 3,
	1466	+ index++) {
	1467	+ ret =
	1468	+ of_property_read_u32_index(np,
	1469	+ "nvidia,adjust-baud-rates",
	1470	+ count, &pval);
	1471	+ if (!ret)
	1472	+ tup->baud_tolerance[index].lower_range_baud =
	1473	+ pval;
	1474	+ ret =
	1475	+ of_property_read_u32_index(np,
	1476	+ "nvidia,adjust-baud-rates",
	1477	+ count + 1, &pval);
	1478	+ if (!ret)
	1479	+ tup->baud_tolerance[index].upper_range_baud =
	1480	+ pval;
	1481	+ ret =
	1482	+ of_property_read_u32_index(np,
	1483	+ "nvidia,adjust-baud-rates",
	1484	+ count + 2, &pval);
	1485	+ if (!ret)
	1486	+ tup->baud_tolerance[index].tolerance =
	1487	+ (s32)pval;
	1488	+ }
	1489	+ } else {
	1490	+ tup->n_adjustable_baud_rates = 0;
	1491	+ }
	1492	+
1224	1493	return 0;
1225	1494	}
1226	1495
..	..	@@ -1228,12 +1497,44 @@
1228	1497	.tx_fifo_full_status = false,
1229	1498	.allow_txfifo_reset_fifo_mode = true,
1230	1499	.support_clk_src_div = false,
	1500	+ .fifo_mode_enable_status = false,
	1501	+ .uart_max_port = 5,
	1502	+ .max_dma_burst_bytes = 4,
	1503	+ .error_tolerance_low_range = -4,
	1504	+ .error_tolerance_high_range = 4,
1231	1505	};
1232	1506
1233	1507	static struct tegra_uart_chip_data tegra30_uart_chip_data = {
1234	1508	.tx_fifo_full_status = true,
1235	1509	.allow_txfifo_reset_fifo_mode = false,
1236	1510	.support_clk_src_div = true,
	1511	+ .fifo_mode_enable_status = false,
	1512	+ .uart_max_port = 5,
	1513	+ .max_dma_burst_bytes = 4,
	1514	+ .error_tolerance_low_range = -4,
	1515	+ .error_tolerance_high_range = 4,
	1516	+};
	1517	+
	1518	+static struct tegra_uart_chip_data tegra186_uart_chip_data = {
	1519	+ .tx_fifo_full_status = true,
	1520	+ .allow_txfifo_reset_fifo_mode = false,
	1521	+ .support_clk_src_div = true,
	1522	+ .fifo_mode_enable_status = true,
	1523	+ .uart_max_port = 8,
	1524	+ .max_dma_burst_bytes = 8,
	1525	+ .error_tolerance_low_range = 0,
	1526	+ .error_tolerance_high_range = 4,
	1527	+};
	1528	+
	1529	+static struct tegra_uart_chip_data tegra194_uart_chip_data = {
	1530	+ .tx_fifo_full_status = true,
	1531	+ .allow_txfifo_reset_fifo_mode = false,
	1532	+ .support_clk_src_div = true,
	1533	+ .fifo_mode_enable_status = true,
	1534	+ .uart_max_port = 8,
	1535	+ .max_dma_burst_bytes = 8,
	1536	+ .error_tolerance_low_range = -2,
	1537	+ .error_tolerance_high_range = 2,
1237	1538	};
1238	1539
1239	1540	static const struct of_device_id tegra_uart_of_match[] = {
..	..	@@ -1243,6 +1544,12 @@
1243	1544	}, {
1244	1545	.compatible = "nvidia,tegra20-hsuart",
1245	1546	.data = &tegra20_uart_chip_data,
	1547	+ }, {
	1548	+ .compatible = "nvidia,tegra186-hsuart",
	1549	+ .data = &tegra186_uart_chip_data,
	1550	+ }, {
	1551	+ .compatible = "nvidia,tegra194-hsuart",
	1552	+ .data = &tegra194_uart_chip_data,
1246	1553	}, {
1247	1554	},
1248	1555	};
..	..	@@ -1307,10 +1614,8 @@
1307	1614
1308	1615	u->iotype = UPIO_MEM32;
1309	1616	ret = platform_get_irq(pdev, 0);
1310		- if (ret < 0) {
1311		- dev_err(&pdev->dev, "Couldn't get IRQ\n");
	1617	+ if (ret < 0)
1312	1618	return ret;
1313		- }
1314	1619	u->irq = ret;
1315	1620	u->regshift = 2;
1316	1621	ret = uart_add_one_port(&tegra_uart_driver, u);
..	..	@@ -1365,11 +1670,22 @@
1365	1670	static int __init tegra_uart_init(void)
1366	1671	{
1367	1672	int ret;
	1673	+ struct device_node *node;
	1674	+ const struct of_device_id *match = NULL;
	1675	+ const struct tegra_uart_chip_data *cdata = NULL;
	1676	+
	1677	+ node = of_find_matching_node(NULL, tegra_uart_of_match);
	1678	+ if (node)
	1679	+ match = of_match_node(tegra_uart_of_match, node);
	1680	+ if (match)
	1681	+ cdata = match->data;
	1682	+ if (cdata)
	1683	+ tegra_uart_driver.nr = cdata->uart_max_port;
1368	1684
1369	1685	ret = uart_register_driver(&tegra_uart_driver);
1370	1686	if (ret < 0) {
1371	1687	pr_err("Could not register %s driver\n",
1372		- tegra_uart_driver.driver_name);
	1688	+ tegra_uart_driver.driver_name);
1373	1689	return ret;
1374	1690	}
1375	1691