~hc/RK356X_SDK_RELEASE.git

..	..	@@ -5,10 +5,6 @@
5	5	* Copyright 2012-2014 Freescale Semiconductor, Inc.
6	6	*/
7	7
8		-#if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
9		-#define SUPPORT_SYSRQ
10		-#endif
11		-
12	8	#include <linux/clk.h>
13	9	#include <linux/console.h>
14	10	#include <linux/dma-mapping.h>
..	..	@@ -214,6 +210,7 @@
214	210	#define UARTFIFO_TXSIZE_OFF 4
215	211	#define UARTFIFO_RXFE 0x00000008
216	212	#define UARTFIFO_RXSIZE_OFF 0
	213	+#define UARTFIFO_DEPTH(x) (0x1 << ((x) ? ((x) + 1) : 0))
217	214
218	215	#define UARTWATER_COUNT_MASK 0xff
219	216	#define UARTWATER_TXCNT_OFF 8
..	..	@@ -232,9 +229,19 @@
232	229	/* IMX lpuart has four extra unused regs located at the beginning */
233	230	#define IMX_REG_OFF 0x10
234	231
	232	+enum lpuart_type {
	233	+ VF610_LPUART,
	234	+ LS1021A_LPUART,
	235	+ LS1028A_LPUART,
	236	+ IMX7ULP_LPUART,
	237	+ IMX8QXP_LPUART,
	238	+};
	239	+
235	240	struct lpuart_port {
236	241	struct uart_port port;
237		- struct clk *clk;
	242	+ enum lpuart_type devtype;
	243	+ struct clk *ipg_clk;
	244	+ struct clk *baud_clk;
238	245	unsigned int txfifo_size;
239	246	unsigned int rxfifo_size;
240	247
..	..	@@ -259,33 +266,61 @@
259	266	};
260	267
261	268	struct lpuart_soc_data {
262		- char iotype;
263		- u8 reg_off;
	269	+ enum lpuart_type devtype;
	270	+ char iotype;
	271	+ u8 reg_off;
264	272	};
265	273
266	274	static const struct lpuart_soc_data vf_data = {
	275	+ .devtype = VF610_LPUART,
267	276	.iotype = UPIO_MEM,
268	277	};
269	278
270		-static const struct lpuart_soc_data ls_data = {
	279	+static const struct lpuart_soc_data ls1021a_data = {
	280	+ .devtype = LS1021A_LPUART,
271	281	.iotype = UPIO_MEM32BE,
272	282	};
273	283
274		-static struct lpuart_soc_data imx_data = {
	284	+static const struct lpuart_soc_data ls1028a_data = {
	285	+ .devtype = LS1028A_LPUART,
	286	+ .iotype = UPIO_MEM32,
	287	+};
	288	+
	289	+static struct lpuart_soc_data imx7ulp_data = {
	290	+ .devtype = IMX7ULP_LPUART,
	291	+ .iotype = UPIO_MEM32,
	292	+ .reg_off = IMX_REG_OFF,
	293	+};
	294	+
	295	+static struct lpuart_soc_data imx8qxp_data = {
	296	+ .devtype = IMX8QXP_LPUART,
275	297	.iotype = UPIO_MEM32,
276	298	.reg_off = IMX_REG_OFF,
277	299	};
278	300
279	301	static const struct of_device_id lpuart_dt_ids[] = {
280	302	{ .compatible = "fsl,vf610-lpuart", .data = &vf_data, },
281		- { .compatible = "fsl,ls1021a-lpuart", .data = &ls_data, },
282		- { .compatible = "fsl,imx7ulp-lpuart", .data = &imx_data, },
	303	+ { .compatible = "fsl,ls1021a-lpuart", .data = &ls1021a_data, },
	304	+ { .compatible = "fsl,ls1028a-lpuart", .data = &ls1028a_data, },
	305	+ { .compatible = "fsl,imx7ulp-lpuart", .data = &imx7ulp_data, },
	306	+ { .compatible = "fsl,imx8qxp-lpuart", .data = &imx8qxp_data, },
283	307	{ /* sentinel */ }
284	308	};
285	309	MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
286	310
287	311	/* Forward declare this for the dma callbacks*/
288	312	static void lpuart_dma_tx_complete(void *arg);
	313	+
	314	+static inline bool is_layerscape_lpuart(struct lpuart_port *sport)
	315	+{
	316	+ return (sport->devtype == LS1021A_LPUART \|\|
	317	+ sport->devtype == LS1028A_LPUART);
	318	+}
	319	+
	320	+static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport)
	321	+{
	322	+ return sport->devtype == IMX8QXP_LPUART;
	323	+}
289	324
290	325	static inline u32 lpuart32_read(struct uart_port *port, u32 off)
291	326	{
..	..	@@ -311,6 +346,39 @@
311	346	break;
312	347	}
313	348	}
	349	+
	350	+static int __lpuart_enable_clks(struct lpuart_port *sport, bool is_en)
	351	+{
	352	+ int ret = 0;
	353	+
	354	+ if (is_en) {
	355	+ ret = clk_prepare_enable(sport->ipg_clk);
	356	+ if (ret)
	357	+ return ret;
	358	+
	359	+ ret = clk_prepare_enable(sport->baud_clk);
	360	+ if (ret) {
	361	+ clk_disable_unprepare(sport->ipg_clk);
	362	+ return ret;
	363	+ }
	364	+ } else {
	365	+ clk_disable_unprepare(sport->baud_clk);
	366	+ clk_disable_unprepare(sport->ipg_clk);
	367	+ }
	368	+
	369	+ return 0;
	370	+}
	371	+
	372	+static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport)
	373	+{
	374	+ if (is_imx8qxp_lpuart(sport))
	375	+ return clk_get_rate(sport->baud_clk);
	376	+
	377	+ return clk_get_rate(sport->ipg_clk);
	378	+}
	379	+
	380	+#define lpuart_enable_clks(x) __lpuart_enable_clks(x, true)
	381	+#define lpuart_disable_clks(x) __lpuart_enable_clks(x, false)
314	382
315	383	static void lpuart_stop_tx(struct uart_port *port)
316	384	{
..	..	@@ -351,6 +419,7 @@
351	419	struct circ_buf *xmit = &sport->port.state->xmit;
352	420	struct scatterlist *sgl = sport->tx_sgl;
353	421	struct device *dev = sport->port.dev;
	422	+ struct dma_chan *chan = sport->dma_tx_chan;
354	423	int ret;
355	424
356	425	if (sport->dma_tx_in_progress)
..	..	@@ -369,17 +438,19 @@
369	438	sg_set_buf(sgl + 1, xmit->buf, xmit->head);
370	439	}
371	440
372		- ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
	441	+ ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents,
	442	+ DMA_TO_DEVICE);
373	443	if (!ret) {
374	444	dev_err(dev, "DMA mapping error for TX.\n");
375	445	return;
376	446	}
377	447
378		- sport->dma_tx_desc = dmaengine_prep_slave_sg(sport->dma_tx_chan, sgl,
	448	+ sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl,
379	449	ret, DMA_MEM_TO_DEV,
380	450	DMA_PREP_INTERRUPT);
381	451	if (!sport->dma_tx_desc) {
382		- dma_unmap_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
	452	+ dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents,
	453	+ DMA_TO_DEVICE);
383	454	dev_err(dev, "Cannot prepare TX slave DMA!\n");
384	455	return;
385	456	}
..	..	@@ -388,7 +459,12 @@
388	459	sport->dma_tx_desc->callback_param = sport;
389	460	sport->dma_tx_in_progress = true;
390	461	sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
391		- dma_async_issue_pending(sport->dma_tx_chan);
	462	+ dma_async_issue_pending(chan);
	463	+}
	464	+
	465	+static bool lpuart_stopped_or_empty(struct uart_port *port)
	466	+{
	467	+ return uart_circ_empty(&port->state->xmit) \|\| uart_tx_stopped(port);
392	468	}
393	469
394	470	static void lpuart_dma_tx_complete(void *arg)
..	..	@@ -396,11 +472,13 @@
396	472	struct lpuart_port *sport = arg;
397	473	struct scatterlist *sgl = &sport->tx_sgl[0];
398	474	struct circ_buf *xmit = &sport->port.state->xmit;
	475	+ struct dma_chan *chan = sport->dma_tx_chan;
399	476	unsigned long flags;
400	477
401	478	spin_lock_irqsave(&sport->port.lock, flags);
402	479
403		- dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
	480	+ dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents,
	481	+ DMA_TO_DEVICE);
404	482
405	483	xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1);
406	484
..	..	@@ -418,10 +496,21 @@
418	496
419	497	spin_lock_irqsave(&sport->port.lock, flags);
420	498
421		- if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
	499	+ if (!lpuart_stopped_or_empty(&sport->port))
422	500	lpuart_dma_tx(sport);
423	501
424	502	spin_unlock_irqrestore(&sport->port.lock, flags);
	503	+}
	504	+
	505	+static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport)
	506	+{
	507	+ switch (sport->port.iotype) {
	508	+ case UPIO_MEM32:
	509	+ return sport->port.mapbase + UARTDATA;
	510	+ case UPIO_MEM32BE:
	511	+ return sport->port.mapbase + UARTDATA + sizeof(u32) - 1;
	512	+ }
	513	+ return sport->port.mapbase + UARTDR;
425	514	}
426	515
427	516	static int lpuart_dma_tx_request(struct uart_port *port)
..	..	@@ -431,7 +520,7 @@
431	520	struct dma_slave_config dma_tx_sconfig = {};
432	521	int ret;
433	522
434		- dma_tx_sconfig.dst_addr = sport->port.mapbase + UARTDR;
	523	+ dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport);
435	524	dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
436	525	dma_tx_sconfig.dst_maxburst = 1;
437	526	dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
..	..	@@ -446,18 +535,50 @@
446	535	return 0;
447	536	}
448	537
	538	+static bool lpuart_is_32(struct lpuart_port *sport)
	539	+{
	540	+ return sport->port.iotype == UPIO_MEM32 \|\|
	541	+ sport->port.iotype == UPIO_MEM32BE;
	542	+}
	543	+
449	544	static void lpuart_flush_buffer(struct uart_port *port)
450	545	{
451	546	struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
	547	+ struct dma_chan *chan = sport->dma_tx_chan;
	548	+ u32 val;
452	549
453	550	if (sport->lpuart_dma_tx_use) {
454	551	if (sport->dma_tx_in_progress) {
455		- dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
	552	+ dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0],
456	553	sport->dma_tx_nents, DMA_TO_DEVICE);
457	554	sport->dma_tx_in_progress = false;
458	555	}
459		- dmaengine_terminate_all(sport->dma_tx_chan);
	556	+ dmaengine_terminate_all(chan);
460	557	}
	558	+
	559	+ if (lpuart_is_32(sport)) {
	560	+ val = lpuart32_read(&sport->port, UARTFIFO);
	561	+ val \|= UARTFIFO_TXFLUSH \| UARTFIFO_RXFLUSH;
	562	+ lpuart32_write(&sport->port, val, UARTFIFO);
	563	+ } else {
	564	+ val = readb(sport->port.membase + UARTCFIFO);
	565	+ val \|= UARTCFIFO_TXFLUSH \| UARTCFIFO_RXFLUSH;
	566	+ writeb(val, sport->port.membase + UARTCFIFO);
	567	+ }
	568	+}
	569	+
	570	+static void lpuart_wait_bit_set(struct uart_port *port, unsigned int offset,
	571	+ u8 bit)
	572	+{
	573	+ while (!(readb(port->membase + offset) & bit))
	574	+ cpu_relax();
	575	+}
	576	+
	577	+static void lpuart32_wait_bit_set(struct uart_port *port, unsigned int offset,
	578	+ u32 bit)
	579	+{
	580	+ while (!(lpuart32_read(port, offset) & bit))
	581	+ cpu_relax();
461	582	}
462	583
463	584	#if defined(CONFIG_CONSOLE_POLL)
..	..	@@ -503,9 +624,7 @@
503	624	static void lpuart_poll_put_char(struct uart_port *port, unsigned char c)
504	625	{
505	626	/* drain */
506		- while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
507		- barrier();
508		-
	627	+ lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);
509	628	writeb(c, port->membase + UARTDR);
510	629	}
511	630
..	..	@@ -528,26 +647,24 @@
528	647	spin_lock_irqsave(&sport->port.lock, flags);
529	648
530	649	/* Disable Rx & Tx */
531		- lpuart32_write(&sport->port, UARTCTRL, 0);
	650	+ lpuart32_write(&sport->port, 0, UARTCTRL);
532	651
533	652	temp = lpuart32_read(&sport->port, UARTFIFO);
534	653
535	654	/* Enable Rx and Tx FIFO */
536		- lpuart32_write(&sport->port, UARTFIFO,
537		- temp \| UARTFIFO_RXFE \| UARTFIFO_TXFE);
	655	+ lpuart32_write(&sport->port, temp \| UARTFIFO_RXFE \| UARTFIFO_TXFE, UARTFIFO);
538	656
539	657	/* flush Tx and Rx FIFO */
540		- lpuart32_write(&sport->port, UARTFIFO,
541		- UARTFIFO_TXFLUSH \| UARTFIFO_RXFLUSH);
	658	+ lpuart32_write(&sport->port, UARTFIFO_TXFLUSH \| UARTFIFO_RXFLUSH, UARTFIFO);
542	659
543	660	/* explicitly clear RDRF */
544	661	if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) {
545	662	lpuart32_read(&sport->port, UARTDATA);
546		- lpuart32_write(&sport->port, UARTFIFO, UARTFIFO_RXUF);
	663	+ lpuart32_write(&sport->port, UARTFIFO_RXUF, UARTFIFO);
547	664	}
548	665
549	666	/* Enable Rx and Tx */
550		- lpuart32_write(&sport->port, UARTCTRL, UARTCTRL_RE \| UARTCTRL_TE);
	667	+ lpuart32_write(&sport->port, UARTCTRL_RE \| UARTCTRL_TE, UARTCTRL);
551	668	spin_unlock_irqrestore(&sport->port.lock, flags);
552	669
553	670	return 0;
..	..	@@ -555,10 +672,8 @@
555	672
556	673	static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c)
557	674	{
558		- while (!(lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE))
559		- barrier();
560		-
561		- lpuart32_write(port, UARTDATA, c);
	675	+ lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);
	676	+ lpuart32_write(port, c, UARTDATA);
562	677	}
563	678
564	679	static int lpuart32_poll_get_char(struct uart_port *port)
..	..	@@ -573,6 +688,18 @@
573	688	static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
574	689	{
575	690	struct circ_buf *xmit = &sport->port.state->xmit;
	691	+
	692	+ if (sport->port.x_char) {
	693	+ writeb(sport->port.x_char, sport->port.membase + UARTDR);
	694	+ sport->port.icount.tx++;
	695	+ sport->port.x_char = 0;
	696	+ return;
	697	+ }
	698	+
	699	+ if (lpuart_stopped_or_empty(&sport->port)) {
	700	+ lpuart_stop_tx(&sport->port);
	701	+ return;
	702	+ }
576	703
577	704	while (!uart_circ_empty(xmit) &&
578	705	(readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) {
..	..	@@ -592,6 +719,18 @@
592	719	{
593	720	struct circ_buf *xmit = &sport->port.state->xmit;
594	721	unsigned long txcnt;
	722	+
	723	+ if (sport->port.x_char) {
	724	+ lpuart32_write(&sport->port, sport->port.x_char, UARTDATA);
	725	+ sport->port.icount.tx++;
	726	+ sport->port.x_char = 0;
	727	+ return;
	728	+ }
	729	+
	730	+ if (lpuart_stopped_or_empty(&sport->port)) {
	731	+ lpuart32_stop_tx(&sport->port);
	732	+ return;
	733	+ }
595	734
596	735	txcnt = lpuart32_read(&sport->port, UARTWATER);
597	736	txcnt = txcnt >> UARTWATER_TXCNT_OFF;
..	..	@@ -616,14 +755,13 @@
616	755	{
617	756	struct lpuart_port *sport = container_of(port,
618	757	struct lpuart_port, port);
619		- struct circ_buf *xmit = &sport->port.state->xmit;
620	758	unsigned char temp;
621	759
622	760	temp = readb(port->membase + UARTCR2);
623	761	writeb(temp \| UARTCR2_TIE, port->membase + UARTCR2);
624	762
625	763	if (sport->lpuart_dma_tx_use) {
626		- if (!uart_circ_empty(xmit) && !uart_tx_stopped(port))
	764	+ if (!lpuart_stopped_or_empty(port))
627	765	lpuart_dma_tx(sport);
628	766	} else {
629	767	if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
..	..	@@ -636,11 +774,16 @@
636	774	struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
637	775	unsigned long temp;
638	776
639		- temp = lpuart32_read(port, UARTCTRL);
640		- lpuart32_write(port, temp \| UARTCTRL_TIE, UARTCTRL);
	777	+ if (sport->lpuart_dma_tx_use) {
	778	+ if (!lpuart_stopped_or_empty(port))
	779	+ lpuart_dma_tx(sport);
	780	+ } else {
	781	+ temp = lpuart32_read(port, UARTCTRL);
	782	+ lpuart32_write(port, temp \| UARTCTRL_TIE, UARTCTRL);
641	783
642		- if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE)
643		- lpuart32_transmit_buffer(sport);
	784	+ if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE)
	785	+ lpuart32_transmit_buffer(sport);
	786	+ }
644	787	}
645	788
646	789	/* return TIOCSER_TEMT when transmitter is not busy */
..	..	@@ -662,56 +805,32 @@
662	805
663	806	static unsigned int lpuart32_tx_empty(struct uart_port *port)
664	807	{
665		- return (lpuart32_read(port, UARTSTAT) & UARTSTAT_TC) ?
666		- TIOCSER_TEMT : 0;
	808	+ struct lpuart_port *sport = container_of(port,
	809	+ struct lpuart_port, port);
	810	+ unsigned long stat = lpuart32_read(port, UARTSTAT);
	811	+ unsigned long sfifo = lpuart32_read(port, UARTFIFO);
	812	+
	813	+ if (sport->dma_tx_in_progress)
	814	+ return 0;
	815	+
	816	+ if (stat & UARTSTAT_TC && sfifo & UARTFIFO_TXEMPT)
	817	+ return TIOCSER_TEMT;
	818	+
	819	+ return 0;
667	820	}
668	821
669		-static bool lpuart_is_32(struct lpuart_port *sport)
	822	+static void lpuart_txint(struct lpuart_port *sport)
670	823	{
671		- return sport->port.iotype == UPIO_MEM32 \|\|
672		- sport->port.iotype == UPIO_MEM32BE;
673		-}
674		-
675		-static irqreturn_t lpuart_txint(int irq, void *dev_id)
676		-{
677		- struct lpuart_port *sport = dev_id;
678		- struct circ_buf *xmit = &sport->port.state->xmit;
679	824	unsigned long flags;
680	825
681	826	spin_lock_irqsave(&sport->port.lock, flags);
682		- if (sport->port.x_char) {
683		- if (lpuart_is_32(sport))
684		- lpuart32_write(&sport->port, sport->port.x_char, UARTDATA);
685		- else
686		- writeb(sport->port.x_char, sport->port.membase + UARTDR);
687		- goto out;
688		- }
689		-
690		- if (uart_circ_empty(xmit) \|\| uart_tx_stopped(&sport->port)) {
691		- if (lpuart_is_32(sport))
692		- lpuart32_stop_tx(&sport->port);
693		- else
694		- lpuart_stop_tx(&sport->port);
695		- goto out;
696		- }
697		-
698		- if (lpuart_is_32(sport))
699		- lpuart32_transmit_buffer(sport);
700		- else
701		- lpuart_transmit_buffer(sport);
702		-
703		- if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
704		- uart_write_wakeup(&sport->port);
705		-
706		-out:
	827	+ lpuart_transmit_buffer(sport);
707	828	spin_unlock_irqrestore(&sport->port.lock, flags);
708		- return IRQ_HANDLED;
709	829	}
710	830
711		-static irqreturn_t lpuart_rxint(int irq, void *dev_id)
	831	+static void lpuart_rxint(struct lpuart_port *sport)
712	832	{
713		- struct lpuart_port *sport = dev_id;
714		- unsigned int flg, ignored = 0;
	833	+ unsigned int flg, ignored = 0, overrun = 0;
715	834	struct tty_port *port = &sport->port.state->port;
716	835	unsigned long flags;
717	836	unsigned char rx, sr;
..	..	@@ -738,7 +857,7 @@
738	857	sport->port.icount.frame++;
739	858
740	859	if (sr & UARTSR1_OR)
741		- sport->port.icount.overrun++;
	860	+ overrun++;
742	861
743	862	if (sr & sport->port.ignore_status_mask) {
744	863	if (++ignored > 100)
..	..	@@ -756,24 +875,40 @@
756	875	if (sr & UARTSR1_OR)
757	876	flg = TTY_OVERRUN;
758	877
759		-#ifdef SUPPORT_SYSRQ
760	878	sport->port.sysrq = 0;
761		-#endif
762	879	}
763	880
764	881	tty_insert_flip_char(port, rx, flg);
765	882	}
766	883
767	884	out:
	885	+ if (overrun) {
	886	+ sport->port.icount.overrun += overrun;
	887	+
	888	+ /*
	889	+ * Overruns cause FIFO pointers to become missaligned.
	890	+ * Flushing the receive FIFO reinitializes the pointers.
	891	+ */
	892	+ writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
	893	+ writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO);
	894	+ }
	895	+
768	896	spin_unlock_irqrestore(&sport->port.lock, flags);
769	897
770	898	tty_flip_buffer_push(port);
771		- return IRQ_HANDLED;
772	899	}
773	900
774		-static irqreturn_t lpuart32_rxint(int irq, void *dev_id)
	901	+static void lpuart32_txint(struct lpuart_port *sport)
775	902	{
776		- struct lpuart_port *sport = dev_id;
	903	+ unsigned long flags;
	904	+
	905	+ spin_lock_irqsave(&sport->port.lock, flags);
	906	+ lpuart32_transmit_buffer(sport);
	907	+ spin_unlock_irqrestore(&sport->port.lock, flags);
	908	+}
	909	+
	910	+static void lpuart32_rxint(struct lpuart_port *sport)
	911	+{
777	912	unsigned int flg, ignored = 0;
778	913	struct tty_port *port = &sport->port.state->port;
779	914	unsigned long flags;
..	..	@@ -820,9 +955,7 @@
820	955	if (sr & UARTSTAT_OR)
821	956	flg = TTY_OVERRUN;
822	957
823		-#ifdef SUPPORT_SYSRQ
824	958	sport->port.sysrq = 0;
825		-#endif
826	959	}
827	960
828	961	tty_insert_flip_char(port, rx, flg);
..	..	@@ -832,7 +965,6 @@
832	965	spin_unlock_irqrestore(&sport->port.lock, flags);
833	966
834	967	tty_flip_buffer_push(port);
835		- return IRQ_HANDLED;
836	968	}
837	969
838	970	static irqreturn_t lpuart_int(int irq, void *dev_id)
..	..	@@ -842,11 +974,20 @@
842	974
843	975	sts = readb(sport->port.membase + UARTSR1);
844	976
845		- if (sts & UARTSR1_RDRF)
846		- lpuart_rxint(irq, dev_id);
	977	+ /* SysRq, using dma, check for linebreak by framing err. */
	978	+ if (sts & UARTSR1_FE && sport->lpuart_dma_rx_use) {
	979	+ readb(sport->port.membase + UARTDR);
	980	+ uart_handle_break(&sport->port);
	981	+ /* linebreak produces some garbage, removing it */
	982	+ writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
	983	+ return IRQ_HANDLED;
	984	+ }
847	985
848		- if (sts & UARTSR1_TDRE)
849		- lpuart_txint(irq, dev_id);
	986	+ if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use)
	987	+ lpuart_rxint(sport);
	988	+
	989	+ if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use)
	990	+ lpuart_txint(sport);
850	991
851	992	return IRQ_HANDLED;
852	993	}
..	..	@@ -860,15 +1001,45 @@
860	1001	rxcount = lpuart32_read(&sport->port, UARTWATER);
861	1002	rxcount = rxcount >> UARTWATER_RXCNT_OFF;
862	1003
863		- if (sts & UARTSTAT_RDRF \|\| rxcount > 0)
864		- lpuart32_rxint(irq, dev_id);
	1004	+ if ((sts & UARTSTAT_RDRF \|\| rxcount > 0) && !sport->lpuart_dma_rx_use)
	1005	+ lpuart32_rxint(sport);
865	1006
866		- if ((sts & UARTSTAT_TDRE) &&
867		- !(lpuart32_read(&sport->port, UARTBAUD) & UARTBAUD_TDMAE))
868		- lpuart_txint(irq, dev_id);
	1007	+ if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use)
	1008	+ lpuart32_txint(sport);
869	1009
870	1010	lpuart32_write(&sport->port, sts, UARTSTAT);
871	1011	return IRQ_HANDLED;
	1012	+}
	1013	+
	1014	+
	1015	+static inline void lpuart_handle_sysrq_chars(struct uart_port *port,
	1016	+ unsigned char *p, int count)
	1017	+{
	1018	+ while (count--) {
	1019	+ if (p && uart_handle_sysrq_char(port, p))
	1020	+ return;
	1021	+ p++;
	1022	+ }
	1023	+}
	1024	+
	1025	+static void lpuart_handle_sysrq(struct lpuart_port *sport)
	1026	+{
	1027	+ struct circ_buf *ring = &sport->rx_ring;
	1028	+ int count;
	1029	+
	1030	+ if (ring->head < ring->tail) {
	1031	+ count = sport->rx_sgl.length - ring->tail;
	1032	+ lpuart_handle_sysrq_chars(&sport->port,
	1033	+ ring->buf + ring->tail, count);
	1034	+ ring->tail = 0;
	1035	+ }
	1036	+
	1037	+ if (ring->head > ring->tail) {
	1038	+ count = ring->head - ring->tail;
	1039	+ lpuart_handle_sysrq_chars(&sport->port,
	1040	+ ring->buf + ring->tail, count);
	1041	+ ring->tail = ring->head;
	1042	+ }
872	1043	}
873	1044
874	1045	static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
..	..	@@ -876,31 +1047,68 @@
876	1047	struct tty_port *port = &sport->port.state->port;
877	1048	struct dma_tx_state state;
878	1049	enum dma_status dmastat;
	1050	+ struct dma_chan *chan = sport->dma_rx_chan;
879	1051	struct circ_buf *ring = &sport->rx_ring;
880	1052	unsigned long flags;
881	1053	int count = 0;
882		- unsigned char sr;
883	1054
884		- sr = readb(sport->port.membase + UARTSR1);
	1055	+ if (lpuart_is_32(sport)) {
	1056	+ unsigned long sr = lpuart32_read(&sport->port, UARTSTAT);
885	1057
886		- if (sr & (UARTSR1_PE \| UARTSR1_FE)) {
887		- /* Read DR to clear the error flags */
888		- readb(sport->port.membase + UARTDR);
	1058	+ if (sr & (UARTSTAT_PE \| UARTSTAT_FE)) {
	1059	+ /* Read DR to clear the error flags */
	1060	+ lpuart32_read(&sport->port, UARTDATA);
889	1061
890		- if (sr & UARTSR1_PE)
891		- sport->port.icount.parity++;
892		- else if (sr & UARTSR1_FE)
893		- sport->port.icount.frame++;
	1062	+ if (sr & UARTSTAT_PE)
	1063	+ sport->port.icount.parity++;
	1064	+ else if (sr & UARTSTAT_FE)
	1065	+ sport->port.icount.frame++;
	1066	+ }
	1067	+ } else {
	1068	+ unsigned char sr = readb(sport->port.membase + UARTSR1);
	1069	+
	1070	+ if (sr & (UARTSR1_PE \| UARTSR1_FE)) {
	1071	+ unsigned char cr2;
	1072	+
	1073	+ /* Disable receiver during this operation... */
	1074	+ cr2 = readb(sport->port.membase + UARTCR2);
	1075	+ cr2 &= ~UARTCR2_RE;
	1076	+ writeb(cr2, sport->port.membase + UARTCR2);
	1077	+
	1078	+ /* Read DR to clear the error flags */
	1079	+ readb(sport->port.membase + UARTDR);
	1080	+
	1081	+ if (sr & UARTSR1_PE)
	1082	+ sport->port.icount.parity++;
	1083	+ else if (sr & UARTSR1_FE)
	1084	+ sport->port.icount.frame++;
	1085	+ /*
	1086	+ * At this point parity/framing error is
	1087	+ * cleared However, since the DMA already read
	1088	+ * the data register and we had to read it
	1089	+ * again after reading the status register to
	1090	+ * properly clear the flags, the FIFO actually
	1091	+ * underflowed... This requires a clearing of
	1092	+ * the FIFO...
	1093	+ */
	1094	+ if (readb(sport->port.membase + UARTSFIFO) &
	1095	+ UARTSFIFO_RXUF) {
	1096	+ writeb(UARTSFIFO_RXUF,
	1097	+ sport->port.membase + UARTSFIFO);
	1098	+ writeb(UARTCFIFO_RXFLUSH,
	1099	+ sport->port.membase + UARTCFIFO);
	1100	+ }
	1101	+
	1102	+ cr2 \|= UARTCR2_RE;
	1103	+ writeb(cr2, sport->port.membase + UARTCR2);
	1104	+ }
894	1105	}
895	1106
896	1107	async_tx_ack(sport->dma_rx_desc);
897	1108
898	1109	spin_lock_irqsave(&sport->port.lock, flags);
899	1110
900		- dmastat = dmaengine_tx_status(sport->dma_rx_chan,
901		- sport->dma_rx_cookie,
902		- &state);
903		-
	1111	+ dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state);
904	1112	if (dmastat == DMA_ERROR) {
905	1113	dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
906	1114	spin_unlock_irqrestore(&sport->port.lock, flags);
..	..	@@ -908,7 +1116,8 @@
908	1116	}
909	1117
910	1118	/* CPU claims ownership of RX DMA buffer */
911		- dma_sync_sg_for_cpu(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
	1119	+ dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1,
	1120	+ DMA_FROM_DEVICE);
912	1121
913	1122	/*
914	1123	* ring->head points to the end of data already written by the DMA.
..	..	@@ -919,6 +1128,15 @@
919	1128	*/
920	1129	ring->head = sport->rx_sgl.length - state.residue;
921	1130	BUG_ON(ring->head > sport->rx_sgl.length);
	1131	+
	1132	+ /*
	1133	+ * Silent handling of keys pressed in the sysrq timeframe
	1134	+ */
	1135	+ if (sport->port.sysrq) {
	1136	+ lpuart_handle_sysrq(sport);
	1137	+ goto exit;
	1138	+ }
	1139	+
922	1140	/*
923	1141	* At this point ring->head may point to the first byte right after the
924	1142	* last byte of the dma buffer:
..	..	@@ -950,7 +1168,8 @@
950	1168	sport->port.icount.rx += count;
951	1169	}
952	1170
953		- dma_sync_sg_for_device(sport->port.dev, &sport->rx_sgl, 1,
	1171	+exit:
	1172	+ dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1,
954	1173	DMA_FROM_DEVICE);
955	1174
956	1175	spin_unlock_irqrestore(&sport->port.lock, flags);
..	..	@@ -982,6 +1201,7 @@
982	1201	struct tty_port *port = &sport->port.state->port;
983	1202	struct tty_struct *tty = port->tty;
984	1203	struct ktermios *termios = &tty->termios;
	1204	+ struct dma_chan *chan = sport->dma_rx_chan;
985	1205
986	1206	baud = tty_get_baud_rate(tty);
987	1207
..	..	@@ -998,26 +1218,24 @@
998	1218	if (sport->rx_dma_rng_buf_len < 16)
999	1219	sport->rx_dma_rng_buf_len = 16;
1000	1220
1001		- ring->buf = kmalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC);
1002		- if (!ring->buf) {
1003		- dev_err(sport->port.dev, "Ring buf alloc failed\n");
	1221	+ ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC);
	1222	+ if (!ring->buf)
1004	1223	return -ENOMEM;
1005		- }
1006	1224
1007	1225	sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
1008		- sg_set_buf(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
1009		- nent = dma_map_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
	1226	+ nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1,
	1227	+ DMA_FROM_DEVICE);
1010	1228
1011	1229	if (!nent) {
1012	1230	dev_err(sport->port.dev, "DMA Rx mapping error\n");
1013	1231	return -EINVAL;
1014	1232	}
1015	1233
1016		- dma_rx_sconfig.src_addr = sport->port.mapbase + UARTDR;
	1234	+ dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport);
1017	1235	dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1018	1236	dma_rx_sconfig.src_maxburst = 1;
1019	1237	dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
1020		- ret = dmaengine_slave_config(sport->dma_rx_chan, &dma_rx_sconfig);
	1238	+ ret = dmaengine_slave_config(chan, &dma_rx_sconfig);
1021	1239
1022	1240	if (ret < 0) {
1023	1241	dev_err(sport->port.dev,
..	..	@@ -1025,7 +1243,7 @@
1025	1243	return ret;
1026	1244	}
1027	1245
1028		- sport->dma_rx_desc = dmaengine_prep_dma_cyclic(sport->dma_rx_chan,
	1246	+ sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan,
1029	1247	sg_dma_address(&sport->rx_sgl),
1030	1248	sport->rx_sgl.length,
1031	1249	sport->rx_sgl.length / 2,
..	..	@@ -1039,10 +1257,16 @@
1039	1257	sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
1040	1258	sport->dma_rx_desc->callback_param = sport;
1041	1259	sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
1042		- dma_async_issue_pending(sport->dma_rx_chan);
	1260	+ dma_async_issue_pending(chan);
1043	1261
1044		- writeb(readb(sport->port.membase + UARTCR5) \| UARTCR5_RDMAS,
1045		- sport->port.membase + UARTCR5);
	1262	+ if (lpuart_is_32(sport)) {
	1263	+ unsigned long temp = lpuart32_read(&sport->port, UARTBAUD);
	1264	+
	1265	+ lpuart32_write(&sport->port, temp \| UARTBAUD_RDMAE, UARTBAUD);
	1266	+ } else {
	1267	+ writeb(readb(sport->port.membase + UARTCR5) \| UARTCR5_RDMAS,
	1268	+ sport->port.membase + UARTCR5);
	1269	+ }
1046	1270
1047	1271	return 0;
1048	1272	}
..	..	@@ -1051,11 +1275,10 @@
1051	1275	{
1052	1276	struct lpuart_port *sport = container_of(port,
1053	1277	struct lpuart_port, port);
	1278	+ struct dma_chan *chan = sport->dma_rx_chan;
1054	1279
1055		- if (sport->dma_rx_chan)
1056		- dmaengine_terminate_all(sport->dma_rx_chan);
1057		-
1058		- dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
	1280	+ dmaengine_terminate_all(chan);
	1281	+ dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
1059	1282	kfree(sport->rx_ring.buf);
1060	1283	sport->rx_ring.tail = 0;
1061	1284	sport->rx_ring.head = 0;
..	..	@@ -1083,7 +1306,7 @@
1083	1306	modem \|= UARTMODEM_TXRTSE;
1084	1307
1085	1308	/*
1086		- * RTS needs to be logic HIGH either during transer _or_ after
	1309	+ * RTS needs to be logic HIGH either during transfer _or_ after
1087	1310	* transfer, other variants are not supported by the hardware.
1088	1311	*/
1089	1312
..	..	@@ -1114,6 +1337,57 @@
1114	1337	return 0;
1115	1338	}
1116	1339
	1340	+static int lpuart32_config_rs485(struct uart_port *port,
	1341	+ struct serial_rs485 *rs485)
	1342	+{
	1343	+ struct lpuart_port *sport = container_of(port,
	1344	+ struct lpuart_port, port);
	1345	+
	1346	+ unsigned long modem = lpuart32_read(&sport->port, UARTMODIR)
	1347	+ & ~(UARTMODEM_TXRTSPOL \| UARTMODEM_TXRTSE);
	1348	+ lpuart32_write(&sport->port, modem, UARTMODIR);
	1349	+
	1350	+ /* clear unsupported configurations */
	1351	+ rs485->delay_rts_before_send = 0;
	1352	+ rs485->delay_rts_after_send = 0;
	1353	+ rs485->flags &= ~SER_RS485_RX_DURING_TX;
	1354	+
	1355	+ if (rs485->flags & SER_RS485_ENABLED) {
	1356	+ /* Enable auto RS-485 RTS mode */
	1357	+ modem \|= UARTMODEM_TXRTSE;
	1358	+
	1359	+ /*
	1360	+ * RTS needs to be logic HIGH either during transfer _or_ after
	1361	+ * transfer, other variants are not supported by the hardware.
	1362	+ */
	1363	+
	1364	+ if (!(rs485->flags & (SER_RS485_RTS_ON_SEND \|
	1365	+ SER_RS485_RTS_AFTER_SEND)))
	1366	+ rs485->flags \|= SER_RS485_RTS_ON_SEND;
	1367	+
	1368	+ if (rs485->flags & SER_RS485_RTS_ON_SEND &&
	1369	+ rs485->flags & SER_RS485_RTS_AFTER_SEND)
	1370	+ rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
	1371	+
	1372	+ /*
	1373	+ * The hardware defaults to RTS logic HIGH while transfer.
	1374	+ * Switch polarity in case RTS shall be logic HIGH
	1375	+ * after transfer.
	1376	+ * Note: UART is assumed to be active high.
	1377	+ */
	1378	+ if (rs485->flags & SER_RS485_RTS_ON_SEND)
	1379	+ modem \|= UARTMODEM_TXRTSPOL;
	1380	+ else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
	1381	+ modem &= ~UARTMODEM_TXRTSPOL;
	1382	+ }
	1383	+
	1384	+ /* Store the new configuration */
	1385	+ sport->port.rs485 = *rs485;
	1386	+
	1387	+ lpuart32_write(&sport->port, modem, UARTMODIR);
	1388	+ return 0;
	1389	+}
	1390	+
1117	1391	static unsigned int lpuart_get_mctrl(struct uart_port *port)
1118	1392	{
1119	1393	unsigned int temp = 0;
..	..	@@ -1131,17 +1405,7 @@
1131	1405
1132	1406	static unsigned int lpuart32_get_mctrl(struct uart_port *port)
1133	1407	{
1134		- unsigned int temp = 0;
1135		- unsigned long reg;
1136		-
1137		- reg = lpuart32_read(port, UARTMODIR);
1138		- if (reg & UARTMODIR_TXCTSE)
1139		- temp \|= TIOCM_CTS;
1140		-
1141		- if (reg & UARTMODIR_RXRTSE)
1142		- temp \|= TIOCM_RTS;
1143		-
1144		- return temp;
	1408	+ return 0;
1145	1409	}
1146	1410
1147	1411	static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
..	..	@@ -1167,18 +1431,7 @@
1167	1431
1168	1432	static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
1169	1433	{
1170		- unsigned long temp;
1171	1434
1172		- temp = lpuart32_read(port, UARTMODIR) &
1173		- ~(UARTMODIR_RXRTSE \| UARTMODIR_TXCTSE);
1174		-
1175		- if (mctrl & TIOCM_RTS)
1176		- temp \|= UARTMODIR_RXRTSE;
1177		-
1178		- if (mctrl & TIOCM_CTS)
1179		- temp \|= UARTMODIR_TXCTSE;
1180		-
1181		- lpuart32_write(port, temp, UARTMODIR);
1182	1435	}
1183	1436
1184	1437	static void lpuart_break_ctl(struct uart_port *port, int break_state)
..	..	@@ -1237,6 +1490,17 @@
1237	1490	writeb(cr2_saved, sport->port.membase + UARTCR2);
1238	1491	}
1239	1492
	1493	+static void lpuart_setup_watermark_enable(struct lpuart_port *sport)
	1494	+{
	1495	+ unsigned char cr2;
	1496	+
	1497	+ lpuart_setup_watermark(sport);
	1498	+
	1499	+ cr2 = readb(sport->port.membase + UARTCR2);
	1500	+ cr2 \|= UARTCR2_RIE \| UARTCR2_RE \| UARTCR2_TE;
	1501	+ writeb(cr2, sport->port.membase + UARTCR2);
	1502	+}
	1503	+
1240	1504	static void lpuart32_setup_watermark(struct lpuart_port *sport)
1241	1505	{
1242	1506	unsigned long val, ctrl;
..	..	@@ -1262,11 +1526,108 @@
1262	1526	lpuart32_write(&sport->port, ctrl_saved, UARTCTRL);
1263	1527	}
1264	1528
	1529	+static void lpuart32_setup_watermark_enable(struct lpuart_port *sport)
	1530	+{
	1531	+ u32 temp;
	1532	+
	1533	+ lpuart32_setup_watermark(sport);
	1534	+
	1535	+ temp = lpuart32_read(&sport->port, UARTCTRL);
	1536	+ temp \|= UARTCTRL_RE \| UARTCTRL_TE \| UARTCTRL_ILIE;
	1537	+ lpuart32_write(&sport->port, temp, UARTCTRL);
	1538	+}
	1539	+
1265	1540	static void rx_dma_timer_init(struct lpuart_port *sport)
1266	1541	{
1267		- timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0);
1268		- sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
1269		- add_timer(&sport->lpuart_timer);
	1542	+ timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0);
	1543	+ sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
	1544	+ add_timer(&sport->lpuart_timer);
	1545	+}
	1546	+
	1547	+static void lpuart_request_dma(struct lpuart_port *sport)
	1548	+{
	1549	+ sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx");
	1550	+ if (IS_ERR(sport->dma_tx_chan)) {
	1551	+ dev_dbg_once(sport->port.dev,
	1552	+ "DMA tx channel request failed, operating without tx DMA (%ld)\n",
	1553	+ PTR_ERR(sport->dma_tx_chan));
	1554	+ sport->dma_tx_chan = NULL;
	1555	+ }
	1556	+
	1557	+ sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx");
	1558	+ if (IS_ERR(sport->dma_rx_chan)) {
	1559	+ dev_dbg_once(sport->port.dev,
	1560	+ "DMA rx channel request failed, operating without rx DMA (%ld)\n",
	1561	+ PTR_ERR(sport->dma_rx_chan));
	1562	+ sport->dma_rx_chan = NULL;
	1563	+ }
	1564	+}
	1565	+
	1566	+static void lpuart_tx_dma_startup(struct lpuart_port *sport)
	1567	+{
	1568	+ u32 uartbaud;
	1569	+ int ret;
	1570	+
	1571	+ if (uart_console(&sport->port))
	1572	+ goto err;
	1573	+
	1574	+ if (!sport->dma_tx_chan)
	1575	+ goto err;
	1576	+
	1577	+ ret = lpuart_dma_tx_request(&sport->port);
	1578	+ if (ret)
	1579	+ goto err;
	1580	+
	1581	+ init_waitqueue_head(&sport->dma_wait);
	1582	+ sport->lpuart_dma_tx_use = true;
	1583	+ if (lpuart_is_32(sport)) {
	1584	+ uartbaud = lpuart32_read(&sport->port, UARTBAUD);
	1585	+ lpuart32_write(&sport->port,
	1586	+ uartbaud \| UARTBAUD_TDMAE, UARTBAUD);
	1587	+ } else {
	1588	+ writeb(readb(sport->port.membase + UARTCR5) \|
	1589	+ UARTCR5_TDMAS, sport->port.membase + UARTCR5);
	1590	+ }
	1591	+
	1592	+ return;
	1593	+
	1594	+err:
	1595	+ sport->lpuart_dma_tx_use = false;
	1596	+}
	1597	+
	1598	+static void lpuart_rx_dma_startup(struct lpuart_port *sport)
	1599	+{
	1600	+ int ret;
	1601	+ unsigned char cr3;
	1602	+
	1603	+ if (uart_console(&sport->port))
	1604	+ goto err;
	1605	+
	1606	+ if (!sport->dma_rx_chan)
	1607	+ goto err;
	1608	+
	1609	+ ret = lpuart_start_rx_dma(sport);
	1610	+ if (ret)
	1611	+ goto err;
	1612	+
	1613	+ /* set Rx DMA timeout */
	1614	+ sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT);
	1615	+ if (!sport->dma_rx_timeout)
	1616	+ sport->dma_rx_timeout = 1;
	1617	+
	1618	+ sport->lpuart_dma_rx_use = true;
	1619	+ rx_dma_timer_init(sport);
	1620	+
	1621	+ if (sport->port.has_sysrq && !lpuart_is_32(sport)) {
	1622	+ cr3 = readb(sport->port.membase + UARTCR3);
	1623	+ cr3 \|= UARTCR3_FEIE;
	1624	+ writeb(cr3, sport->port.membase + UARTCR3);
	1625	+ }
	1626	+
	1627	+ return;
	1628	+
	1629	+err:
	1630	+ sport->lpuart_dma_rx_use = false;
1270	1631	}
1271	1632
1272	1633	static int lpuart_startup(struct uart_port *port)
..	..	@@ -1278,46 +1639,43 @@
1278	1639	/* determine FIFO size and enable FIFO mode */
1279	1640	temp = readb(sport->port.membase + UARTPFIFO);
1280	1641
1281		- sport->txfifo_size = 0x1 << (((temp >> UARTPFIFO_TXSIZE_OFF) &
1282		- UARTPFIFO_FIFOSIZE_MASK) + 1);
1283		-
	1642	+ sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) &
	1643	+ UARTPFIFO_FIFOSIZE_MASK);
1284	1644	sport->port.fifosize = sport->txfifo_size;
1285	1645
1286		- sport->rxfifo_size = 0x1 << (((temp >> UARTPFIFO_RXSIZE_OFF) &
1287		- UARTPFIFO_FIFOSIZE_MASK) + 1);
	1646	+ sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) &
	1647	+ UARTPFIFO_FIFOSIZE_MASK);
	1648	+
	1649	+ lpuart_request_dma(sport);
1288	1650
1289	1651	spin_lock_irqsave(&sport->port.lock, flags);
1290	1652
1291		- lpuart_setup_watermark(sport);
	1653	+ lpuart_setup_watermark_enable(sport);
1292	1654
1293		- temp = readb(sport->port.membase + UARTCR2);
1294		- temp \|= (UARTCR2_RIE \| UARTCR2_TIE \| UARTCR2_RE \| UARTCR2_TE);
1295		- writeb(temp, sport->port.membase + UARTCR2);
1296		-
1297		- if (sport->dma_rx_chan && !lpuart_start_rx_dma(sport)) {
1298		- /* set Rx DMA timeout */
1299		- sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT);
1300		- if (!sport->dma_rx_timeout)
1301		- sport->dma_rx_timeout = 1;
1302		-
1303		- sport->lpuart_dma_rx_use = true;
1304		- rx_dma_timer_init(sport);
1305		- } else {
1306		- sport->lpuart_dma_rx_use = false;
1307		- }
1308		-
1309		- if (sport->dma_tx_chan && !lpuart_dma_tx_request(port)) {
1310		- init_waitqueue_head(&sport->dma_wait);
1311		- sport->lpuart_dma_tx_use = true;
1312		- temp = readb(port->membase + UARTCR5);
1313		- writeb(temp \| UARTCR5_TDMAS, port->membase + UARTCR5);
1314		- } else {
1315		- sport->lpuart_dma_tx_use = false;
1316		- }
	1655	+ lpuart_rx_dma_startup(sport);
	1656	+ lpuart_tx_dma_startup(sport);
1317	1657
1318	1658	spin_unlock_irqrestore(&sport->port.lock, flags);
1319	1659
1320	1660	return 0;
	1661	+}
	1662	+
	1663	+static void lpuart32_configure(struct lpuart_port *sport)
	1664	+{
	1665	+ unsigned long temp;
	1666	+
	1667	+ if (sport->lpuart_dma_rx_use) {
	1668	+ /* RXWATER must be 0 */
	1669	+ temp = lpuart32_read(&sport->port, UARTWATER);
	1670	+ temp &= ~(UARTWATER_WATER_MASK << UARTWATER_RXWATER_OFF);
	1671	+ lpuart32_write(&sport->port, temp, UARTWATER);
	1672	+ }
	1673	+ temp = lpuart32_read(&sport->port, UARTCTRL);
	1674	+ if (!sport->lpuart_dma_rx_use)
	1675	+ temp \|= UARTCTRL_RIE;
	1676	+ if (!sport->lpuart_dma_tx_use)
	1677	+ temp \|= UARTCTRL_TIE;
	1678	+ lpuart32_write(&sport->port, temp, UARTCTRL);
1321	1679	}
1322	1680
1323	1681	static int lpuart32_startup(struct uart_port *port)
..	..	@@ -1329,23 +1687,60 @@
1329	1687	/* determine FIFO size */
1330	1688	temp = lpuart32_read(&sport->port, UARTFIFO);
1331	1689
1332		- sport->txfifo_size = 0x1 << (((temp >> UARTFIFO_TXSIZE_OFF) &
1333		- UARTFIFO_FIFOSIZE_MASK) - 1);
	1690	+ sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) &
	1691	+ UARTFIFO_FIFOSIZE_MASK);
	1692	+ sport->port.fifosize = sport->txfifo_size;
1334	1693
1335		- sport->rxfifo_size = 0x1 << (((temp >> UARTFIFO_RXSIZE_OFF) &
1336		- UARTFIFO_FIFOSIZE_MASK) - 1);
	1694	+ sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) &
	1695	+ UARTFIFO_FIFOSIZE_MASK);
	1696	+
	1697	+ /*
	1698	+ * The LS1021A and LS1028A have a fixed FIFO depth of 16 words.
	1699	+ * Although they support the RX/TXSIZE fields, their encoding is
	1700	+ * different. Eg the reference manual states 0b101 is 16 words.
	1701	+ */
	1702	+ if (is_layerscape_lpuart(sport)) {
	1703	+ sport->rxfifo_size = 16;
	1704	+ sport->txfifo_size = 16;
	1705	+ sport->port.fifosize = sport->txfifo_size;
	1706	+ }
	1707	+
	1708	+ lpuart_request_dma(sport);
1337	1709
1338	1710	spin_lock_irqsave(&sport->port.lock, flags);
1339	1711
1340		- lpuart32_setup_watermark(sport);
	1712	+ lpuart32_setup_watermark_enable(sport);
1341	1713
1342		- temp = lpuart32_read(&sport->port, UARTCTRL);
1343		- temp \|= (UARTCTRL_RIE \| UARTCTRL_TIE \| UARTCTRL_RE \| UARTCTRL_TE);
1344		- temp \|= UARTCTRL_ILIE;
1345		- lpuart32_write(&sport->port, temp, UARTCTRL);
	1714	+ lpuart_rx_dma_startup(sport);
	1715	+ lpuart_tx_dma_startup(sport);
	1716	+
	1717	+ lpuart32_configure(sport);
1346	1718
1347	1719	spin_unlock_irqrestore(&sport->port.lock, flags);
1348	1720	return 0;
	1721	+}
	1722	+
	1723	+static void lpuart_dma_shutdown(struct lpuart_port *sport)
	1724	+{
	1725	+ if (sport->lpuart_dma_rx_use) {
	1726	+ del_timer_sync(&sport->lpuart_timer);
	1727	+ lpuart_dma_rx_free(&sport->port);
	1728	+ sport->lpuart_dma_rx_use = false;
	1729	+ }
	1730	+
	1731	+ if (sport->lpuart_dma_tx_use) {
	1732	+ if (wait_event_interruptible(sport->dma_wait,
	1733	+ !sport->dma_tx_in_progress) != false) {
	1734	+ sport->dma_tx_in_progress = false;
	1735	+ dmaengine_terminate_all(sport->dma_tx_chan);
	1736	+ }
	1737	+ sport->lpuart_dma_tx_use = false;
	1738	+ }
	1739	+
	1740	+ if (sport->dma_tx_chan)
	1741	+ dma_release_channel(sport->dma_tx_chan);
	1742	+ if (sport->dma_rx_chan)
	1743	+ dma_release_channel(sport->dma_rx_chan);
1349	1744	}
1350	1745
1351	1746	static void lpuart_shutdown(struct uart_port *port)
..	..	@@ -1364,24 +1759,13 @@
1364	1759
1365	1760	spin_unlock_irqrestore(&port->lock, flags);
1366	1761
1367		- if (sport->lpuart_dma_rx_use) {
1368		- del_timer_sync(&sport->lpuart_timer);
1369		- lpuart_dma_rx_free(&sport->port);
1370		- }
1371		-
1372		- if (sport->lpuart_dma_tx_use) {
1373		- if (wait_event_interruptible(sport->dma_wait,
1374		- !sport->dma_tx_in_progress) != false) {
1375		- sport->dma_tx_in_progress = false;
1376		- dmaengine_terminate_all(sport->dma_tx_chan);
1377		- }
1378		-
1379		- lpuart_stop_tx(port);
1380		- }
	1762	+ lpuart_dma_shutdown(sport);
1381	1763	}
1382	1764
1383	1765	static void lpuart32_shutdown(struct uart_port *port)
1384	1766	{
	1767	+ struct lpuart_port *sport =
	1768	+ container_of(port, struct lpuart_port, port);
1385	1769	unsigned long temp;
1386	1770	unsigned long flags;
1387	1771
..	..	@@ -1394,6 +1778,8 @@
1394	1778	lpuart32_write(port, temp, UARTCTRL);
1395	1779
1396	1780	spin_unlock_irqrestore(&port->lock, flags);
	1781	+
	1782	+ lpuart_dma_shutdown(sport);
1397	1783	}
1398	1784
1399	1785	static void
..	..	@@ -1447,21 +1833,18 @@
1447	1833	if (sport->port.rs485.flags & SER_RS485_ENABLED)
1448	1834	termios->c_cflag &= ~CRTSCTS;
1449	1835
1450		- if (termios->c_cflag & CRTSCTS) {
1451		- modem \|= (UARTMODEM_RXRTSE \| UARTMODEM_TXCTSE);
1452		- } else {
1453		- termios->c_cflag &= ~CRTSCTS;
	1836	+ if (termios->c_cflag & CRTSCTS)
	1837	+ modem \|= UARTMODEM_RXRTSE \| UARTMODEM_TXCTSE;
	1838	+ else
1454	1839	modem &= ~(UARTMODEM_RXRTSE \| UARTMODEM_TXCTSE);
1455		- }
1456	1840
1457		- if (termios->c_cflag & CSTOPB)
1458		- termios->c_cflag &= ~CSTOPB;
	1841	+ termios->c_cflag &= ~CSTOPB;
1459	1842
1460	1843	/* parity must be enabled when CS7 to match 8-bits format */
1461	1844	if ((termios->c_cflag & CSIZE) == CS7)
1462	1845	termios->c_cflag \|= PARENB;
1463	1846
1464		- if ((termios->c_cflag & PARENB)) {
	1847	+ if (termios->c_cflag & PARENB) {
1465	1848	if (termios->c_cflag & CMSPAR) {
1466	1849	cr1 &= ~UARTCR1_PE;
1467	1850	if (termios->c_cflag & PARODD)
..	..	@@ -1500,7 +1883,7 @@
1500	1883
1501	1884	sport->port.read_status_mask = 0;
1502	1885	if (termios->c_iflag & INPCK)
1503		- sport->port.read_status_mask \|= (UARTSR1_FE \| UARTSR1_PE);
	1886	+ sport->port.read_status_mask \|= UARTSR1_FE \| UARTSR1_PE;
1504	1887	if (termios->c_iflag & (IGNBRK \| BRKINT \| PARMRK))
1505	1888	sport->port.read_status_mask \|= UARTSR1_FE;
1506	1889
..	..	@@ -1522,8 +1905,7 @@
1522	1905	uart_update_timeout(port, termios->c_cflag, baud);
1523	1906
1524	1907	/* wait transmit engin complete */
1525		- while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1526		- barrier();
	1908	+ lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
1527	1909
1528	1910	/* disable transmit and receive */
1529	1911	writeb(old_cr2 & ~(UARTCR2_TE \| UARTCR2_RE),
..	..	@@ -1555,11 +1937,12 @@
1555	1937	spin_unlock_irqrestore(&sport->port.lock, flags);
1556	1938	}
1557	1939
1558		-static void
1559		-lpuart32_serial_setbrg(struct lpuart_port *sport, unsigned int baudrate)
	1940	+static void __lpuart32_serial_setbrg(struct uart_port *port,
	1941	+ unsigned int baudrate, bool use_rx_dma,
	1942	+ bool use_tx_dma)
1560	1943	{
1561	1944	u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
1562		- u32 clk = sport->port.uartclk;
	1945	+ u32 clk = port->uartclk;
1563	1946
1564	1947	/*
1565	1948	* The idea is to use the best OSR (over-sampling rate) possible.
..	..	@@ -1593,6 +1976,9 @@
1593	1976	tmp_sbr++;
1594	1977	}
1595	1978
	1979	+ if (tmp_sbr > UARTBAUD_SBR_MASK)
	1980	+ continue;
	1981	+
1596	1982	if (tmp_diff <= baud_diff) {
1597	1983	baud_diff = tmp_diff;
1598	1984	osr = tmp_osr;
..	..	@@ -1605,24 +1991,36 @@
1605	1991
1606	1992	/* handle buadrate outside acceptable rate */
1607	1993	if (baud_diff > ((baudrate / 100) * 3))
1608		- dev_warn(sport->port.dev,
	1994	+ dev_warn(port->dev,
1609	1995	"unacceptable baud rate difference of more than 3%%\n");
1610	1996
1611		- tmp = lpuart32_read(&sport->port, UARTBAUD);
	1997	+ tmp = lpuart32_read(port, UARTBAUD);
1612	1998
1613	1999	if ((osr > 3) && (osr < 8))
1614	2000	tmp \|= UARTBAUD_BOTHEDGE;
1615	2001
1616	2002	tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT);
1617		- tmp \|= (((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT);
	2003	+ tmp \|= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT;
1618	2004
1619	2005	tmp &= ~UARTBAUD_SBR_MASK;
1620	2006	tmp \|= sbr & UARTBAUD_SBR_MASK;
1621	2007
1622		- tmp &= ~(UARTBAUD_TDMAE \| UARTBAUD_RDMAE);
	2008	+ if (!use_rx_dma)
	2009	+ tmp &= ~UARTBAUD_RDMAE;
	2010	+ if (!use_tx_dma)
	2011	+ tmp &= ~UARTBAUD_TDMAE;
1623	2012
1624		- lpuart32_write(&sport->port, tmp, UARTBAUD);
	2013	+ lpuart32_write(port, tmp, UARTBAUD);
1625	2014	}
	2015	+
	2016	+static void lpuart32_serial_setbrg(struct lpuart_port *sport,
	2017	+ unsigned int baudrate)
	2018	+{
	2019	+ __lpuart32_serial_setbrg(&sport->port, baudrate,
	2020	+ sport->lpuart_dma_rx_use,
	2021	+ sport->lpuart_dma_tx_use);
	2022	+}
	2023	+
1626	2024
1627	2025	static void
1628	2026	lpuart32_set_termios(struct uart_port port, struct ktermios termios,
..	..	@@ -1663,11 +2061,18 @@
1663	2061	ctrl \|= UARTCTRL_M;
1664	2062	}
1665	2063
	2064	+ /*
	2065	+ * When auto RS-485 RTS mode is enabled,
	2066	+ * hardware flow control need to be disabled.
	2067	+ */
	2068	+ if (sport->port.rs485.flags & SER_RS485_ENABLED)
	2069	+ termios->c_cflag &= ~CRTSCTS;
	2070	+
1666	2071	if (termios->c_cflag & CRTSCTS) {
1667		- modem \|= (UARTMODEM_RXRTSE \| UARTMODEM_TXCTSE);
	2072	+ modem \|= (UARTMODIR_RXRTSE \| UARTMODIR_TXCTSE);
1668	2073	} else {
1669	2074	termios->c_cflag &= ~CRTSCTS;
1670		- modem &= ~(UARTMODEM_RXRTSE \| UARTMODEM_TXCTSE);
	2075	+ modem &= ~(UARTMODIR_RXRTSE \| UARTMODIR_TXCTSE);
1671	2076	}
1672	2077
1673	2078	if (termios->c_cflag & CSTOPB)
..	..	@@ -1682,7 +2087,7 @@
1682	2087	ctrl &= ~UARTCTRL_PE;
1683	2088	ctrl \|= UARTCTRL_M;
1684	2089	} else {
1685		- ctrl \|= UARTCR1_PE;
	2090	+ ctrl \|= UARTCTRL_PE;
1686	2091	if ((termios->c_cflag & CSIZE) == CS8)
1687	2092	ctrl \|= UARTCTRL_M;
1688	2093	if (termios->c_cflag & PARODD)
..	..	@@ -1697,11 +2102,23 @@
1697	2102	/* ask the core to calculate the divisor */
1698	2103	baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4);
1699	2104
	2105	+ /*
	2106	+ * Need to update the Ring buffer length according to the selected
	2107	+ * baud rate and restart Rx DMA path.
	2108	+ *
	2109	+ * Since timer function acqures sport->port.lock, need to stop before
	2110	+ * acquring same lock because otherwise del_timer_sync() can deadlock.
	2111	+ */
	2112	+ if (old && sport->lpuart_dma_rx_use) {
	2113	+ del_timer_sync(&sport->lpuart_timer);
	2114	+ lpuart_dma_rx_free(&sport->port);
	2115	+ }
	2116	+
1700	2117	spin_lock_irqsave(&sport->port.lock, flags);
1701	2118
1702	2119	sport->port.read_status_mask = 0;
1703	2120	if (termios->c_iflag & INPCK)
1704		- sport->port.read_status_mask \|= (UARTSTAT_FE \| UARTSTAT_PE);
	2121	+ sport->port.read_status_mask \|= UARTSTAT_FE \| UARTSTAT_PE;
1705	2122	if (termios->c_iflag & (IGNBRK \| BRKINT \| PARMRK))
1706	2123	sport->port.read_status_mask \|= UARTSTAT_FE;
1707	2124
..	..	@@ -1723,8 +2140,8 @@
1723	2140	uart_update_timeout(port, termios->c_cflag, baud);
1724	2141
1725	2142	/* wait transmit engin complete */
1726		- while (!(lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_TC))
1727		- barrier();
	2143	+ lpuart32_write(&sport->port, 0, UARTMODIR);
	2144	+ lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
1728	2145
1729	2146	/* disable transmit and receive */
1730	2147	lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE \| UARTCTRL_RE),
..	..	@@ -1734,6 +2151,13 @@
1734	2151	lpuart32_write(&sport->port, modem, UARTMODIR);
1735	2152	lpuart32_write(&sport->port, ctrl, UARTCTRL);
1736	2153	/* restore control register */
	2154	+
	2155	+ if (old && sport->lpuart_dma_rx_use) {
	2156	+ if (!lpuart_start_rx_dma(sport))
	2157	+ rx_dma_timer_init(sport);
	2158	+ else
	2159	+ sport->lpuart_dma_rx_use = false;
	2160	+ }
1737	2161
1738	2162	spin_unlock_irqrestore(&sport->port.lock, flags);
1739	2163	}
..	..	@@ -1832,17 +2256,13 @@
1832	2256	#ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
1833	2257	static void lpuart_console_putchar(struct uart_port *port, int ch)
1834	2258	{
1835		- while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
1836		- barrier();
1837		-
	2259	+ lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);
1838	2260	writeb(ch, port->membase + UARTDR);
1839	2261	}
1840	2262
1841	2263	static void lpuart32_console_putchar(struct uart_port *port, int ch)
1842	2264	{
1843		- while (!(lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE))
1844		- barrier();
1845		-
	2265	+ lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);
1846	2266	lpuart32_write(port, ch, UARTDATA);
1847	2267	}
1848	2268
..	..	@@ -1861,15 +2281,14 @@
1861	2281
1862	2282	/* first save CR2 and then disable interrupts */
1863	2283	cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
1864		- cr2 \|= (UARTCR2_TE \| UARTCR2_RE);
	2284	+ cr2 \|= UARTCR2_TE \| UARTCR2_RE;
1865	2285	cr2 &= ~(UARTCR2_TIE \| UARTCR2_TCIE \| UARTCR2_RIE);
1866	2286	writeb(cr2, sport->port.membase + UARTCR2);
1867	2287
1868	2288	uart_console_write(&sport->port, s, count, lpuart_console_putchar);
1869	2289
1870	2290	/* wait for transmitter finish complete and restore CR2 */
1871		- while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1872		- barrier();
	2291	+ lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
1873	2292
1874	2293	writeb(old_cr2, sport->port.membase + UARTCR2);
1875	2294
..	..	@@ -1892,15 +2311,14 @@
1892	2311
1893	2312	/* first save CR2 and then disable interrupts */
1894	2313	cr = old_cr = lpuart32_read(&sport->port, UARTCTRL);
1895		- cr \|= (UARTCTRL_TE \| UARTCTRL_RE);
	2314	+ cr \|= UARTCTRL_TE \| UARTCTRL_RE;
1896	2315	cr &= ~(UARTCTRL_TIE \| UARTCTRL_TCIE \| UARTCTRL_RIE);
1897	2316	lpuart32_write(&sport->port, cr, UARTCTRL);
1898	2317
1899	2318	uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
1900	2319
1901	2320	/* wait for transmitter finish complete and restore CR2 */
1902		- while (!(lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_TC))
1903		- barrier();
	2321	+ lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
1904	2322
1905	2323	lpuart32_write(&sport->port, old_cr, UARTCTRL);
1906	2324
..	..	@@ -1950,14 +2368,14 @@
1950	2368	brfa = readb(sport->port.membase + UARTCR4);
1951	2369	brfa &= UARTCR4_BRFA_MASK;
1952	2370
1953		- uartclk = clk_get_rate(sport->clk);
	2371	+ uartclk = lpuart_get_baud_clk_rate(sport);
1954	2372	/*
1955	2373	* baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1956	2374	*/
1957	2375	baud_raw = uartclk / (16 * (sbr + brfa / 32));
1958	2376
1959	2377	if (*baud != baud_raw)
1960		- printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
	2378	+ dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
1961	2379	"from %d to %d\n", baud_raw, *baud);
1962	2380	}
1963	2381
..	..	@@ -1996,14 +2414,14 @@
1996	2414	return;
1997	2415
1998	2416	sbr = bd;
1999		- uartclk = clk_get_rate(sport->clk);
	2417	+ uartclk = lpuart_get_baud_clk_rate(sport);
2000	2418	/*
2001	2419	* baud = mod_clk/(16*(sbr[13]+(brfa)/32)
2002	2420	*/
2003	2421	baud_raw = uartclk / (16 * sbr);
2004	2422
2005	2423	if (*baud != baud_raw)
2006		- printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
	2424	+ dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2007	2425	"from %d to %d\n", baud_raw, *baud);
2008	2426	}
2009	2427
..	..	@@ -2094,8 +2512,34 @@
2094	2512	if (!device->port.membase)
2095	2513	return -ENODEV;
2096	2514
2097		- device->port.iotype = UPIO_MEM32BE;
	2515	+ if (device->port.iotype != UPIO_MEM32)
	2516	+ device->port.iotype = UPIO_MEM32BE;
	2517	+
2098	2518	device->con->write = lpuart32_early_write;
	2519	+ return 0;
	2520	+}
	2521	+
	2522	+static int __init ls1028a_early_console_setup(struct earlycon_device *device,
	2523	+ const char *opt)
	2524	+{
	2525	+ u32 cr;
	2526	+
	2527	+ if (!device->port.membase)
	2528	+ return -ENODEV;
	2529	+
	2530	+ device->port.iotype = UPIO_MEM32;
	2531	+ device->con->write = lpuart32_early_write;
	2532	+
	2533	+ /* set the baudrate */
	2534	+ if (device->port.uartclk && device->baud)
	2535	+ __lpuart32_serial_setbrg(&device->port, device->baud,
	2536	+ false, false);
	2537	+
	2538	+ /* enable transmitter */
	2539	+ cr = lpuart32_read(&device->port, UARTCTRL);
	2540	+ cr \|= UARTCTRL_TE;
	2541	+ lpuart32_write(&device->port, cr, UARTCTRL);
	2542	+
2099	2543	return 0;
2100	2544	}
2101	2545
..	..	@@ -2113,7 +2557,9 @@
2113	2557	}
2114	2558	OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
2115	2559	OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
	2560	+OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1028a-lpuart", ls1028a_early_console_setup);
2116	2561	OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup);
	2562	+OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8qxp-lpuart", lpuart32_imx_early_console_setup);
2117	2563	EARLYCON_DECLARE(lpuart, lpuart_early_console_setup);
2118	2564	EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup);
2119	2565
..	..	@@ -2146,7 +2592,49 @@
2146	2592	if (!sport)
2147	2593	return -ENOMEM;
2148	2594
2149		- pdev->dev.coherent_dma_mask = 0;
	2595	+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	2596	+ sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
	2597	+ if (IS_ERR(sport->port.membase))
	2598	+ return PTR_ERR(sport->port.membase);
	2599	+
	2600	+ sport->port.membase += sdata->reg_off;
	2601	+ sport->port.mapbase = res->start + sdata->reg_off;
	2602	+ sport->port.dev = &pdev->dev;
	2603	+ sport->port.type = PORT_LPUART;
	2604	+ sport->devtype = sdata->devtype;
	2605	+ ret = platform_get_irq(pdev, 0);
	2606	+ if (ret < 0)
	2607	+ return ret;
	2608	+ sport->port.irq = ret;
	2609	+ sport->port.iotype = sdata->iotype;
	2610	+ if (lpuart_is_32(sport))
	2611	+ sport->port.ops = &lpuart32_pops;
	2612	+ else
	2613	+ sport->port.ops = &lpuart_pops;
	2614	+ sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE);
	2615	+ sport->port.flags = UPF_BOOT_AUTOCONF;
	2616	+
	2617	+ if (lpuart_is_32(sport))
	2618	+ sport->port.rs485_config = lpuart32_config_rs485;
	2619	+ else
	2620	+ sport->port.rs485_config = lpuart_config_rs485;
	2621	+
	2622	+ sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
	2623	+ if (IS_ERR(sport->ipg_clk)) {
	2624	+ ret = PTR_ERR(sport->ipg_clk);
	2625	+ dev_err(&pdev->dev, "failed to get uart ipg clk: %d\n", ret);
	2626	+ return ret;
	2627	+ }
	2628	+
	2629	+ sport->baud_clk = NULL;
	2630	+ if (is_imx8qxp_lpuart(sport)) {
	2631	+ sport->baud_clk = devm_clk_get(&pdev->dev, "baud");
	2632	+ if (IS_ERR(sport->baud_clk)) {
	2633	+ ret = PTR_ERR(sport->baud_clk);
	2634	+ dev_err(&pdev->dev, "failed to get uart baud clk: %d\n", ret);
	2635	+ return ret;
	2636	+ }
	2637	+ }
2150	2638
2151	2639	ret = of_alias_get_id(np, "serial");
2152	2640	if (ret < 0) {
..	..	@@ -2158,44 +2646,11 @@
2158	2646	return -EINVAL;
2159	2647	}
2160	2648	sport->port.line = ret;
2161		- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2162		- sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
2163		- if (IS_ERR(sport->port.membase))
2164		- return PTR_ERR(sport->port.membase);
2165	2649
2166		- sport->port.membase += sdata->reg_off;
2167		- sport->port.mapbase = res->start + sdata->reg_off;
2168		- sport->port.dev = &pdev->dev;
2169		- sport->port.type = PORT_LPUART;
2170		- ret = platform_get_irq(pdev, 0);
2171		- if (ret < 0) {
2172		- dev_err(&pdev->dev, "cannot obtain irq\n");
	2650	+ ret = lpuart_enable_clks(sport);
	2651	+ if (ret)
2173	2652	return ret;
2174		- }
2175		- sport->port.irq = ret;
2176		- sport->port.iotype = sdata->iotype;
2177		- if (lpuart_is_32(sport))
2178		- sport->port.ops = &lpuart32_pops;
2179		- else
2180		- sport->port.ops = &lpuart_pops;
2181		- sport->port.flags = UPF_BOOT_AUTOCONF;
2182		-
2183		- sport->port.rs485_config = lpuart_config_rs485;
2184		-
2185		- sport->clk = devm_clk_get(&pdev->dev, "ipg");
2186		- if (IS_ERR(sport->clk)) {
2187		- ret = PTR_ERR(sport->clk);
2188		- dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret);
2189		- return ret;
2190		- }
2191		-
2192		- ret = clk_prepare_enable(sport->clk);
2193		- if (ret) {
2194		- dev_err(&pdev->dev, "failed to enable uart clk: %d\n", ret);
2195		- return ret;
2196		- }
2197		-
2198		- sport->port.uartclk = clk_get_rate(sport->clk);
	2653	+ sport->port.uartclk = lpuart_get_baud_clk_rate(sport);
2199	2654
2200	2655	lpuart_ports[sport->port.line] = sport;
2201	2656
..	..	@@ -2214,11 +2669,9 @@
2214	2669	if (ret)
2215	2670	goto failed_irq_request;
2216	2671
2217		- ret = uart_add_one_port(&lpuart_reg, &sport->port);
	2672	+ ret = uart_get_rs485_mode(&sport->port);
2218	2673	if (ret)
2219		- goto failed_attach_port;
2220		-
2221		- uart_get_rs485_mode(&pdev->dev, &sport->port.rs485);
	2674	+ goto failed_get_rs485;
2222	2675
2223	2676	if (sport->port.rs485.flags & SER_RS485_RX_DURING_TX)
2224	2677	dev_err(&pdev->dev, "driver doesn't support RX during TX\n");
..	..	@@ -2227,23 +2680,16 @@
2227	2680	sport->port.rs485.delay_rts_after_send)
2228	2681	dev_err(&pdev->dev, "driver doesn't support RTS delays\n");
2229	2682
2230		- lpuart_config_rs485(&sport->port, &sport->port.rs485);
2231		-
2232		- sport->dma_tx_chan = dma_request_slave_channel(sport->port.dev, "tx");
2233		- if (!sport->dma_tx_chan)
2234		- dev_info(sport->port.dev, "DMA tx channel request failed, "
2235		- "operating without tx DMA\n");
2236		-
2237		- sport->dma_rx_chan = dma_request_slave_channel(sport->port.dev, "rx");
2238		- if (!sport->dma_rx_chan)
2239		- dev_info(sport->port.dev, "DMA rx channel request failed, "
2240		- "operating without rx DMA\n");
	2683	+ ret = uart_add_one_port(&lpuart_reg, &sport->port);
	2684	+ if (ret)
	2685	+ goto failed_attach_port;
2241	2686
2242	2687	return 0;
2243	2688
	2689	+failed_get_rs485:
2244	2690	failed_attach_port:
2245	2691	failed_irq_request:
2246		- clk_disable_unprepare(sport->clk);
	2692	+ lpuart_disable_clks(sport);
2247	2693	return ret;
2248	2694	}
2249	2695
..	..	@@ -2253,7 +2699,7 @@
2253	2699
2254	2700	uart_remove_one_port(&lpuart_reg, &sport->port);
2255	2701
2256		- clk_disable_unprepare(sport->clk);
	2702	+ lpuart_disable_clks(sport);
2257	2703
2258	2704	if (sport->dma_tx_chan)
2259	2705	dma_release_channel(sport->dma_tx_chan);
..	..	@@ -2264,8 +2710,7 @@
2264	2710	return 0;
2265	2711	}
2266	2712
2267		-#ifdef CONFIG_PM_SLEEP
2268		-static int lpuart_suspend(struct device *dev)
	2713	+static int __maybe_unused lpuart_suspend(struct device *dev)
2269	2714	{
2270	2715	struct lpuart_port *sport = dev_get_drvdata(dev);
2271	2716	unsigned long temp;
..	..	@@ -2302,8 +2747,14 @@
2302	2747	}
2303	2748
2304	2749	/* Disable Rx DMA to use UART port as wakeup source */
2305		- writeb(readb(sport->port.membase + UARTCR5) & ~UARTCR5_RDMAS,
2306		- sport->port.membase + UARTCR5);
	2750	+ if (lpuart_is_32(sport)) {
	2751	+ temp = lpuart32_read(&sport->port, UARTBAUD);
	2752	+ lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE,
	2753	+ UARTBAUD);
	2754	+ } else {
	2755	+ writeb(readb(sport->port.membase + UARTCR5) &
	2756	+ ~UARTCR5_RDMAS, sport->port.membase + UARTCR5);
	2757	+ }
2307	2758	}
2308	2759
2309	2760	if (sport->lpuart_dma_tx_use) {
..	..	@@ -2312,32 +2763,23 @@
2312	2763	}
2313	2764
2314	2765	if (sport->port.suspended && !irq_wake)
2315		- clk_disable_unprepare(sport->clk);
	2766	+ lpuart_disable_clks(sport);
2316	2767
2317	2768	return 0;
2318	2769	}
2319	2770
2320		-static int lpuart_resume(struct device *dev)
	2771	+static int __maybe_unused lpuart_resume(struct device *dev)
2321	2772	{
2322	2773	struct lpuart_port *sport = dev_get_drvdata(dev);
2323	2774	bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
2324		- unsigned long temp;
2325	2775
2326	2776	if (sport->port.suspended && !irq_wake)
2327		- clk_prepare_enable(sport->clk);
	2777	+ lpuart_enable_clks(sport);
2328	2778
2329		- if (lpuart_is_32(sport)) {
2330		- lpuart32_setup_watermark(sport);
2331		- temp = lpuart32_read(&sport->port, UARTCTRL);
2332		- temp \|= (UARTCTRL_RIE \| UARTCTRL_TIE \| UARTCTRL_RE \|
2333		- UARTCTRL_TE \| UARTCTRL_ILIE);
2334		- lpuart32_write(&sport->port, temp, UARTCTRL);
2335		- } else {
2336		- lpuart_setup_watermark(sport);
2337		- temp = readb(sport->port.membase + UARTCR2);
2338		- temp \|= (UARTCR2_RIE \| UARTCR2_TIE \| UARTCR2_RE \| UARTCR2_TE);
2339		- writeb(temp, sport->port.membase + UARTCR2);
2340		- }
	2779	+ if (lpuart_is_32(sport))
	2780	+ lpuart32_setup_watermark_enable(sport);
	2781	+ else
	2782	+ lpuart_setup_watermark_enable(sport);
2341	2783
2342	2784	if (sport->lpuart_dma_rx_use) {
2343	2785	if (irq_wake) {
..	..	@@ -2348,20 +2790,15 @@
2348	2790	}
2349	2791	}
2350	2792
2351		- if (sport->dma_tx_chan && !lpuart_dma_tx_request(&sport->port)) {
2352		- init_waitqueue_head(&sport->dma_wait);
2353		- sport->lpuart_dma_tx_use = true;
2354		- writeb(readb(sport->port.membase + UARTCR5) \|
2355		- UARTCR5_TDMAS, sport->port.membase + UARTCR5);
2356		- } else {
2357		- sport->lpuart_dma_tx_use = false;
2358		- }
	2793	+ lpuart_tx_dma_startup(sport);
	2794	+
	2795	+ if (lpuart_is_32(sport))
	2796	+ lpuart32_configure(sport);
2359	2797
2360	2798	uart_resume_port(&lpuart_reg, &sport->port);
2361	2799
2362	2800	return 0;
2363	2801	}
2364		-#endif
2365	2802
2366	2803	static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume);
2367	2804