forked from ~ljy/RK356X_SDK_RELEASE
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hc
2023-12-06 08f87f769b595151be1afeff53e144f543faa614 
 kernel/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
....@@ -59,10 +59,12 @@
5959 	struct combphy_reg con2_for_sata;
6060 	struct combphy_reg con3_for_sata;
6161 	struct combphy_reg pipe_con0_for_sata;
62
+	struct combphy_reg pipe_con1_for_sata;
6263 	struct combphy_reg pipe_sgmii_mac_sel;
6364 	struct combphy_reg pipe_xpcs_phy_ready;
6465 	struct combphy_reg u3otg0_port_en;
6566 	struct combphy_reg u3otg1_port_en;
67
+	struct combphy_reg pipe_phy_grf_reset;
6668 };
6769 
6870 struct rockchip_combphy_cfg {
....@@ -251,6 +253,9 @@
251253 	if (ret)
252254 		goto err_clk;
253255 
256
+	if (cfg->pipe_phy_grf_reset.enable)
257
+		param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, false);
258
+
254259 	if (priv->mode == PHY_TYPE_USB3) {
255260 		ret = readx_poll_timeout_atomic(rockchip_combphy_is_ready,
256261 						priv, val,
....@@ -271,6 +276,10 @@
271276 static int rockchip_combphy_exit(struct phy *phy)
272277 {
273278 	struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
279
+	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
280
+
281
+	if (cfg->pipe_phy_grf_reset.enable)
282
+		param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, true);
274283 
275284 	clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
276285 	reset_control_assert(priv->phy_rst);
....@@ -308,6 +317,7 @@
308317 {
309318 	const struct rockchip_combphy_cfg *phy_cfg = priv->cfg;
310319 	int ret, mac_id;
320
+	u32 vals[4];
311321 
312322 	ret = devm_clk_bulk_get(dev, priv->num_clks, priv->clks);
313323 	if (ret == -EPROBE_DEFER)
....@@ -340,6 +350,11 @@
340350 	    (mac_id > 0))
341351 		param_write(priv->pipe_grf, &phy_cfg->grfcfg->pipe_sgmii_mac_sel,
342352 			    true);
353
+
354
+	if (!device_property_read_u32_array(dev, "rockchip,pcie1ln-sel-bits",
355
+					    vals, ARRAY_SIZE(vals)))
356
+		regmap_write(priv->pipe_grf, vals[0],
357
+			     (GENMASK(vals[2], vals[1]) << 16) | (vals[3] << vals[1]));
343358 
344359 	priv->apb_rst = devm_reset_control_get_optional(dev, "combphy-apb");
345360 	if (IS_ERR(priv->apb_rst)) {
....@@ -495,39 +510,15 @@
495510 			val |= 0x17d;
496511 			writel(val, priv->mmio + 0x100);
497512 		} else if (priv->mode == PHY_TYPE_PCIE) {
498
-			/* Set ssc_cnt[10:0]=00101111101 & 31.5KHz */
499
-			val = readl(priv->mmio + 0x100);
500
-			val &= ~GENMASK(10, 0);
501
-			val |= 0x17d;
502
-			writel(val, priv->mmio + 0x100);
503
-
504513 			/* tx_trim[14]=1, Enable the counting clock of the rterm detect */
505514 			val = readl(priv->mmio + 0x218);
506515 			val |= (1 << 14);
507516 			writel(val, priv->mmio + 0x218);
508
-
509
-			/* PLL KVCO tuning fine */
510
-			val = readl(priv->mmio + 0x18);
511
-			val &= ~(0x7 << 10);
512
-			val |= 0x2 << 10;
513
-			writel(val, priv->mmio + 0x18);
514
-
515
-			/* su_trim[6:4]=111, [10:7]=1001, [2:0]=000 */
516
-			val = readl(priv->mmio + 0x108);
517
-			val &= ~(0x7f7);
518
-			val |= 0x4f0;
519
-			writel(val, priv->mmio + 0x108);
520517 		}
521518 		break;
522519 	case 100000000:
523520 		param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
524521 		if (priv->mode == PHY_TYPE_PCIE) {
525
-			/* Set ssc_cnt[10:0]=11000110011 & 31.5KHz */
526
-			val = readl(priv->mmio + 0x100);
527
-			val &= ~GENMASK(10, 0);
528
-			val |= 0x633;
529
-			writel(val, priv->mmio + 0x100);
530
-
531522 			/* PLL KVCO tuning fine */
532523 			val = readl(priv->mmio + 0x18);
533524 			val &= ~(0x7 << 10);
....@@ -542,14 +533,6 @@
542533 	default:
543534 		dev_err(priv->dev, "Unsupported rate: %lu\n", rate);
544535 		return -EINVAL;
545
-	}
546
-
547
-	if (priv->mode == PHY_TYPE_PCIE) {
548
-		if (device_property_read_bool(priv->dev, "rockchip,enable-ssc")) {
549
-			val = readl(priv->mmio + 0x100);
550
-			val |= BIT(20);
551
-			writel(val, priv->mmio + 0x100);
552
-		}
553536 	}
554537 
555538 	return 0;
....@@ -588,6 +571,201 @@
588571 	.clks		= rk3528_clks,
589572 	.grfcfg		= &rk3528_combphy_grfcfgs,
590573 	.combphy_cfg	= rk3528_combphy_cfg,
574
+};
575
+
576
+static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
577
+{
578
+	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
579
+	struct clk *refclk = NULL;
580
+	unsigned long rate;
581
+	int i;
582
+	u32 val;
583
+
584
+	/* Configure PHY reference clock frequency */
585
+	for (i = 0; i < priv->num_clks; i++) {
586
+		if (!strncmp(priv->clks[i].id, "refclk", 6)) {
587
+			refclk = priv->clks[i].clk;
588
+			break;
589
+		}
590
+	}
591
+
592
+	if (!refclk) {
593
+		dev_err(priv->dev, "No refclk found\n");
594
+		return -EINVAL;
595
+	}
596
+
597
+	switch (priv->mode) {
598
+	case PHY_TYPE_PCIE:
599
+		/* Set SSC downward spread spectrum */
600
+		val = readl(priv->mmio + (0x1f << 2));
601
+		val &= ~GENMASK(5, 4);
602
+		val |= 0x01 << 4;
603
+		writel(val, priv->mmio + 0x7c);
604
+
605
+		param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
606
+		param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
607
+		param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
608
+		param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
609
+		break;
610
+	case PHY_TYPE_USB3:
611
+		/* Set SSC downward spread spectrum */
612
+		val = readl(priv->mmio + (0x1f << 2));
613
+		val &= ~GENMASK(5, 4);
614
+		val |= 0x01 << 4;
615
+		writel(val, priv->mmio + 0x7c);
616
+
617
+		/* Enable adaptive CTLE for USB3.0 Rx */
618
+		val = readl(priv->mmio + (0x0e << 2));
619
+		val &= ~GENMASK(0, 0);
620
+		val |= 0x01;
621
+		writel(val, priv->mmio + (0x0e << 2));
622
+
623
+		/* Set PLL KVCO fine tuning signals */
624
+		val = readl(priv->mmio + (0x20 << 2));
625
+		val &= ~(0x7 << 2);
626
+		val |= 0x2 << 2;
627
+		writel(val, priv->mmio + (0x20 << 2));
628
+
629
+		/* Set PLL LPF R1 to su_trim[10:7]=1001 */
630
+		writel(0x4, priv->mmio + (0xb << 2));
631
+
632
+		/* Set PLL input clock divider 1/2 */
633
+		val = readl(priv->mmio + (0x5 << 2));
634
+		val &= ~(0x3 << 6);
635
+		val |= 0x1 << 6;
636
+		writel(val, priv->mmio + (0x5 << 2));
637
+
638
+		/* Set PLL loop divider */
639
+		writel(0x32, priv->mmio + (0x11 << 2));
640
+
641
+		/* Set PLL KVCO to min and set PLL charge pump current to max */
642
+		writel(0xf0, priv->mmio + (0xa << 2));
643
+
644
+		/* Set Rx squelch input filler bandwidth */
645
+		writel(0x0e, priv->mmio + (0x14 << 2));
646
+
647
+		param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
648
+		param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
649
+		param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
650
+		param_write(priv->phy_grf, &cfg->usb_mode_set, true);
651
+		break;
652
+	default:
653
+		dev_err(priv->dev, "incompatible PHY type\n");
654
+		return -EINVAL;
655
+	}
656
+
657
+	rate = clk_get_rate(refclk);
658
+
659
+	switch (rate) {
660
+	case 24000000:
661
+		if (priv->mode == PHY_TYPE_USB3) {
662
+			/* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */
663
+			val = readl(priv->mmio + (0x0e << 2));
664
+			val &= ~GENMASK(7, 6);
665
+			val |= 0x01 << 6;
666
+			writel(val, priv->mmio + (0x0e << 2));
667
+
668
+			val = readl(priv->mmio + (0x0f << 2));
669
+			val &= ~GENMASK(7, 0);
670
+			val |= 0x5f;
671
+			writel(val, priv->mmio + (0x0f << 2));
672
+		}
673
+		break;
674
+	case 25000000:
675
+		param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
676
+		break;
677
+	case 100000000:
678
+		param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
679
+		if (priv->mode == PHY_TYPE_PCIE) {
680
+			/* PLL KVCO tuning fine */
681
+			val = readl(priv->mmio + (0x20 << 2));
682
+			val &= ~(0x7 << 2);
683
+			val |= 0x2 << 2;
684
+			writel(val, priv->mmio + (0x20 << 2));
685
+
686
+			/* Enable controlling random jitter, aka RMJ */
687
+			writel(0x4, priv->mmio + (0xb << 2));
688
+
689
+			val = readl(priv->mmio + (0x5 << 2));
690
+			val &= ~(0x3 << 6);
691
+			val |= 0x1 << 6;
692
+			writel(val, priv->mmio + (0x5 << 2));
693
+
694
+			writel(0x32, priv->mmio + (0x11 << 2));
695
+			writel(0xf0, priv->mmio + (0xa << 2));
696
+
697
+			/* CKDRV output swing adjust to 650mv */
698
+			val = readl(priv->mmio + (0xd << 2));
699
+			val &= ~(0xf << 1);
700
+			val |= 0xb;
701
+			writel(val, priv->mmio + (0xd << 2));
702
+		}
703
+		break;
704
+	default:
705
+		dev_err(priv->dev, "Unsupported rate: %lu\n", rate);
706
+		return -EINVAL;
707
+	}
708
+
709
+	if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) {
710
+		param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
711
+		if (priv->mode == PHY_TYPE_PCIE && rate == 100000000) {
712
+			val = readl(priv->mmio + (0xc << 2));
713
+			val |= 0x3 << 4 | 0x1 << 7;
714
+			writel(val, priv->mmio + (0xc << 2));
715
+
716
+			val = readl(priv->mmio + (0xd << 2));
717
+			val |= 0x1;
718
+			writel(val, priv->mmio + (0xd << 2));
719
+		}
720
+	}
721
+
722
+	if (device_property_read_bool(priv->dev, "rockchip,enable-ssc")) {
723
+		val = readl(priv->mmio + (0x7 << 2));
724
+		val |= BIT(4);
725
+		writel(val, priv->mmio + (0x7 << 2));
726
+	}
727
+
728
+	return 0;
729
+}
730
+
731
+static const struct rockchip_combphy_grfcfg rk3562_combphy_grfcfgs = {
732
+	/* pipe-phy-grf */
733
+	.pcie_mode_set		= { 0x0000, 5, 0, 0x00, 0x11 },
734
+	.usb_mode_set		= { 0x0000, 5, 0, 0x00, 0x04 },
735
+	.pipe_rxterm_set	= { 0x0000, 12, 12, 0x00, 0x01 },
736
+	.pipe_txelec_set	= { 0x0004, 1, 1, 0x00, 0x01 },
737
+	.pipe_txcomp_set	= { 0x0004, 4, 4, 0x00, 0x01 },
738
+	.pipe_clk_25m		= { 0x0004, 14, 13, 0x00, 0x01 },
739
+	.pipe_clk_100m		= { 0x0004, 14, 13, 0x00, 0x02 },
740
+	.pipe_phymode_sel	= { 0x0008, 1, 1, 0x00, 0x01 },
741
+	.pipe_rate_sel		= { 0x0008, 2, 2, 0x00, 0x01 },
742
+	.pipe_rxterm_sel	= { 0x0008, 8, 8, 0x00, 0x01 },
743
+	.pipe_txelec_sel	= { 0x0008, 12, 12, 0x00, 0x01 },
744
+	.pipe_txcomp_sel	= { 0x0008, 15, 15, 0x00, 0x01 },
745
+	.pipe_clk_ext		= { 0x000c, 9, 8, 0x02, 0x01 },
746
+	.pipe_sel_usb		= { 0x000c, 14, 13, 0x00, 0x01 },
747
+	.pipe_phy_status	= { 0x0034, 6, 6, 0x01, 0x00 },
748
+	.con0_for_pcie		= { 0x0000, 15, 0, 0x00, 0x1000 },
749
+	.con1_for_pcie		= { 0x0004, 15, 0, 0x00, 0x0000 },
750
+	.con2_for_pcie		= { 0x0008, 15, 0, 0x00, 0x0101 },
751
+	.con3_for_pcie		= { 0x000c, 15, 0, 0x00, 0x0200 },
752
+	.pipe_phy_grf_reset	= { 0x0014, 1, 0, 0x3, 0x1 },
753
+	/* peri-grf */
754
+	.u3otg0_port_en		= { 0x0094, 15, 0, 0x0181, 0x1100 },
755
+};
756
+
757
+static const struct clk_bulk_data rk3562_clks[] = {
758
+	{ .id = "refclk" },
759
+	{ .id = "apbclk" },
760
+	{ .id = "pipe_clk" },
761
+};
762
+
763
+static const struct rockchip_combphy_cfg rk3562_combphy_cfgs = {
764
+	.num_clks	= ARRAY_SIZE(rk3562_clks),
765
+	.clks		= rk3562_clks,
766
+	.grfcfg		= &rk3562_combphy_grfcfgs,
767
+	.combphy_cfg	= rk3562_combphy_cfg,
768
+	.force_det_out	= true,
591769 };
592770 
593771 static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
....@@ -817,15 +995,294 @@
817995 	.force_det_out	= true,
818996 };
819997 
998
+static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
999
+{
1000
+	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
1001
+	struct clk *refclk = NULL;
1002
+	unsigned long rate;
1003
+	int i;
1004
+	u32 val;
1005
+
1006
+	/* Configure PHY reference clock frequency */
1007
+	for (i = 0; i < priv->num_clks; i++) {
1008
+		if (!strncmp(priv->clks[i].id, "refclk", 6)) {
1009
+			refclk = priv->clks[i].clk;
1010
+			break;
1011
+		}
1012
+	}
1013
+
1014
+	if (!refclk) {
1015
+		dev_err(priv->dev, "No refclk found\n");
1016
+		return -EINVAL;
1017
+	}
1018
+
1019
+	switch (priv->mode) {
1020
+	case PHY_TYPE_PCIE:
1021
+		/* Set SSC downward spread spectrum */
1022
+		val = readl(priv->mmio + (0x1f << 2));
1023
+		val &= ~GENMASK(5, 4);
1024
+		val |= 0x01 << 4;
1025
+		writel(val, priv->mmio + 0x7c);
1026
+
1027
+		param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
1028
+		param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
1029
+		param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
1030
+		param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
1031
+		break;
1032
+	case PHY_TYPE_USB3:
1033
+		/* Set SSC downward spread spectrum */
1034
+		val = readl(priv->mmio + (0x1f << 2));
1035
+		val &= ~GENMASK(5, 4);
1036
+		val |= 0x01 << 4;
1037
+		writel(val, priv->mmio + 0x7c);
1038
+
1039
+		/* Enable adaptive CTLE for USB3.0 Rx */
1040
+		val = readl(priv->mmio + (0x0e << 2));
1041
+		val &= ~GENMASK(0, 0);
1042
+		val |= 0x01;
1043
+		writel(val, priv->mmio + (0x0e << 2));
1044
+
1045
+		/* Set PLL KVCO fine tuning signals */
1046
+		val = readl(priv->mmio + (0x20 << 2));
1047
+		val &= ~(0x7 << 2);
1048
+		val |= 0x2 << 2;
1049
+		writel(val, priv->mmio + (0x20 << 2));
1050
+
1051
+		/* Set PLL LPF R1 to su_trim[10:7]=1001 */
1052
+		writel(0x4, priv->mmio + (0xb << 2));
1053
+
1054
+		/* Set PLL input clock divider 1/2 */
1055
+		val = readl(priv->mmio + (0x5 << 2));
1056
+		val &= ~(0x3 << 6);
1057
+		val |= 0x1 << 6;
1058
+		writel(val, priv->mmio + (0x5 << 2));
1059
+
1060
+		/* Set PLL loop divider */
1061
+		writel(0x32, priv->mmio + (0x11 << 2));
1062
+
1063
+		/* Set PLL KVCO to min and set PLL charge pump current to max */
1064
+		writel(0xf0, priv->mmio + (0xa << 2));
1065
+
1066
+		/* Set Rx squelch input filler bandwidth */
1067
+		writel(0x0d, priv->mmio + (0x14 << 2));
1068
+
1069
+		param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
1070
+		param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
1071
+		param_write(priv->phy_grf, &cfg->usb_mode_set, true);
1072
+		break;
1073
+	case PHY_TYPE_SATA:
1074
+		/* Enable adaptive CTLE for SATA Rx */
1075
+		val = readl(priv->mmio + (0x0e << 2));
1076
+		val &= ~GENMASK(0, 0);
1077
+		val |= 0x01;
1078
+		writel(val, priv->mmio + (0x0e << 2));
1079
+		/* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */
1080
+		writel(0x8F, priv->mmio + (0x06 << 2));
1081
+
1082
+		param_write(priv->phy_grf, &cfg->con0_for_sata, true);
1083
+		param_write(priv->phy_grf, &cfg->con1_for_sata, true);
1084
+		param_write(priv->phy_grf, &cfg->con2_for_sata, true);
1085
+		param_write(priv->phy_grf, &cfg->con3_for_sata, true);
1086
+		param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
1087
+		param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true);
1088
+		break;
1089
+	case PHY_TYPE_SGMII:
1090
+	case PHY_TYPE_QSGMII:
1091
+	default:
1092
+		dev_err(priv->dev, "incompatible PHY type\n");
1093
+		return -EINVAL;
1094
+	}
1095
+
1096
+	rate = clk_get_rate(refclk);
1097
+
1098
+	switch (rate) {
1099
+	case 24000000:
1100
+		param_write(priv->phy_grf, &cfg->pipe_clk_24m, true);
1101
+		if (priv->mode == PHY_TYPE_USB3 || priv->mode == PHY_TYPE_SATA) {
1102
+			/* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */
1103
+			val = readl(priv->mmio + (0x0e << 2));
1104
+			val &= ~GENMASK(7, 6);
1105
+			val |= 0x01 << 6;
1106
+			writel(val, priv->mmio + (0x0e << 2));
1107
+
1108
+			val = readl(priv->mmio + (0x0f << 2));
1109
+			val &= ~GENMASK(7, 0);
1110
+			val |= 0x5f;
1111
+			writel(val, priv->mmio + (0x0f << 2));
1112
+		} else if (priv->mode == PHY_TYPE_PCIE) {
1113
+			/* PLL KVCO tuning fine */
1114
+			val = readl(priv->mmio + (0x20 << 2));
1115
+			val &= ~GENMASK(4, 2);
1116
+			val |= 0x4 << 2;
1117
+			writel(val, priv->mmio + (0x20 << 2));
1118
+
1119
+			/* Set up rx_trim */
1120
+			val = 0x0;
1121
+			writel(val, priv->mmio + (0x1b << 2));
1122
+
1123
+			/* Set up su_trim: T0_1 */
1124
+			val = 0x90;
1125
+			writel(val, priv->mmio + (0xa << 2));
1126
+			val = 0x02;
1127
+			writel(val, priv->mmio + (0xb << 2));
1128
+			val = 0x57;
1129
+			writel(val, priv->mmio + (0xd << 2));
1130
+
1131
+			val = 0x5f;
1132
+			writel(val, priv->mmio + (0xf << 2));
1133
+		}
1134
+		break;
1135
+	case 25000000:
1136
+		param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
1137
+		break;
1138
+	case 100000000:
1139
+		param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
1140
+		if (priv->mode == PHY_TYPE_PCIE) {
1141
+			/* gate_tx_pck_sel length select work for L1SS */
1142
+			val = 0xc0;
1143
+			writel(val, priv->mmio + 0x74);
1144
+
1145
+			/* PLL KVCO tuning fine */
1146
+			val = readl(priv->mmio + (0x20 << 2));
1147
+			val &= ~GENMASK(4, 2);
1148
+			val |= 0x4 << 2;
1149
+			writel(val, priv->mmio + (0x20 << 2));
1150
+
1151
+			/* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */
1152
+			val = 0x4c;
1153
+			writel(val, priv->mmio + (0x1b << 2));
1154
+
1155
+			/* Set up su_trim: T3_P1 650mv */
1156
+			val = 0x90;
1157
+			writel(val, priv->mmio + (0xa << 2));
1158
+			val = 0x43;
1159
+			writel(val, priv->mmio + (0xb << 2));
1160
+			val = 0x88;
1161
+			writel(val, priv->mmio + (0xc << 2));
1162
+			val = 0x56;
1163
+			writel(val, priv->mmio + (0xd << 2));
1164
+		} else if (priv->mode == PHY_TYPE_SATA) {
1165
+			/* downward spread spectrum +500ppm */
1166
+			val = readl(priv->mmio + (0x1f << 2));
1167
+			val &= ~GENMASK(7, 4);
1168
+			val |= 0x50;
1169
+			writel(val, priv->mmio + (0x1f << 2));
1170
+
1171
+			/* ssc ppm adjust to 3500ppm */
1172
+			val = readl(priv->mmio + (0x9 << 2));
1173
+			val &= ~GENMASK(3, 0);
1174
+			val |= 0x7;
1175
+			writel(val, priv->mmio + (0x9 << 2));
1176
+		}
1177
+		break;
1178
+	default:
1179
+		dev_err(priv->dev, "Unsupported rate: %lu\n", rate);
1180
+		return -EINVAL;
1181
+	}
1182
+
1183
+	if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) {
1184
+		param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
1185
+		if (priv->mode == PHY_TYPE_PCIE && rate == 100000000) {
1186
+			val = 0x10;
1187
+			writel(val, priv->mmio + (0x20 << 2));
1188
+
1189
+			val = 0x0c;
1190
+			writel(val, priv->mmio + (0x1b << 2));
1191
+
1192
+			/* Set up su_trim: T3_P1 650mv */
1193
+			val = 0x90;
1194
+			writel(val, priv->mmio + (0xa << 2));
1195
+			val = 0x43;
1196
+			writel(val, priv->mmio + (0xb << 2));
1197
+			val = 0x88;
1198
+			writel(val, priv->mmio + (0xc << 2));
1199
+			val = 0x56;
1200
+			writel(val, priv->mmio + (0xd << 2));
1201
+		}
1202
+	}
1203
+
1204
+	if (device_property_read_bool(priv->dev, "rockchip,enable-ssc")) {
1205
+		val = readl(priv->mmio + (0x7 << 2));
1206
+		val |= BIT(4);
1207
+		writel(val, priv->mmio + (0x7 << 2));
1208
+
1209
+		if (priv->mode == PHY_TYPE_PCIE && rate == 24000000) {
1210
+			/* Xin24M T0_1 650mV */
1211
+			writel(0x00, priv->mmio + (0x10 << 2));
1212
+			writel(0x32, priv->mmio + (0x11 << 2));
1213
+			writel(0x00, priv->mmio + (0x1b << 2));
1214
+			writel(0x90, priv->mmio + (0x0a << 2));
1215
+			writel(0x02, priv->mmio + (0x0b << 2));
1216
+			writel(0x08, priv->mmio + (0x0c << 2));
1217
+			writel(0x57, priv->mmio + (0x0d << 2));
1218
+			writel(0x40, priv->mmio + (0x0e << 2));
1219
+			writel(0x5f, priv->mmio + (0x0f << 2));
1220
+			writel(0x10, priv->mmio + (0x20 << 2));
1221
+		}
1222
+	}
1223
+
1224
+	return 0;
1225
+}
1226
+
1227
+static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = {
1228
+	/* pipe-phy-grf */
1229
+	.pcie_mode_set		= { 0x0000, 5, 0, 0x00, 0x11 },
1230
+	.usb_mode_set		= { 0x0000, 5, 0, 0x00, 0x04 },
1231
+	.pipe_rxterm_set	= { 0x0000, 12, 12, 0x00, 0x01 },
1232
+	.pipe_txelec_set	= { 0x0004, 1, 1, 0x00, 0x01 },
1233
+	.pipe_txcomp_set	= { 0x0004, 4, 4, 0x00, 0x01 },
1234
+	.pipe_clk_24m		= { 0x0004, 14, 13, 0x00, 0x00 },
1235
+	.pipe_clk_25m		= { 0x0004, 14, 13, 0x00, 0x01 },
1236
+	.pipe_clk_100m		= { 0x0004, 14, 13, 0x00, 0x02 },
1237
+	.pipe_rxterm_sel	= { 0x0008, 8, 8, 0x00, 0x01 },
1238
+	.pipe_txelec_sel	= { 0x0008, 12, 12, 0x00, 0x01 },
1239
+	.pipe_txcomp_sel	= { 0x0008, 15, 15, 0x00, 0x01 },
1240
+	.pipe_clk_ext		= { 0x000c, 9, 8, 0x02, 0x01 },
1241
+	.pipe_phy_status	= { 0x0034, 6, 6, 0x01, 0x00 },
1242
+	.con0_for_pcie		= { 0x0000, 15, 0, 0x00, 0x1000 },
1243
+	.con1_for_pcie		= { 0x0004, 15, 0, 0x00, 0x0000 },
1244
+	.con2_for_pcie		= { 0x0008, 15, 0, 0x00, 0x0101 },
1245
+	.con3_for_pcie		= { 0x000c, 15, 0, 0x00, 0x0200 },
1246
+	.con0_for_sata		= { 0x0000, 15, 0, 0x00, 0x0129 },
1247
+	.con1_for_sata		= { 0x0004, 15, 0, 0x00, 0x0000 },
1248
+	.con2_for_sata		= { 0x0008, 15, 0, 0x00, 0x80c1 },
1249
+	.con3_for_sata		= { 0x000c, 15, 0, 0x00, 0x0407 },
1250
+	/* pipe-grf */
1251
+	.pipe_con0_for_sata	= { 0x0000, 11, 5, 0x00, 0x22 },
1252
+	.pipe_con1_for_sata	= { 0x0004, 2, 0, 0x00, 0x2 },
1253
+};
1254
+
1255
+static const struct clk_bulk_data rk3588_clks[] = {
1256
+	{ .id = "refclk" },
1257
+	{ .id = "apbclk" },
1258
+	{ .id = "phpclk" },
1259
+};
1260
+
1261
+static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = {
1262
+	.num_clks	= ARRAY_SIZE(rk3588_clks),
1263
+	.clks		= rk3588_clks,
1264
+	.grfcfg		= &rk3588_combphy_grfcfgs,
1265
+	.combphy_cfg	= rk3588_combphy_cfg,
1266
+	.force_det_out	= true,
1267
+};
1268
+
8201269 static const struct of_device_id rockchip_combphy_of_match[] = {
8211270 	{
8221271 		.compatible = "rockchip,rk3528-naneng-combphy",
8231272 		.data = &rk3528_combphy_cfgs,
8241273 	},
8251274 	{
1275
+		.compatible = "rockchip,rk3562-naneng-combphy",
1276
+		.data = &rk3562_combphy_cfgs,
1277
+	},
1278
+	{
8261279 		.compatible = "rockchip,rk3568-naneng-combphy",
8271280 		.data = &rk3568_combphy_cfgs,
8281281 	},
1282
+	{
1283
+		.compatible = "rockchip,rk3588-naneng-combphy",
1284
+		.data = &rk3588_combphy_cfgs,
1285
+	},
8291286 	{ },
8301287 };
8311288 MODULE_DEVICE_TABLE(of, rockchip_combphy_of_match);