forked from ~ljy/RK356X_SDK_RELEASE
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hc
2023-12-06 08f87f769b595151be1afeff53e144f543faa614 
 kernel/drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c
....@@ -82,6 +82,10 @@
8282 #define PCIE_CLIENT_LTSSM_STATUS	0x300
8383 #define PCIE_CLIENT_INTR_MASK		0x24
8484 #define PCIE_LTSSM_ENABLE_ENHANCE       BIT(4)
85
+#define PCIE_CLIENT_MSI_GEN_CON		0x38
86
+
87
+#define PCIe_CLIENT_MSI_OBJ_IRQ		0	/* rockchip ep object special irq */
88
+
8589 #define PCIE_ELBI_REG_NUM		0x2
8690 #define PCIE_ELBI_LOCAL_BASE		0x200e00
8791 
....@@ -99,6 +103,10 @@
99103 
100104 #define PCIE_DBI_SIZE			0x400000
101105 
106
+#define PCIE_EP_OBJ_INFO_DRV_VERSION	0x00000001
107
+
108
+#define PCIE_BAR_MAX_NUM		6
109
+
102110 struct rockchip_pcie {
103111 	struct dw_pcie			pci;
104112 	void __iomem			*apb_base;
....@@ -113,13 +121,15 @@
113121 	u32				num_ib_windows;
114122 	u32				num_ob_windows;
115123 	phys_addr_t			*outbound_addr;
116
-	u8				bar_to_atu[6];
117
-	dma_addr_t			ib_target_address;
118
-	u32				ib_target_size;
119
-	void				*ib_target_base;
124
+	u8				bar_to_atu[PCIE_BAR_MAX_NUM];
125
+	dma_addr_t			ib_target_address[PCIE_BAR_MAX_NUM];
126
+	u32				ib_target_size[PCIE_BAR_MAX_NUM];
127
+	void				*ib_target_base[PCIE_BAR_MAX_NUM];
120128 	struct dma_trx_obj		*dma_obj;
121129 	struct fasync_struct		*async;
122130 	phys_addr_t			dbi_base_physical;
131
+	struct pcie_ep_obj_info		*obj_info;
132
+	enum pcie_ep_mmap_resource	cur_mmap_res;
123133 };
124134 
125135 struct rockchip_pcie_misc_dev {
....@@ -138,6 +148,12 @@
138148 };
139149 
140150 MODULE_DEVICE_TABLE(of, rockchip_pcie_ep_of_match);
151
+
152
+static void rockchip_pcie_devmode_update(struct rockchip_pcie *rockchip, int mode, int submode)
153
+{
154
+	rockchip->obj_info->devmode.mode = mode;
155
+	rockchip->obj_info->devmode.submode = submode;
156
+}
141157 
142158 static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip, u32 reg)
143159 {
....@@ -183,9 +199,10 @@
183199 	struct device_node *np = dev->of_node;
184200 	void *addr;
185201 	struct resource *dbi_base;
186
-	struct resource *apb_base;
187202 	struct device_node *mem;
188203 	struct resource reg;
204
+	char name[8];
205
+	int i, idx;
189206 
190207 	dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM,
191208 						"pcie-dbi");
....@@ -197,17 +214,14 @@
197214 	rockchip->pci.dbi_base = devm_ioremap_resource(dev, dbi_base);
198215 	if (IS_ERR(rockchip->pci.dbi_base))
199216 		return PTR_ERR(rockchip->pci.dbi_base);
217
+	rockchip->pci.atu_base = rockchip->pci.dbi_base + DEFAULT_DBI_ATU_OFFSET;
200218 	rockchip->dbi_base_physical = dbi_base->start;
201219 
202
-	apb_base = platform_get_resource_byname(pdev, IORESOURCE_MEM,
203
-						"pcie-apb");
204
-	if (!apb_base) {
220
+	rockchip->apb_base = devm_platform_ioremap_resource_byname(pdev, "pcie-apb");
221
+	if (!rockchip->apb_base) {
205222 		dev_err(dev, "get pcie-apb failed\n");
206223 		return -ENODEV;
207224 	}
208
-	rockchip->apb_base = devm_ioremap_resource(dev, apb_base);
209
-	if (IS_ERR(rockchip->apb_base))
210
-		return PTR_ERR(rockchip->apb_base);
211225 
212226 	rockchip->rst_gpio = devm_gpiod_get_optional(dev, "reset",
213227 						     GPIOD_OUT_HIGH);
....@@ -255,22 +269,42 @@
255269 
256270 	rockchip->outbound_addr = addr;
257271 
258
-	mem = of_parse_phandle(np, "memory-region", 0);
259
-	if (!mem) {
260
-		dev_err(dev, "missing \"memory-region\" property\n");
261
-		return -ENODEV;
272
+	for (i = 0; i < PCIE_BAR_MAX_NUM; i++) {
273
+		snprintf(name, sizeof(name), "bar%d", i);
274
+		idx = of_property_match_string(np, "memory-region-names", name);
275
+		if (idx < 0)
276
+			continue;
277
+
278
+		mem = of_parse_phandle(np, "memory-region", idx);
279
+		if (!mem) {
280
+			dev_err(dev, "missing \"memory-region\" %s property\n", name);
281
+			return -ENODEV;
282
+		}
283
+
284
+		ret = of_address_to_resource(mem, 0, &reg);
285
+		if (ret < 0) {
286
+			dev_err(dev, "missing \"reg\" %s property\n", name);
287
+			return -ENODEV;
288
+		}
289
+
290
+		rockchip->ib_target_address[i] = reg.start;
291
+		rockchip->ib_target_size[i] = resource_size(&reg);
292
+		rockchip->ib_target_base[i] = rockchip_pcie_map_kernel(reg.start,
293
+							resource_size(&reg));
294
+		dev_info(dev, "%s: assigned [0x%llx-%llx]\n", name, rockchip->ib_target_address[i],
295
+			rockchip->ib_target_address[i] + rockchip->ib_target_size[i] - 1);
262296 	}
263297 
264
-	ret = of_address_to_resource(mem, 0, &reg);
265
-	if (ret < 0) {
266
-		dev_err(dev, "missing \"reg\" property\n");
298
+	if (rockchip->ib_target_size[0]) {
299
+		rockchip->obj_info = (struct pcie_ep_obj_info *)rockchip->ib_target_base[0];
300
+		memset_io(rockchip->obj_info, 0, sizeof(struct pcie_ep_obj_info));
301
+		rockchip->obj_info->magic = PCIE_EP_OBJ_INFO_MAGIC;
302
+		rockchip->obj_info->version = PCIE_EP_OBJ_INFO_DRV_VERSION;
303
+		rockchip_pcie_devmode_update(rockchip, RKEP_MODE_KERNEL, RKEP_SMODE_INIT);
304
+	} else {
305
+		dev_err(dev, "missing bar0 memory region\n");
267306 		return -ENODEV;
268307 	}
269
-
270
-	rockchip->ib_target_address = reg.start;
271
-	rockchip->ib_target_size = resource_size(&reg);
272
-	rockchip->ib_target_base = rockchip_pcie_map_kernel(reg.start,
273
-						resource_size(&reg));
274308 
275309 	return 0;
276310 }
....@@ -485,24 +519,27 @@
485519 
486520 	resbar_base = rockchip_pci_find_resbar_capability(rockchip);
487521 
488
-	/* Resize BAR0 4M 32bits, BAR2 64M 64bits-pref */
489
-	bar = 0;
522
+	/* Resize BAR0 4M 32bits, BAR2 64M 64bits-pref, BAR4 1MB 32bits */
523
+	bar = BAR_0;
490524 	dw_pcie_writel_dbi(pci, resbar_base + 0x4 + bar * 0x8, 0xfffff0);
491525 	dw_pcie_writel_dbi(pci, resbar_base + 0x8 + bar * 0x8, 0x2c0);
492
-	rockchip_pcie_ep_set_bar_flag(rockchip, BAR_0, PCI_BASE_ADDRESS_MEM_TYPE_32);
526
+	rockchip_pcie_ep_set_bar_flag(rockchip, bar, PCI_BASE_ADDRESS_MEM_TYPE_32);
493527 
494
-	bar = 2;
528
+	bar = BAR_2;
495529 	dw_pcie_writel_dbi(pci, resbar_base + 0x4 + bar * 0x8, 0xfffff0);
496530 	dw_pcie_writel_dbi(pci, resbar_base + 0x8 + bar * 0x8, 0x6c0);
497
-	rockchip_pcie_ep_set_bar_flag(rockchip, BAR_2,
531
+	rockchip_pcie_ep_set_bar_flag(rockchip, bar,
498532 				      PCI_BASE_ADDRESS_MEM_PREFETCH | PCI_BASE_ADDRESS_MEM_TYPE_64);
499533 
500
-	/* Disable BAR1 BAR4 BAR5*/
501
-	bar = 1;
534
+	bar = BAR_4;
535
+	dw_pcie_writel_dbi(pci, resbar_base + 0x4 + bar * 0x8, 0xfffff0);
536
+	dw_pcie_writel_dbi(pci, resbar_base + 0x8 + bar * 0x8, 0xc0);
537
+	rockchip_pcie_ep_set_bar_flag(rockchip, bar, PCI_BASE_ADDRESS_MEM_TYPE_32);
538
+
539
+	/* Disable BAR1 BAR5*/
540
+	bar = BAR_1;
502541 	dw_pcie_writel_dbi(pci, PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + bar * 4, 0);
503
-	bar = 4;
504
-	dw_pcie_writel_dbi(pci, PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + bar * 4, 0);
505
-	bar = 5;
542
+	bar = BAR_5;
506543 	dw_pcie_writel_dbi(pci, PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + bar * 4, 0);
507544 }
508545 
....@@ -514,14 +551,13 @@
514551 	dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE, 0x0580);
515552 }
516553 
517
-static int rockchip_pcie_ep_set_bar(struct rockchip_pcie *rockchip)
554
+static int rockchip_pcie_ep_set_bar(struct rockchip_pcie *rockchip, enum pci_barno bar,
555
+				    dma_addr_t cpu_addr)
518556 {
519557 	int ret;
520558 	u32 free_win;
521559 	struct dw_pcie *pci = &rockchip->pci;
522
-	enum pci_barno bar;
523560 	enum dw_pcie_as_type as_type;
524
-	dma_addr_t cpu_addr;
525561 
526562 	free_win = find_first_zero_bit(rockchip->ib_window_map,
527563 				       rockchip->num_ib_windows);
....@@ -531,10 +567,8 @@
531567 	}
532568 
533569 	as_type = DW_PCIE_AS_MEM;
534
-	bar = BAR_0;
535
-	cpu_addr = rockchip->ib_target_address;
536570 
537
-	ret = dw_pcie_prog_inbound_atu(pci, free_win, bar, cpu_addr, as_type);
571
+	ret = dw_pcie_prog_inbound_atu(pci, 0, free_win, bar, cpu_addr, as_type);
538572 	if (ret < 0) {
539573 		dev_err(pci->dev, "Failed to program IB window\n");
540574 		return ret;
....@@ -544,7 +578,6 @@
544578 	set_bit(free_win, rockchip->ib_window_map);
545579 
546580 	return 0;
547
-
548581 }
549582 
550583 static void rockchip_pcie_fast_link_setup(struct rockchip_pcie *rockchip)
....@@ -571,87 +604,112 @@
571604 static void rockchip_pcie_local_elbi_enable(struct rockchip_pcie *rockchip)
572605 {
573606 	int i;
574
-	u32 dlbi_reg;
607
+	u32 elbi_reg;
575608 	struct dw_pcie *pci = &rockchip->pci;
576609 
577610 	for (i = 0; i < PCIE_ELBI_REG_NUM; i++) {
578
-		dlbi_reg = PCIE_ELBI_LOCAL_BASE + PCIE_ELBI_LOCAL_ENABLE_OFF +
611
+		elbi_reg = PCIE_ELBI_LOCAL_BASE + PCIE_ELBI_LOCAL_ENABLE_OFF +
579612 			   i * 4;
580
-		dw_pcie_writel_dbi(pci, dlbi_reg, 0xffff0000);
613
+		dw_pcie_writel_dbi(pci, elbi_reg, 0xffff0000);
581614 	}
582615 }
583616 
584617 static void rockchip_pcie_elbi_clear(struct rockchip_pcie *rockchip)
585618 {
586619 	int i;
587
-	u32 dlbi_reg;
620
+	u32 elbi_reg;
588621 	struct dw_pcie *pci = &rockchip->pci;
589622 	u32 val;
590623 
591624 	for (i = 0; i < PCIE_ELBI_REG_NUM; i++) {
592
-		dlbi_reg = PCIE_ELBI_LOCAL_BASE + i * 4;
593
-		val = dw_pcie_readl_dbi(pci, dlbi_reg);
625
+		elbi_reg = PCIE_ELBI_LOCAL_BASE + i * 4;
626
+		val = dw_pcie_readl_dbi(pci, elbi_reg);
594627 		val <<= 16;
595
-		dw_pcie_writel_dbi(pci, dlbi_reg, val);
628
+		dw_pcie_writel_dbi(pci, elbi_reg, val);
596629 	}
630
+}
631
+
632
+static void rockchip_pcie_raise_msi_irq(struct rockchip_pcie *rockchip, u8 interrupt_num)
633
+{
634
+	rockchip_pcie_writel_apb(rockchip, BIT(interrupt_num), PCIE_CLIENT_MSI_GEN_CON);
597635 }
598636 
599637 static irqreturn_t rockchip_pcie_sys_irq_handler(int irq, void *arg)
600638 {
601639 	struct rockchip_pcie *rockchip = arg;
602640 	struct dw_pcie *pci = &rockchip->pci;
603
-	u32 dlbi_reg;
641
+	u32 elbi_reg;
604642 	u32 chn;
605
-	union int_status status;
643
+	union int_status wr_status, rd_status;
606644 	union int_clear clears;
607
-	u32 reg, val;
645
+	u32 reg, val, mask;
646
+	bool sigio = false;
608647 
609648 	/* ELBI helper, only check the valid bits, and discard the rest interrupts */
610
-	dlbi_reg = dw_pcie_readl_dbi(pci, PCIE_ELBI_LOCAL_BASE + PCIE_ELBI_APP_ELBI_INT_GEN0);
611
-	if (dlbi_reg & PCIE_ELBI_APP_ELBI_INT_GEN0_SIGIO) {
612
-		dev_dbg(rockchip->pci.dev, "SIGIO\n");
613
-		kill_fasync(&rockchip->async, SIGIO, POLL_IN);
649
+	elbi_reg = dw_pcie_readl_dbi(pci, PCIE_ELBI_LOCAL_BASE + PCIE_ELBI_APP_ELBI_INT_GEN0);
650
+	if (elbi_reg & PCIE_ELBI_APP_ELBI_INT_GEN0_SIGIO) {
651
+		sigio = true;
652
+		rockchip->obj_info->irq_type_ep = OBJ_IRQ_ELBI;
653
+		rockchip_pcie_elbi_clear(rockchip);
654
+		goto out;
614655 	}
615656 
616
-	rockchip_pcie_elbi_clear(rockchip);
617
-
618657 	/* DMA helper */
619
-	status.asdword = dw_pcie_readl_dbi(pci, PCIE_DMA_OFFSET +
620
-					   PCIE_DMA_WR_INT_STATUS);
658
+	mask = dw_pcie_readl_dbi(pci, PCIE_DMA_OFFSET + PCIE_DMA_WR_INT_MASK);
659
+	wr_status.asdword = dw_pcie_readl_dbi(pci, PCIE_DMA_OFFSET + PCIE_DMA_WR_INT_STATUS) & (~mask);
660
+	mask = dw_pcie_readl_dbi(pci, PCIE_DMA_OFFSET + PCIE_DMA_RD_INT_MASK);
661
+	rd_status.asdword = dw_pcie_readl_dbi(pci, PCIE_DMA_OFFSET + PCIE_DMA_RD_INT_STATUS) & (~mask);
662
+
621663 	for (chn = 0; chn < PCIE_DMA_CHANEL_MAX_NUM; chn++) {
622
-		if (status.donesta & BIT(chn)) {
623
-			clears.doneclr = 0x1 << chn;
664
+		if (wr_status.donesta & BIT(chn)) {
665
+			clears.doneclr = BIT(chn);
624666 			dw_pcie_writel_dbi(pci, PCIE_DMA_OFFSET +
625667 					PCIE_DMA_WR_INT_CLEAR, clears.asdword);
626668 			if (rockchip->dma_obj && rockchip->dma_obj->cb)
627669 				rockchip->dma_obj->cb(rockchip->dma_obj, chn, DMA_TO_BUS);
628670 		}
629671 
630
-		if (status.abortsta & BIT(chn)) {
672
+		if (wr_status.abortsta & BIT(chn)) {
631673 			dev_err(pci->dev, "%s, abort\n", __func__);
632
-			clears.abortclr = 0x1 << chn;
674
+			clears.abortclr = BIT(chn);
633675 			dw_pcie_writel_dbi(pci, PCIE_DMA_OFFSET +
634676 					PCIE_DMA_WR_INT_CLEAR, clears.asdword);
635677 		}
636678 	}
637679 
638
-	status.asdword = dw_pcie_readl_dbi(pci, PCIE_DMA_OFFSET +
639
-					   PCIE_DMA_RD_INT_STATUS);
640680 	for (chn = 0; chn < PCIE_DMA_CHANEL_MAX_NUM; chn++) {
641
-		if (status.donesta & BIT(chn)) {
642
-			clears.doneclr = 0x1 << chn;
681
+		if (rd_status.donesta & BIT(chn)) {
682
+			clears.doneclr = BIT(chn);
643683 			dw_pcie_writel_dbi(pci, PCIE_DMA_OFFSET +
644684 					PCIE_DMA_RD_INT_CLEAR, clears.asdword);
645685 			if (rockchip->dma_obj && rockchip->dma_obj->cb)
646686 				rockchip->dma_obj->cb(rockchip->dma_obj, chn, DMA_FROM_BUS);
647687 		}
648688 
649
-		if (status.abortsta & BIT(chn)) {
689
+		if (rd_status.abortsta & BIT(chn)) {
650690 			dev_err(pci->dev, "%s, abort\n", __func__);
651
-			clears.abortclr = 0x1 << chn;
691
+			clears.abortclr = BIT(chn);
652692 			dw_pcie_writel_dbi(pci, PCIE_DMA_OFFSET +
653693 					PCIE_DMA_RD_INT_CLEAR, clears.asdword);
654694 		}
695
+	}
696
+
697
+	if (wr_status.asdword || rd_status.asdword) {
698
+		rockchip->obj_info->irq_type_rc = OBJ_IRQ_DMA;
699
+		rockchip->obj_info->dma_status_rc.wr |= wr_status.asdword;
700
+		rockchip->obj_info->dma_status_rc.rd |= rd_status.asdword;
701
+		rockchip_pcie_raise_msi_irq(rockchip, PCIe_CLIENT_MSI_OBJ_IRQ);
702
+
703
+		rockchip->obj_info->irq_type_ep = OBJ_IRQ_DMA;
704
+		rockchip->obj_info->dma_status_ep.wr |= wr_status.asdword;
705
+		rockchip->obj_info->dma_status_ep.rd |= rd_status.asdword;
706
+		sigio = true;
707
+	}
708
+
709
+out:
710
+	if (sigio) {
711
+		dev_dbg(rockchip->pci.dev, "SIGIO\n");
712
+		kill_fasync(&rockchip->async, SIGIO, POLL_IN);
655713 	}
656714 
657715 	reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_MISC);
....@@ -706,7 +764,7 @@
706764 	if (!rockchip_pcie_udma_enabled(rockchip))
707765 		return 0;
708766 
709
-	rockchip->dma_obj = pcie_dw_dmatest_register(pci, true);
767
+	rockchip->dma_obj = pcie_dw_dmatest_register(pci->dev, true);
710768 	if (IS_ERR(rockchip->dma_obj)) {
711769 		dev_err(rockchip->pci.dev, "failed to prepare dmatest\n");
712770 		return -EINVAL;
....@@ -812,6 +870,56 @@
812870 	table->start.chnl = table->chn;
813871 }
814872 
873
+static int rockchip_pcie_get_dma_status(struct dma_trx_obj *obj, u8 chn, enum dma_dir dir)
874
+{
875
+	struct rockchip_pcie *rockchip = dev_get_drvdata(obj->dev);
876
+	struct dw_pcie *pci = &rockchip->pci;
877
+	union int_status status;
878
+	union int_clear clears;
879
+	int ret = 0;
880
+
881
+	dev_dbg(pci->dev, "%s %x %x\n", __func__,
882
+		dw_pcie_readl_dbi(pci, PCIE_DMA_OFFSET + PCIE_DMA_WR_INT_STATUS),
883
+		dw_pcie_readl_dbi(pci, PCIE_DMA_OFFSET + PCIE_DMA_RD_INT_STATUS));
884
+
885
+	if (dir == DMA_TO_BUS) {
886
+		status.asdword = dw_pcie_readl_dbi(pci, PCIE_DMA_OFFSET + PCIE_DMA_WR_INT_STATUS);
887
+		if (status.donesta & BIT(chn)) {
888
+			clears.doneclr = BIT(chn);
889
+			dw_pcie_writel_dbi(pci, PCIE_DMA_OFFSET +
890
+					   PCIE_DMA_WR_INT_CLEAR, clears.asdword);
891
+			ret = 1;
892
+		}
893
+
894
+		if (status.abortsta & BIT(chn)) {
895
+			dev_err(pci->dev, "%s, write abort\n", __func__);
896
+			clears.abortclr = BIT(chn);
897
+			dw_pcie_writel_dbi(pci, PCIE_DMA_OFFSET +
898
+					   PCIE_DMA_WR_INT_CLEAR, clears.asdword);
899
+			ret = -1;
900
+		}
901
+	} else {
902
+		status.asdword = dw_pcie_readl_dbi(pci, PCIE_DMA_OFFSET + PCIE_DMA_RD_INT_STATUS);
903
+
904
+		if (status.donesta & BIT(chn)) {
905
+			clears.doneclr = BIT(chn);
906
+			dw_pcie_writel_dbi(pci, PCIE_DMA_OFFSET +
907
+					   PCIE_DMA_RD_INT_CLEAR, clears.asdword);
908
+			ret = 1;
909
+		}
910
+
911
+		if (status.abortsta & BIT(chn)) {
912
+			dev_err(pci->dev, "%s, read abort %x\n", __func__, status.asdword);
913
+			clears.abortclr = BIT(chn);
914
+			dw_pcie_writel_dbi(pci, PCIE_DMA_OFFSET +
915
+					   PCIE_DMA_RD_INT_CLEAR, clears.asdword);
916
+			ret = -1;
917
+		}
918
+	}
919
+
920
+	return ret;
921
+}
922
+
815923 static const struct dw_pcie_ops dw_pcie_ops = {
816924 	.start_link = rockchip_pcie_start_link,
817925 	.link_up = rockchip_pcie_link_up,
....@@ -847,6 +955,7 @@
847955 	struct pcie_ep_dma_cache_cfg cfg;
848956 	void __user *uarg = (void __user *)arg;
849957 	int i, ret;
958
+	enum pcie_ep_mmap_resource mmap_res;
850959 
851960 	switch (cmd) {
852961 	case PCIE_DMA_GET_ELBI_DATA:
....@@ -885,6 +994,33 @@
885994 		dw_pcie_writel_dbi(&rockchip->pci, PCIE_DMA_OFFSET + PCIE_DMA_RD_INT_MASK,
886995 				   0xffffffff);
887996 		break;
997
+	case PCIE_DMA_RAISE_MSI_OBJ_IRQ_USER:
998
+		rockchip->obj_info->irq_type_rc = OBJ_IRQ_USER;
999
+		rockchip_pcie_raise_msi_irq(rockchip, PCIe_CLIENT_MSI_OBJ_IRQ);
1000
+		break;
1001
+	case PCIE_EP_GET_USER_INFO:
1002
+		msg.bar0_phys_addr = rockchip->ib_target_address[0];
1003
+
1004
+		ret = copy_to_user(uarg, &msg, sizeof(msg));
1005
+		if (ret) {
1006
+			dev_err(rockchip->pci.dev, "failed to get elbi data\n");
1007
+			return -EFAULT;
1008
+		}
1009
+		break;
1010
+	case PCIE_EP_SET_MMAP_RESOURCE:
1011
+		ret = copy_from_user(&mmap_res, uarg, sizeof(mmap_res));
1012
+		if (ret) {
1013
+			dev_err(rockchip->pci.dev, "failed to get copy from\n");
1014
+			return -EFAULT;
1015
+		}
1016
+
1017
+		if (mmap_res >= PCIE_EP_MMAP_RESOURCE_MAX) {
1018
+			dev_err(rockchip->pci.dev, "mmap index %d is out of number\n", mmap_res);
1019
+			return -EINVAL;
1020
+		}
1021
+
1022
+		rockchip->cur_mmap_res = mmap_res;
1023
+		break;
8881024 	default:
8891025 		break;
8901026 	}
....@@ -896,18 +1032,45 @@
8961032 	struct rockchip_pcie *rockchip = (struct rockchip_pcie *)file->private_data;
8971033 	size_t size = vma->vm_end - vma->vm_start;
8981034 	int err;
1035
+	unsigned long addr;
8991036 
900
-	if (size > PCIE_DBI_SIZE) {
901
-		dev_warn(rockchip->pci.dev, "mmap size is out of limitation\n");
1037
+	switch (rockchip->cur_mmap_res) {
1038
+	case PCIE_EP_MMAP_RESOURCE_DBI:
1039
+		if (size > PCIE_DBI_SIZE) {
1040
+			dev_warn(rockchip->pci.dev, "dbi mmap size is out of limitation\n");
1041
+			return -EINVAL;
1042
+		}
1043
+		addr = rockchip->dbi_base_physical;
1044
+		break;
1045
+	case PCIE_EP_MMAP_RESOURCE_BAR0:
1046
+		if (size > rockchip->ib_target_size[0]) {
1047
+			dev_warn(rockchip->pci.dev, "bar0 mmap size is out of limitation\n");
1048
+			return -EINVAL;
1049
+		}
1050
+		addr = rockchip->ib_target_address[0];
1051
+		break;
1052
+	case PCIE_EP_MMAP_RESOURCE_BAR2:
1053
+		if (size > rockchip->ib_target_size[2]) {
1054
+			dev_warn(rockchip->pci.dev, "bar2 mmap size is out of limitation\n");
1055
+			return -EINVAL;
1056
+		}
1057
+		addr = rockchip->ib_target_address[2];
1058
+		break;
1059
+	default:
1060
+		dev_err(rockchip->pci.dev, "cur mmap_res %d is unsurreport\n", rockchip->cur_mmap_res);
9021061 		return -EINVAL;
9031062 	}
9041063 
9051064 	vma->vm_flags |= VM_IO;
9061065 	vma->vm_flags |= (VM_DONTEXPAND | VM_DONTDUMP);
907
-	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1066
+
1067
+	if (rockchip->cur_mmap_res == PCIE_EP_MMAP_RESOURCE_BAR2)
1068
+		vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
1069
+	else
1070
+		vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
9081071 
9091072 	err = remap_pfn_range(vma, vma->vm_start,
910
-			      __phys_to_pfn(rockchip->dbi_base_physical),
1073
+			      __phys_to_pfn(addr),
9111074 			      size, vma->vm_page_prot);
9121075 	if (err)
9131076 		return -EAGAIN;
....@@ -941,13 +1104,13 @@
9411104 
9421105 	ret = misc_register(&pcie_dev->dev);
9431106 	if (ret) {
944
-		pr_err("pcie: failed to register misc device.\n");
1107
+		dev_err(rockchip->pci.dev, "pcie: failed to register misc device.\n");
9451108 		return ret;
9461109 	}
9471110 
9481111 	pcie_dev->pcie = rockchip;
9491112 
950
-	pr_info("register misc device pcie-dev\n");
1113
+	dev_info(rockchip->pci.dev, "register misc device pcie_ep\n");
9511114 
9521115 	return 0;
9531116 }
....@@ -957,7 +1120,7 @@
9571120 	struct device *dev = &pdev->dev;
9581121 	struct rockchip_pcie *rockchip;
9591122 	int ret;
960
-	int retry;
1123
+	int retry, i;
9611124 
9621125 	rockchip = devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL);
9631126 	if (!rockchip)
....@@ -993,8 +1156,10 @@
9931156 		goto disable_regulator;
9941157 
9951158 	if (dw_pcie_link_up(&rockchip->pci)) {
996
-		pr_info("%s, %d, already linkup\n", __func__, __LINE__);
1159
+		dev_info(dev, "already linkup\n");
9971160 		goto already_linkup;
1161
+	} else {
1162
+		dev_info(dev, "initial\n");
9981163 	}
9991164 
10001165 	ret = rockchip_pcie_phy_init(rockchip);
....@@ -1015,6 +1180,7 @@
10151180 	rockchip_pcie_fast_link_setup(rockchip);
10161181 
10171182 	rockchip_pcie_start_link(&rockchip->pci);
1183
+	rockchip_pcie_devmode_update(rockchip, RKEP_MODE_KERNEL, RKEP_SMODE_LNKRDY);
10181184 
10191185 	for (retry = 0; retry < 10000; retry++) {
10201186 		if (dw_pcie_link_up(&rockchip->pci)) {
....@@ -1042,8 +1208,11 @@
10421208 	}
10431209 
10441210 already_linkup:
1211
+	rockchip_pcie_devmode_update(rockchip, RKEP_MODE_KERNEL, RKEP_SMODE_LNKUP);
10451212 	rockchip->pci.iatu_unroll_enabled = rockchip_pcie_iatu_unroll_enabled(&rockchip->pci);
1046
-	rockchip_pcie_ep_set_bar(rockchip);
1213
+	for (i = 0; i < PCIE_BAR_MAX_NUM; i++)
1214
+		if (rockchip->ib_target_size[i])
1215
+			rockchip_pcie_ep_set_bar(rockchip, i, rockchip->ib_target_address[i]);
10471216 
10481217 	ret = rockchip_pcie_init_dma_trx(rockchip);
10491218 	if (ret) {
....@@ -1054,6 +1223,7 @@
10541223 	if (rockchip->dma_obj) {
10551224 		rockchip->dma_obj->start_dma_func = rockchip_pcie_start_dma_dwc;
10561225 		rockchip->dma_obj->config_dma_func = rockchip_pcie_config_dma_dwc;
1226
+		rockchip->dma_obj->get_dma_status = rockchip_pcie_get_dma_status;
10571227 	}
10581228 
10591229 	/* Enable client ELBI interrupt */
....@@ -1086,9 +1256,10 @@
10861256 		.of_match_table = rockchip_pcie_ep_of_match,
10871257 		.suppress_bind_attrs = true,
10881258 	},
1259
+	.probe = rockchip_pcie_ep_probe,
10891260 };
10901261 
1091
-module_platform_driver_probe(rk_plat_pcie_driver, rockchip_pcie_ep_probe);
1262
+module_platform_driver(rk_plat_pcie_driver);
10921263 
10931264 MODULE_AUTHOR("Simon Xue <xxm@rock-chips.com>");
10941265 MODULE_DESCRIPTION("RockChip PCIe Controller EP driver");