add dts config

hc

2023-12-06 08f87f769b595151be1afeff53e144f543faa614

 kernel/drivers/net/phy/rk630phy.c
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@@ -160,14 +160,33 @@
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 	phy_write(phydev, REG_PAGE_SEL, 0x0000);
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 }
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-static void rk630_phy_set_uaps(struct phy_device *phydev)
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+static void rk630_phy_set_aps(struct phy_device *phydev, bool enable)
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+{
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+	u32 value;
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+
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+	/* Switch to page 1 */
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+	phy_write(phydev, REG_PAGE_SEL, 0x0100);
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+	value = phy_read(phydev, REG_PAGE1_APS_CTRL);
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+	if (enable)
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+		value |= BIT(15);
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+	else
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+		value &= ~BIT(15);
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+	phy_write(phydev, REG_PAGE1_APS_CTRL, value);
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+	/* Switch to page 0 */
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+	phy_write(phydev, REG_PAGE_SEL, 0x0000);
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+}
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+
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+static void rk630_phy_set_uaps(struct phy_device *phydev, bool enable)
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 {
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 	u32 value;
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 	/* Switch to page 1 */
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 	phy_write(phydev, REG_PAGE_SEL, 0x0100);
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 	value = phy_read(phydev, REG_PAGE1_UAPS_CONFIGURE);
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-	value |= BIT(15);
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+	if (enable)
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+		value |= BIT(15);
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+	else
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+		value &= ~BIT(15);
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 	phy_write(phydev, REG_PAGE1_UAPS_CONFIGURE, value);
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 	/* Switch to page 0 */
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 	phy_write(phydev, REG_PAGE_SEL, 0x0000);
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@@ -208,6 +227,8 @@
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 	/* Switch to page 1 */
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 	phy_write(phydev, REG_PAGE_SEL, 0x0100);
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+	/* Enable offset clock */
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+	phy_write(phydev, 0x10, 0xfbfe);
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 	/* Disable APS */
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 	phy_write(phydev, REG_PAGE1_APS_CTRL, 0x4824);
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 	/* Switch to page 2 */
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@@ -217,7 +238,7 @@
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 	/* Switch to page 6 */
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 	phy_write(phydev, REG_PAGE_SEL, 0x0600);
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 	/* PHYAFE ADC optimization */
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-	phy_write(phydev, REG_PAGE6_ADC_ANONTROL, 0x5540);
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+	phy_write(phydev, REG_PAGE6_ADC_ANONTROL, 0x555e);
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 	/* PHYAFE Gain optimization */
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 	phy_write(phydev, REG_PAGE6_GAIN_ANONTROL, 0x0400);
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 	/* PHYAFE EQ optimization */
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@@ -244,6 +265,8 @@
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 	phy_write(phydev, REG_PAGE_SEL, 0x0800);
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 	/* Disable auto-cal */
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 	phy_write(phydev, REG_PAGE8_AUTO_CAL, 0x0844);
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+	/* Reatart offset calibration */
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+	phy_write(phydev, 0x13, 0xc096);
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270
 
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 	/* Switch to page 0 */
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 	phy_write(phydev, REG_PAGE_SEL, 0x0000);
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@@ -264,10 +287,12 @@
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 		 * Ultra Auto-Power Saving Mode (UAPS) is designed to
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 		 * save power when cable is not plugged into PHY.
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 		 */
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-		rk630_phy_set_uaps(phydev);
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+		rk630_phy_set_uaps(phydev, true);
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 		break;
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 	case PHY_ADDR_T22:
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 		rk630_phy_t22_config_init(phydev);
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+		rk630_phy_set_aps(phydev, true);
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+		rk630_phy_set_uaps(phydev, true);
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 		break;
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 	default:
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 		phydev_err(phydev, "Unsupported address for current phy: %d\n",
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@@ -278,6 +303,23 @@
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 	rk630_phy_ieee_set(phydev, true);
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 	return 0;
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+}
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+
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+static void rk630_link_change_notify(struct phy_device *phydev)
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+{
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+	unsigned int val;
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+
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+	if (phydev->state == PHY_RUNNING || phydev->state == PHY_NOLINK) {
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+		/* Switch to page 6 */
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+		phy_write(phydev, REG_PAGE_SEL, 0x0600);
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+		val = phy_read(phydev, REG_PAGE6_AFE_TX_CTRL);
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+		val &= ~GENMASK(14, 13);
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+		if (phydev->speed == SPEED_10 && phydev->link)
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+			val |= BIT(13);
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+		phy_write(phydev, REG_PAGE6_AFE_TX_CTRL, val);
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+		/* Switch to page 0 */
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+		phy_write(phydev, REG_PAGE_SEL, 0x0000);
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+	}
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 }
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 static irqreturn_t rk630_wol_irq_thread(int irq, void *dev_id)
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@@ -365,6 +407,7 @@
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 	.name			= "RK630 PHY",
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 	.features		= PHY_BASIC_FEATURES,
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 	.flags			= 0,
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+	.link_change_notify	= rk630_link_change_notify,
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 	.probe			= rk630_phy_probe,
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 	.remove			= rk630_phy_remove,
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 	.soft_reset		= genphy_soft_reset,
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@@ -381,7 +424,7 @@
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 	{ }
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 };
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-MODULE_DEVICE_TABLE(mdio, rockchip_phy_tbl);
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+MODULE_DEVICE_TABLE(mdio, rk630_phy_tbl);
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 module_phy_driver(rk630_phy_driver);
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