~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,7 +1,8 @@
1	1	/* Broadcom NetXtreme-C/E network driver.
2	2	*
3	3	* Copyright (c) 2014-2016 Broadcom Corporation
4		- * Copyright (c) 2016-2018 Broadcom Limited
	4	+ * Copyright (c) 2014-2018 Broadcom Limited
	5	+ * Copyright (c) 2018-2020 Broadcom Inc.
5	6	*
6	7	* This program is free software; you can redistribute it and/or modify
7	8	* it under the terms of the GNU General Public License as published by
..	..	@@ -37,15 +38,18 @@
37	38	#define TLV_TYPE_HWRM_REQUEST 0x1UL
38	39	#define TLV_TYPE_HWRM_RESPONSE 0x2UL
39	40	#define TLV_TYPE_ROCE_SP_COMMAND 0x3UL
40		-#define TLV_TYPE_ENGINE_CKV_DEVICE_SERIAL_NUMBER 0x8001UL
41		-#define TLV_TYPE_ENGINE_CKV_NONCE 0x8002UL
	41	+#define TLV_TYPE_QUERY_ROCE_CC_GEN1 0x4UL
	42	+#define TLV_TYPE_MODIFY_ROCE_CC_GEN1 0x5UL
	43	+#define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY 0x8001UL
42	44	#define TLV_TYPE_ENGINE_CKV_IV 0x8003UL
43	45	#define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL
44	46	#define TLV_TYPE_ENGINE_CKV_CIPHERTEXT 0x8005UL
45		-#define TLV_TYPE_ENGINE_CKV_ALGORITHMS 0x8006UL
46		-#define TLV_TYPE_ENGINE_CKV_ECC_PUBLIC_KEY 0x8007UL
	47	+#define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS 0x8006UL
	48	+#define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY 0x8007UL
47	49	#define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 0x8008UL
48		-#define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE
	50	+#define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY 0x8009UL
	51	+#define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 0x800aUL
	52	+#define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS
49	53
50	54
51	55	/* tlv (size:64b/8B) */
..	..	@@ -87,7 +91,10 @@
87	91	__le16 signature;
88	92	#define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL
89	93	#define SHORT_REQ_SIGNATURE_LAST SHORT_REQ_SIGNATURE_SHORT_CMD
90		- __le16 unused_0;
	94	+ __le16 target_id;
	95	+ #define SHORT_REQ_TARGET_ID_DEFAULT 0x0UL
	96	+ #define SHORT_REQ_TARGET_ID_TOOLS 0xfffdUL
	97	+ #define SHORT_REQ_TARGET_ID_LAST SHORT_REQ_TARGET_ID_TOOLS
91	98	__le16 size;
92	99	__le64 req_addr;
93	100	};
..	..	@@ -96,6 +103,7 @@
96	103	struct cmd_nums {
97	104	__le16 req_type;
98	105	#define HWRM_VER_GET 0x0UL
	106	+ #define HWRM_ERROR_RECOVERY_QCFG 0xcUL
99	107	#define HWRM_FUNC_DRV_IF_CHANGE 0xdUL
100	108	#define HWRM_FUNC_BUF_UNRGTR 0xeUL
101	109	#define HWRM_FUNC_VF_CFG 0xfUL
..	..	@@ -161,13 +169,21 @@
161	169	#define HWRM_RING_CMPL_RING_QAGGINT_PARAMS 0x52UL
162	170	#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS 0x53UL
163	171	#define HWRM_RING_AGGINT_QCAPS 0x54UL
	172	+ #define HWRM_RING_SCHQ_ALLOC 0x55UL
	173	+ #define HWRM_RING_SCHQ_CFG 0x56UL
	174	+ #define HWRM_RING_SCHQ_FREE 0x57UL
164	175	#define HWRM_RING_RESET 0x5eUL
165	176	#define HWRM_RING_GRP_ALLOC 0x60UL
166	177	#define HWRM_RING_GRP_FREE 0x61UL
	178	+ #define HWRM_RING_CFG 0x62UL
	179	+ #define HWRM_RING_QCFG 0x63UL
167	180	#define HWRM_RESERVED5 0x64UL
168	181	#define HWRM_RESERVED6 0x65UL
169	182	#define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC 0x70UL
170	183	#define HWRM_VNIC_RSS_COS_LB_CTX_FREE 0x71UL
	184	+ #define HWRM_QUEUE_MPLS_QCAPS 0x80UL
	185	+ #define HWRM_QUEUE_MPLSTC2PRI_QCFG 0x81UL
	186	+ #define HWRM_QUEUE_MPLSTC2PRI_CFG 0x82UL
171	187	#define HWRM_CFA_L2_FILTER_ALLOC 0x90UL
172	188	#define HWRM_CFA_L2_FILTER_FREE 0x91UL
173	189	#define HWRM_CFA_L2_FILTER_CFG 0x92UL
..	..	@@ -186,35 +202,62 @@
186	202	#define HWRM_TUNNEL_DST_PORT_QUERY 0xa0UL
187	203	#define HWRM_TUNNEL_DST_PORT_ALLOC 0xa1UL
188	204	#define HWRM_TUNNEL_DST_PORT_FREE 0xa2UL
	205	+ #define HWRM_STAT_CTX_ENG_QUERY 0xafUL
189	206	#define HWRM_STAT_CTX_ALLOC 0xb0UL
190	207	#define HWRM_STAT_CTX_FREE 0xb1UL
191	208	#define HWRM_STAT_CTX_QUERY 0xb2UL
192	209	#define HWRM_STAT_CTX_CLR_STATS 0xb3UL
193	210	#define HWRM_PORT_QSTATS_EXT 0xb4UL
	211	+ #define HWRM_PORT_PHY_MDIO_WRITE 0xb5UL
	212	+ #define HWRM_PORT_PHY_MDIO_READ 0xb6UL
	213	+ #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE 0xb7UL
	214	+ #define HWRM_PORT_PHY_MDIO_BUS_RELEASE 0xb8UL
	215	+ #define HWRM_PORT_QSTATS_EXT_PFC_WD 0xb9UL
	216	+ #define HWRM_RESERVED7 0xbaUL
	217	+ #define HWRM_PORT_TX_FIR_CFG 0xbbUL
	218	+ #define HWRM_PORT_TX_FIR_QCFG 0xbcUL
	219	+ #define HWRM_PORT_ECN_QSTATS 0xbdUL
194	220	#define HWRM_FW_RESET 0xc0UL
195	221	#define HWRM_FW_QSTATUS 0xc1UL
196	222	#define HWRM_FW_HEALTH_CHECK 0xc2UL
197	223	#define HWRM_FW_SYNC 0xc3UL
	224	+ #define HWRM_FW_STATE_QCAPS 0xc4UL
	225	+ #define HWRM_FW_STATE_QUIESCE 0xc5UL
	226	+ #define HWRM_FW_STATE_BACKUP 0xc6UL
	227	+ #define HWRM_FW_STATE_RESTORE 0xc7UL
198	228	#define HWRM_FW_SET_TIME 0xc8UL
199	229	#define HWRM_FW_GET_TIME 0xc9UL
200	230	#define HWRM_FW_SET_STRUCTURED_DATA 0xcaUL
201	231	#define HWRM_FW_GET_STRUCTURED_DATA 0xcbUL
202	232	#define HWRM_FW_IPC_MAILBOX 0xccUL
	233	+ #define HWRM_FW_ECN_CFG 0xcdUL
	234	+ #define HWRM_FW_ECN_QCFG 0xceUL
	235	+ #define HWRM_FW_SECURE_CFG 0xcfUL
203	236	#define HWRM_EXEC_FWD_RESP 0xd0UL
204	237	#define HWRM_REJECT_FWD_RESP 0xd1UL
205	238	#define HWRM_FWD_RESP 0xd2UL
206	239	#define HWRM_FWD_ASYNC_EVENT_CMPL 0xd3UL
207	240	#define HWRM_OEM_CMD 0xd4UL
	241	+ #define HWRM_PORT_PRBS_TEST 0xd5UL
	242	+ #define HWRM_PORT_SFP_SIDEBAND_CFG 0xd6UL
	243	+ #define HWRM_PORT_SFP_SIDEBAND_QCFG 0xd7UL
	244	+ #define HWRM_FW_STATE_UNQUIESCE 0xd8UL
	245	+ #define HWRM_PORT_DSC_DUMP 0xd9UL
208	246	#define HWRM_TEMP_MONITOR_QUERY 0xe0UL
	247	+ #define HWRM_REG_POWER_QUERY 0xe1UL
	248	+ #define HWRM_CORE_FREQUENCY_QUERY 0xe2UL
	249	+ #define HWRM_REG_POWER_HISTOGRAM 0xe3UL
209	250	#define HWRM_WOL_FILTER_ALLOC 0xf0UL
210	251	#define HWRM_WOL_FILTER_FREE 0xf1UL
211	252	#define HWRM_WOL_FILTER_QCFG 0xf2UL
212	253	#define HWRM_WOL_REASON_QCFG 0xf3UL
	254	+ #define HWRM_CFA_METER_QCAPS 0xf4UL
213	255	#define HWRM_CFA_METER_PROFILE_ALLOC 0xf5UL
214	256	#define HWRM_CFA_METER_PROFILE_FREE 0xf6UL
215	257	#define HWRM_CFA_METER_PROFILE_CFG 0xf7UL
216	258	#define HWRM_CFA_METER_INSTANCE_ALLOC 0xf8UL
217	259	#define HWRM_CFA_METER_INSTANCE_FREE 0xf9UL
	260	+ #define HWRM_CFA_METER_INSTANCE_CFG 0xfaUL
218	261	#define HWRM_CFA_VFR_ALLOC 0xfdUL
219	262	#define HWRM_CFA_VFR_FREE 0xfeUL
220	263	#define HWRM_CFA_VF_PAIR_ALLOC 0x100UL
..	..	@@ -235,7 +278,26 @@
235	278	#define HWRM_CFA_PAIR_INFO 0x10fUL
236	279	#define HWRM_FW_IPC_MSG 0x110UL
237	280	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO 0x111UL
238		- #define HWRM_ENGINE_CKV_HELLO 0x12dUL
	281	+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE 0x112UL
	282	+ #define HWRM_CFA_FLOW_AGING_TIMER_RESET 0x113UL
	283	+ #define HWRM_CFA_FLOW_AGING_CFG 0x114UL
	284	+ #define HWRM_CFA_FLOW_AGING_QCFG 0x115UL
	285	+ #define HWRM_CFA_FLOW_AGING_QCAPS 0x116UL
	286	+ #define HWRM_CFA_CTX_MEM_RGTR 0x117UL
	287	+ #define HWRM_CFA_CTX_MEM_UNRGTR 0x118UL
	288	+ #define HWRM_CFA_CTX_MEM_QCTX 0x119UL
	289	+ #define HWRM_CFA_CTX_MEM_QCAPS 0x11aUL
	290	+ #define HWRM_CFA_COUNTER_QCAPS 0x11bUL
	291	+ #define HWRM_CFA_COUNTER_CFG 0x11cUL
	292	+ #define HWRM_CFA_COUNTER_QCFG 0x11dUL
	293	+ #define HWRM_CFA_COUNTER_QSTATS 0x11eUL
	294	+ #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG 0x11fUL
	295	+ #define HWRM_CFA_EEM_QCAPS 0x120UL
	296	+ #define HWRM_CFA_EEM_CFG 0x121UL
	297	+ #define HWRM_CFA_EEM_QCFG 0x122UL
	298	+ #define HWRM_CFA_EEM_OP 0x123UL
	299	+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS 0x124UL
	300	+ #define HWRM_CFA_TFLIB 0x125UL
239	301	#define HWRM_ENGINE_CKV_STATUS 0x12eUL
240	302	#define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL
241	303	#define HWRM_ENGINE_CKV_CKEK_DELETE 0x130UL
..	..	@@ -244,6 +306,8 @@
244	306	#define HWRM_ENGINE_CKV_FLUSH 0x133UL
245	307	#define HWRM_ENGINE_CKV_RNG_GET 0x134UL
246	308	#define HWRM_ENGINE_CKV_KEY_GEN 0x135UL
	309	+ #define HWRM_ENGINE_CKV_KEY_LABEL_CFG 0x136UL
	310	+ #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG 0x137UL
247	311	#define HWRM_ENGINE_QG_CONFIG_QUERY 0x13cUL
248	312	#define HWRM_ENGINE_QG_QUERY 0x13dUL
249	313	#define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL
..	..	@@ -264,6 +328,7 @@
264	328	#define HWRM_ENGINE_STATS_CONFIG 0x155UL
265	329	#define HWRM_ENGINE_STATS_CLEAR 0x156UL
266	330	#define HWRM_ENGINE_STATS_QUERY 0x157UL
	331	+ #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR 0x158UL
267	332	#define HWRM_ENGINE_RQ_ALLOC 0x15eUL
268	333	#define HWRM_ENGINE_RQ_FREE 0x15fUL
269	334	#define HWRM_ENGINE_CQ_ALLOC 0x160UL
..	..	@@ -271,6 +336,7 @@
271	336	#define HWRM_ENGINE_NQ_ALLOC 0x162UL
272	337	#define HWRM_ENGINE_NQ_FREE 0x163UL
273	338	#define HWRM_ENGINE_ON_DIE_RQE_CREDITS 0x164UL
	339	+ #define HWRM_ENGINE_FUNC_QCFG 0x165UL
274	340	#define HWRM_FUNC_RESOURCE_QCAPS 0x190UL
275	341	#define HWRM_FUNC_VF_RESOURCE_CFG 0x191UL
276	342	#define HWRM_FUNC_BACKING_STORE_QCAPS 0x192UL
..	..	@@ -278,11 +344,55 @@
278	344	#define HWRM_FUNC_BACKING_STORE_QCFG 0x194UL
279	345	#define HWRM_FUNC_VF_BW_CFG 0x195UL
280	346	#define HWRM_FUNC_VF_BW_QCFG 0x196UL
	347	+ #define HWRM_FUNC_HOST_PF_IDS_QUERY 0x197UL
	348	+ #define HWRM_FUNC_QSTATS_EXT 0x198UL
	349	+ #define HWRM_STAT_EXT_CTX_QUERY 0x199UL
281	350	#define HWRM_SELFTEST_QLIST 0x200UL
282	351	#define HWRM_SELFTEST_EXEC 0x201UL
283	352	#define HWRM_SELFTEST_IRQ 0x202UL
284	353	#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA 0x203UL
285	354	#define HWRM_PCIE_QSTATS 0x204UL
	355	+ #define HWRM_MFG_FRU_WRITE_CONTROL 0x205UL
	356	+ #define HWRM_MFG_TIMERS_QUERY 0x206UL
	357	+ #define HWRM_MFG_OTP_CFG 0x207UL
	358	+ #define HWRM_MFG_OTP_QCFG 0x208UL
	359	+ #define HWRM_MFG_HDMA_TEST 0x209UL
	360	+ #define HWRM_MFG_FRU_EEPROM_WRITE 0x20aUL
	361	+ #define HWRM_MFG_FRU_EEPROM_READ 0x20bUL
	362	+ #define HWRM_TF 0x2bcUL
	363	+ #define HWRM_TF_VERSION_GET 0x2bdUL
	364	+ #define HWRM_TF_SESSION_OPEN 0x2c6UL
	365	+ #define HWRM_TF_SESSION_ATTACH 0x2c7UL
	366	+ #define HWRM_TF_SESSION_REGISTER 0x2c8UL
	367	+ #define HWRM_TF_SESSION_UNREGISTER 0x2c9UL
	368	+ #define HWRM_TF_SESSION_CLOSE 0x2caUL
	369	+ #define HWRM_TF_SESSION_QCFG 0x2cbUL
	370	+ #define HWRM_TF_SESSION_RESC_QCAPS 0x2ccUL
	371	+ #define HWRM_TF_SESSION_RESC_ALLOC 0x2cdUL
	372	+ #define HWRM_TF_SESSION_RESC_FREE 0x2ceUL
	373	+ #define HWRM_TF_SESSION_RESC_FLUSH 0x2cfUL
	374	+ #define HWRM_TF_TBL_TYPE_GET 0x2daUL
	375	+ #define HWRM_TF_TBL_TYPE_SET 0x2dbUL
	376	+ #define HWRM_TF_TBL_TYPE_BULK_GET 0x2dcUL
	377	+ #define HWRM_TF_CTXT_MEM_ALLOC 0x2e2UL
	378	+ #define HWRM_TF_CTXT_MEM_FREE 0x2e3UL
	379	+ #define HWRM_TF_CTXT_MEM_RGTR 0x2e4UL
	380	+ #define HWRM_TF_CTXT_MEM_UNRGTR 0x2e5UL
	381	+ #define HWRM_TF_EXT_EM_QCAPS 0x2e6UL
	382	+ #define HWRM_TF_EXT_EM_OP 0x2e7UL
	383	+ #define HWRM_TF_EXT_EM_CFG 0x2e8UL
	384	+ #define HWRM_TF_EXT_EM_QCFG 0x2e9UL
	385	+ #define HWRM_TF_EM_INSERT 0x2eaUL
	386	+ #define HWRM_TF_EM_DELETE 0x2ebUL
	387	+ #define HWRM_TF_TCAM_SET 0x2f8UL
	388	+ #define HWRM_TF_TCAM_GET 0x2f9UL
	389	+ #define HWRM_TF_TCAM_MOVE 0x2faUL
	390	+ #define HWRM_TF_TCAM_FREE 0x2fbUL
	391	+ #define HWRM_TF_GLOBAL_CFG_SET 0x2fcUL
	392	+ #define HWRM_TF_GLOBAL_CFG_GET 0x2fdUL
	393	+ #define HWRM_TF_IF_TBL_SET 0x2feUL
	394	+ #define HWRM_TF_IF_TBL_GET 0x2ffUL
	395	+ #define HWRM_SV 0x400UL
286	396	#define HWRM_DBG_READ_DIRECT 0xff10UL
287	397	#define HWRM_DBG_READ_INDIRECT 0xff11UL
288	398	#define HWRM_DBG_WRITE_DIRECT 0xff12UL
..	..	@@ -295,6 +405,14 @@
295	405	#define HWRM_DBG_COREDUMP_RETRIEVE 0xff19UL
296	406	#define HWRM_DBG_FW_CLI 0xff1aUL
297	407	#define HWRM_DBG_I2C_CMD 0xff1bUL
	408	+ #define HWRM_DBG_RING_INFO_GET 0xff1cUL
	409	+ #define HWRM_DBG_CRASHDUMP_HEADER 0xff1dUL
	410	+ #define HWRM_DBG_CRASHDUMP_ERASE 0xff1eUL
	411	+ #define HWRM_DBG_DRV_TRACE 0xff1fUL
	412	+ #define HWRM_DBG_QCAPS 0xff20UL
	413	+ #define HWRM_DBG_QCFG 0xff21UL
	414	+ #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG 0xff22UL
	415	+ #define HWRM_NVM_REQ_ARBITRATION 0xffedUL
298	416	#define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL
299	417	#define HWRM_NVM_VALIDATE_OPTION 0xffefUL
300	418	#define HWRM_NVM_FLUSH 0xfff0UL
..	..	@@ -320,20 +438,28 @@
320	438	/* ret_codes (size:64b/8B) */
321	439	struct ret_codes {
322	440	__le16 error_code;
323		- #define HWRM_ERR_CODE_SUCCESS 0x0UL
324		- #define HWRM_ERR_CODE_FAIL 0x1UL
325		- #define HWRM_ERR_CODE_INVALID_PARAMS 0x2UL
326		- #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED 0x3UL
327		- #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR 0x4UL
328		- #define HWRM_ERR_CODE_INVALID_FLAGS 0x5UL
329		- #define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL
330		- #define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL
331		- #define HWRM_ERR_CODE_NO_BUFFER 0x8UL
332		- #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR 0x9UL
333		- #define HWRM_ERR_CODE_HWRM_ERROR 0xfUL
334		- #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL
335		- #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL
336		- #define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED
	441	+ #define HWRM_ERR_CODE_SUCCESS 0x0UL
	442	+ #define HWRM_ERR_CODE_FAIL 0x1UL
	443	+ #define HWRM_ERR_CODE_INVALID_PARAMS 0x2UL
	444	+ #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED 0x3UL
	445	+ #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR 0x4UL
	446	+ #define HWRM_ERR_CODE_INVALID_FLAGS 0x5UL
	447	+ #define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL
	448	+ #define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL
	449	+ #define HWRM_ERR_CODE_NO_BUFFER 0x8UL
	450	+ #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR 0x9UL
	451	+ #define HWRM_ERR_CODE_HOT_RESET_PROGRESS 0xaUL
	452	+ #define HWRM_ERR_CODE_HOT_RESET_FAIL 0xbUL
	453	+ #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC 0xcUL
	454	+ #define HWRM_ERR_CODE_KEY_HASH_COLLISION 0xdUL
	455	+ #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS 0xeUL
	456	+ #define HWRM_ERR_CODE_HWRM_ERROR 0xfUL
	457	+ #define HWRM_ERR_CODE_BUSY 0x10UL
	458	+ #define HWRM_ERR_CODE_RESOURCE_LOCKED 0x11UL
	459	+ #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE 0x8000UL
	460	+ #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL
	461	+ #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL
	462	+ #define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED
337	463	__le16 unused_0[3];
338	464	};
339	465
..	..	@@ -350,15 +476,19 @@
350	476	};
351	477	#define HWRM_NA_SIGNATURE ((__le32)(-1))
352	478	#define HWRM_MAX_REQ_LEN 128
353		-#define HWRM_MAX_RESP_LEN 280
	479	+#define HWRM_MAX_RESP_LEN 704
354	480	#define HW_HASH_INDEX_SIZE 0x80
355	481	#define HW_HASH_KEY_SIZE 40
356	482	#define HWRM_RESP_VALID_KEY 1
	483	+#define HWRM_TARGET_ID_BONO 0xFFF8
	484	+#define HWRM_TARGET_ID_KONG 0xFFF9
	485	+#define HWRM_TARGET_ID_APE 0xFFFA
	486	+#define HWRM_TARGET_ID_TOOLS 0xFFFD
357	487	#define HWRM_VERSION_MAJOR 1
358		-#define HWRM_VERSION_MINOR 9
359		-#define HWRM_VERSION_UPDATE 2
360		-#define HWRM_VERSION_RSVD 25
361		-#define HWRM_VERSION_STR "1.9.2.25"
	488	+#define HWRM_VERSION_MINOR 10
	489	+#define HWRM_VERSION_UPDATE 1
	490	+#define HWRM_VERSION_RSVD 68
	491	+#define HWRM_VERSION_STR "1.10.1.68"
362	492
363	493	/* hwrm_ver_get_input (size:192b/24B) */
364	494	struct hwrm_ver_get_input {
..	..	@@ -396,10 +526,21 @@
396	526	u8 netctrl_fw_bld_8b;
397	527	u8 netctrl_fw_rsvd_8b;
398	528	__le32 dev_caps_cfg;
399		- #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL
400		- #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL
401		- #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL
402		- #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL
	529	+ #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL
	530	+ #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL
	531	+ #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL
	532	+ #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL
	533	+ #define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED 0x10UL
	534	+ #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED 0x20UL
	535	+ #define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED 0x40UL
	536	+ #define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED 0x80UL
	537	+ #define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED 0x100UL
	538	+ #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED 0x200UL
	539	+ #define VER_GET_RESP_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED 0x400UL
	540	+ #define VER_GET_RESP_DEV_CAPS_CFG_CFA_EEM_SUPPORTED 0x800UL
	541	+ #define VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED 0x1000UL
	542	+ #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED 0x2000UL
	543	+ #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED 0x4000UL
403	544	u8 roce_fw_maj_8b;
404	545	u8 roce_fw_min_8b;
405	546	u8 roce_fw_bld_8b;
..	..	@@ -407,7 +548,7 @@
407	548	char hwrm_fw_name[16];
408	549	char mgmt_fw_name[16];
409	550	char netctrl_fw_name[16];
410		- u8 reserved2[16];
	551	+ char active_pkg_name[16];
411	552	char roce_fw_name[16];
412	553	__le16 chip_num;
413	554	u8 chip_rev;
..	..	@@ -454,14 +595,27 @@
454	595	/* eject_cmpl (size:128b/16B) */
455	596	struct eject_cmpl {
456	597	__le16 type;
457		- #define EJECT_CMPL_TYPE_MASK 0x3fUL
458		- #define EJECT_CMPL_TYPE_SFT 0
459		- #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL
460		- #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
	598	+ #define EJECT_CMPL_TYPE_MASK 0x3fUL
	599	+ #define EJECT_CMPL_TYPE_SFT 0
	600	+ #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL
	601	+ #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
	602	+ #define EJECT_CMPL_FLAGS_MASK 0xffc0UL
	603	+ #define EJECT_CMPL_FLAGS_SFT 6
	604	+ #define EJECT_CMPL_FLAGS_ERROR 0x40UL
461	605	__le16 len;
462	606	__le32 opaque;
463		- __le32 v;
464		- #define EJECT_CMPL_V 0x1UL
	607	+ __le16 v;
	608	+ #define EJECT_CMPL_V 0x1UL
	609	+ #define EJECT_CMPL_ERRORS_MASK 0xfffeUL
	610	+ #define EJECT_CMPL_ERRORS_SFT 1
	611	+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK 0xeUL
	612	+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
	613	+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0UL << 1)
	614	+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1UL << 1)
	615	+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3UL << 1)
	616	+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH (0x5UL << 1)
	617	+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
	618	+ __le16 reserved16;
465	619	__le32 unused_2;
466	620	};
467	621
..	..	@@ -528,6 +682,9 @@
528	682	#define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL
529	683	#define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL
530	684	#define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL
	685	+ #define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY 0x8UL
	686	+ #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY 0x9UL
	687	+ #define ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG 0xaUL
531	688	#define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL
532	689	#define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL
533	690	#define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL
..	..	@@ -539,6 +696,19 @@
539	696	#define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL
540	697	#define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL
541	698	#define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE 0x35UL
	699	+ #define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED 0x36UL
	700	+ #define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION 0x37UL
	701	+ #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL
	702	+ #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL
	703	+ #define ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE 0x3aUL
	704	+ #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE 0x3bUL
	705	+ #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE 0x3cUL
	706	+ #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE 0x3dUL
	707	+ #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE 0x3eUL
	708	+ #define ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE 0x3fUL
	709	+ #define ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE 0x40UL
	710	+ #define ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE 0x41UL
	711	+ #define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG 0xfeUL
542	712	#define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL
543	713	#define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
544	714	__le32 event_data2;
..	..	@@ -634,6 +804,89 @@
634	804	#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL
635	805	};
636	806
	807	+/* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */
	808	+struct hwrm_async_event_cmpl_reset_notify {
	809	+ __le16 type;
	810	+ #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK 0x3fUL
	811	+ #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0
	812	+ #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 0x2eUL
	813	+ #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT
	814	+ __le16 event_id;
	815	+ #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL
	816	+ #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY
	817	+ __le32 event_data2;
	818	+ u8 opaque_v;
	819	+ #define ASYNC_EVENT_CMPL_RESET_NOTIFY_V 0x1UL
	820	+ #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL
	821	+ #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1
	822	+ u8 timestamp_lo;
	823	+ __le16 timestamp_hi;
	824	+ __le32 event_data1;
	825	+ #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK 0xffUL
	826	+ #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT 0
	827	+ #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE 0x1UL
	828	+ #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 0x2UL
	829	+ #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN
	830	+ #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK 0xff00UL
	831	+ #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT 8
	832	+ #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST (0x1UL << 8)
	833	+ #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL (0x2UL << 8)
	834	+ #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL (0x3UL << 8)
	835	+ #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL
	836	+ #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK 0xffff0000UL
	837	+ #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT 16
	838	+};
	839	+
	840	+/* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */
	841	+struct hwrm_async_event_cmpl_error_recovery {
	842	+ __le16 type;
	843	+ #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK 0x3fUL
	844	+ #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0
	845	+ #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 0x2eUL
	846	+ #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT
	847	+ __le16 event_id;
	848	+ #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 0x9UL
	849	+ #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY
	850	+ __le32 event_data2;
	851	+ u8 opaque_v;
	852	+ #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_V 0x1UL
	853	+ #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK 0xfeUL
	854	+ #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1
	855	+ u8 timestamp_lo;
	856	+ __le16 timestamp_hi;
	857	+ __le32 event_data1;
	858	+ #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK 0xffUL
	859	+ #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT 0
	860	+ #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC 0x1UL
	861	+ #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED 0x2UL
	862	+};
	863	+
	864	+/* hwrm_async_event_cmpl_ring_monitor_msg (size:128b/16B) */
	865	+struct hwrm_async_event_cmpl_ring_monitor_msg {
	866	+ __le16 type;
	867	+ #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_MASK 0x3fUL
	868	+ #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_SFT 0
	869	+ #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT 0x2eUL
	870	+ #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT
	871	+ __le16 event_id;
	872	+ #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 0xaUL
	873	+ #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG
	874	+ __le32 event_data2;
	875	+ #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK 0xffUL
	876	+ #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_SFT 0
	877	+ #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_TX 0x0UL
	878	+ #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX 0x1UL
	879	+ #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL 0x2UL
	880	+ #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL
	881	+ u8 opaque_v;
	882	+ #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_V 0x1UL
	883	+ #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_MASK 0xfeUL
	884	+ #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_SFT 1
	885	+ u8 timestamp_lo;
	886	+ __le16 timestamp_hi;
	887	+ __le32 event_data1;
	888	+};
	889	+
637	890	/* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */
638	891	struct hwrm_async_event_cmpl_vf_cfg_change {
639	892	__le16 type;
..	..	@@ -652,10 +905,132 @@
652	905	u8 timestamp_lo;
653	906	__le16 timestamp_hi;
654	907	__le32 event_data1;
655		- #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL
656		- #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL
657		- #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL
658		- #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL
	908	+ #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL
	909	+ #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL
	910	+ #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL
	911	+ #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL
	912	+ #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE 0x10UL
	913	+};
	914	+
	915	+/* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */
	916	+struct hwrm_async_event_cmpl_default_vnic_change {
	917	+ __le16 type;
	918	+ #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK 0x3fUL
	919	+ #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT 0
	920	+ #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
	921	+ #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT
	922	+ #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK 0xffc0UL
	923	+ #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT 6
	924	+ __le16 event_id;
	925	+ #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 0x35UL
	926	+ #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION
	927	+ __le32 event_data2;
	928	+ u8 opaque_v;
	929	+ #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V 0x1UL
	930	+ #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK 0xfeUL
	931	+ #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1
	932	+ u8 timestamp_lo;
	933	+ __le16 timestamp_hi;
	934	+ __le32 event_data1;
	935	+ #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK 0x3UL
	936	+ #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT 0
	937	+ #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC 0x1UL
	938	+ #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 0x2UL
	939	+ #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
	940	+ #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK 0x3fcUL
	941	+ #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT 2
	942	+ #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK 0x3fffc00UL
	943	+ #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT 10
	944	+};
	945	+
	946	+/* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */
	947	+struct hwrm_async_event_cmpl_hw_flow_aged {
	948	+ __le16 type;
	949	+ #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK 0x3fUL
	950	+ #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0
	951	+ #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 0x2eUL
	952	+ #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT
	953	+ __le16 event_id;
	954	+ #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 0x36UL
	955	+ #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED
	956	+ __le32 event_data2;
	957	+ u8 opaque_v;
	958	+ #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V 0x1UL
	959	+ #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK 0xfeUL
	960	+ #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1
	961	+ u8 timestamp_lo;
	962	+ __le16 timestamp_hi;
	963	+ __le32 event_data1;
	964	+ #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK 0x7fffffffUL
	965	+ #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT 0
	966	+ #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION 0x80000000UL
	967	+ #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX (0x0UL << 31)
	968	+ #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX (0x1UL << 31)
	969	+ #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
	970	+};
	971	+
	972	+/* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */
	973	+struct hwrm_async_event_cmpl_eem_cache_flush_req {
	974	+ __le16 type;
	975	+ #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK 0x3fUL
	976	+ #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT 0
	977	+ #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 0x2eUL
	978	+ #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT
	979	+ __le16 event_id;
	980	+ #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL
	981	+ #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ
	982	+ __le32 event_data2;
	983	+ u8 opaque_v;
	984	+ #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V 0x1UL
	985	+ #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK 0xfeUL
	986	+ #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1
	987	+ u8 timestamp_lo;
	988	+ __le16 timestamp_hi;
	989	+ __le32 event_data1;
	990	+};
	991	+
	992	+/* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */
	993	+struct hwrm_async_event_cmpl_eem_cache_flush_done {
	994	+ __le16 type;
	995	+ #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK 0x3fUL
	996	+ #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT 0
	997	+ #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
	998	+ #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT
	999	+ __le16 event_id;
	1000	+ #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL
	1001	+ #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE
	1002	+ __le32 event_data2;
	1003	+ u8 opaque_v;
	1004	+ #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V 0x1UL
	1005	+ #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK 0xfeUL
	1006	+ #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1
	1007	+ u8 timestamp_lo;
	1008	+ __le16 timestamp_hi;
	1009	+ __le32 event_data1;
	1010	+ #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK 0xffffUL
	1011	+ #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT 0
	1012	+};
	1013	+
	1014	+/* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */
	1015	+struct hwrm_async_event_cmpl_deferred_response {
	1016	+ __le16 type;
	1017	+ #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK 0x3fUL
	1018	+ #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT 0
	1019	+ #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
	1020	+ #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT
	1021	+ __le16 event_id;
	1022	+ #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 0x40UL
	1023	+ #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE
	1024	+ __le32 event_data2;
	1025	+ #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK 0xffffUL
	1026	+ #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT 0
	1027	+ u8 opaque_v;
	1028	+ #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V 0x1UL
	1029	+ #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK 0xfeUL
	1030	+ #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1
	1031	+ u8 timestamp_lo;
	1032	+ __le16 timestamp_hi;
	1033	+ __le32 event_data1;
659	1034	};
660	1035
661	1036	/* hwrm_func_reset_input (size:192b/24B) */
..	..	@@ -791,6 +1166,8 @@
791	1166	#define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x20UL
792	1167	#define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x40UL
793	1168	#define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x80UL
	1169	+ #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x100UL
	1170	+ #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x200UL
794	1171	__le16 num_rsscos_ctxs;
795	1172	__le16 num_cmpl_rings;
796	1173	__le16 num_tx_rings;
..	..	@@ -823,7 +1200,7 @@
823	1200	u8 unused_0[6];
824	1201	};
825	1202
826		-/* hwrm_func_qcaps_output (size:640b/80B) */
	1203	+/* hwrm_func_qcaps_output (size:704b/88B) */
827	1204	struct hwrm_func_qcaps_output {
828	1205	__le16 error_code;
829	1206	__le16 req_type;
..	..	@@ -832,26 +1209,38 @@
832	1209	__le16 fid;
833	1210	__le16 port_id;
834	1211	__le32 flags;
835		- #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL
836		- #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL
837		- #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL
838		- #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL
839		- #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL
840		- #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL
841		- #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL
842		- #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL
843		- #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL
844		- #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL
845		- #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL
846		- #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL
847		- #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL
848		- #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL
849		- #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL
850		- #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL
851		- #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED 0x10000UL
852		- #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED 0x20000UL
853		- #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL
854		- #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL
	1212	+ #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL
	1213	+ #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL
	1214	+ #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL
	1215	+ #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL
	1216	+ #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL
	1217	+ #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL
	1218	+ #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL
	1219	+ #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL
	1220	+ #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL
	1221	+ #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL
	1222	+ #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL
	1223	+ #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL
	1224	+ #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL
	1225	+ #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL
	1226	+ #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL
	1227	+ #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL
	1228	+ #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED 0x10000UL
	1229	+ #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED 0x20000UL
	1230	+ #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL
	1231	+ #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL
	1232	+ #define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE 0x100000UL
	1233	+ #define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC 0x200000UL
	1234	+ #define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE 0x400000UL
	1235	+ #define FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE 0x800000UL
	1236	+ #define FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED 0x1000000UL
	1237	+ #define FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD 0x2000000UL
	1238	+ #define FUNC_QCAPS_RESP_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED 0x4000000UL
	1239	+ #define FUNC_QCAPS_RESP_FLAGS_VLAN_ACCELERATION_TX_DISABLED 0x8000000UL
	1240	+ #define FUNC_QCAPS_RESP_FLAGS_COREDUMP_CMD_SUPPORTED 0x10000000UL
	1241	+ #define FUNC_QCAPS_RESP_FLAGS_CRASHDUMP_CMD_SUPPORTED 0x20000000UL
	1242	+ #define FUNC_QCAPS_RESP_FLAGS_PFC_WD_STATS_SUPPORTED 0x40000000UL
	1243	+ #define FUNC_QCAPS_RESP_FLAGS_DBG_QCAPS_CMD_SUPPORTED 0x80000000UL
855	1244	u8 mac_address[6];
856	1245	__le16 max_rsscos_ctx;
857	1246	__le16 max_cmpl_rings;
..	..	@@ -872,7 +1261,24 @@
872	1261	__le32 max_flow_id;
873	1262	__le32 max_hw_ring_grps;
874	1263	__le16 max_sp_tx_rings;
875		- u8 unused_0;
	1264	+ u8 unused_0[2];
	1265	+ __le32 flags_ext;
	1266	+ #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_MARK_SUPPORTED 0x1UL
	1267	+ #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_STATS_SUPPORTED 0x2UL
	1268	+ #define FUNC_QCAPS_RESP_FLAGS_EXT_EXT_HW_STATS_SUPPORTED 0x4UL
	1269	+ #define FUNC_QCAPS_RESP_FLAGS_EXT_HOT_RESET_IF_SUPPORT 0x8UL
	1270	+ #define FUNC_QCAPS_RESP_FLAGS_EXT_PROXY_MODE_SUPPORT 0x10UL
	1271	+ #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT 0x20UL
	1272	+ #define FUNC_QCAPS_RESP_FLAGS_EXT_SCHQ_SUPPORTED 0x40UL
	1273	+ #define FUNC_QCAPS_RESP_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED 0x80UL
	1274	+ u8 max_schqs;
	1275	+ u8 mpc_chnls_cap;
	1276	+ #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TCE 0x1UL
	1277	+ #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RCE 0x2UL
	1278	+ #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TE_CFA 0x4UL
	1279	+ #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RE_CFA 0x8UL
	1280	+ #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_PRIMATE 0x10UL
	1281	+ u8 unused_1;
876	1282	u8 valid;
877	1283	};
878	1284
..	..	@@ -887,7 +1293,7 @@
887	1293	u8 unused_0[6];
888	1294	};
889	1295
890		-/* hwrm_func_qcfg_output (size:640b/80B) */
	1296	+/* hwrm_func_qcfg_output (size:768b/96B) */
891	1297	struct hwrm_func_qcfg_output {
892	1298	__le16 error_code;
893	1299	__le16 req_type;
..	..	@@ -903,6 +1309,12 @@
903	1309	#define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL
904	1310	#define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL
905	1311	#define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL
	1312	+ #define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF 0x40UL
	1313	+ #define FUNC_QCFG_RESP_FLAGS_SECURE_MODE_ENABLED 0x80UL
	1314	+ #define FUNC_QCFG_RESP_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x100UL
	1315	+ #define FUNC_QCFG_RESP_FLAGS_HOT_RESET_ALLOWED 0x200UL
	1316	+ #define FUNC_QCFG_RESP_FLAGS_PPP_PUSH_MODE_ENABLED 0x400UL
	1317	+ #define FUNC_QCFG_RESP_FLAGS_RING_MONITOR_ENABLED 0x800UL
906	1318	u8 mac_address[6];
907	1319	__le16 pci_id;
908	1320	__le16 alloc_rsscos_ctx;
..	..	@@ -984,11 +1396,27 @@
984	1396	__le16 alloc_sp_tx_rings;
985	1397	__le16 alloc_stat_ctx;
986	1398	__le16 alloc_msix;
987		- u8 unused_2[5];
	1399	+ __le16 registered_vfs;
	1400	+ __le16 l2_doorbell_bar_size_kb;
	1401	+ u8 unused_1;
	1402	+ u8 always_1;
	1403	+ __le32 reset_addr_poll;
	1404	+ __le16 legacy_l2_db_size_kb;
	1405	+ __le16 svif_info;
	1406	+ #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_MASK 0x7fffUL
	1407	+ #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_SFT 0
	1408	+ #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_VALID 0x8000UL
	1409	+ u8 mpc_chnls;
	1410	+ #define FUNC_QCFG_RESP_MPC_CHNLS_TCE_ENABLED 0x1UL
	1411	+ #define FUNC_QCFG_RESP_MPC_CHNLS_RCE_ENABLED 0x2UL
	1412	+ #define FUNC_QCFG_RESP_MPC_CHNLS_TE_CFA_ENABLED 0x4UL
	1413	+ #define FUNC_QCFG_RESP_MPC_CHNLS_RE_CFA_ENABLED 0x8UL
	1414	+ #define FUNC_QCFG_RESP_MPC_CHNLS_PRIMATE_ENABLED 0x10UL
	1415	+ u8 unused_2[6];
988	1416	u8 valid;
989	1417	};
990	1418
991		-/* hwrm_func_cfg_input (size:704b/88B) */
	1419	+/* hwrm_func_cfg_input (size:768b/96B) */
992	1420	struct hwrm_func_cfg_input {
993	1421	__le16 req_type;
994	1422	__le16 cmpl_ring;
..	..	@@ -1014,30 +1442,41 @@
1014	1442	#define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x40000UL
1015	1443	#define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x80000UL
1016	1444	#define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x100000UL
	1445	+ #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE 0x200000UL
	1446	+ #define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC 0x400000UL
	1447	+ #define FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST 0x800000UL
	1448	+ #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_DISABLE 0x1000000UL
	1449	+ #define FUNC_CFG_REQ_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x2000000UL
	1450	+ #define FUNC_CFG_REQ_FLAGS_HOT_RESET_IF_EN_DIS 0x4000000UL
	1451	+ #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x8000000UL
	1452	+ #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x10000000UL
1017	1453	__le32 enables;
1018		- #define FUNC_CFG_REQ_ENABLES_MTU 0x1UL
1019		- #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL
1020		- #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL
1021		- #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL
1022		- #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL
1023		- #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL
1024		- #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL
1025		- #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL
1026		- #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL
1027		- #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL
1028		- #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL
1029		- #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL
1030		- #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL
1031		- #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL
1032		- #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL
1033		- #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL
1034		- #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL
1035		- #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL
1036		- #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL
1037		- #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL
1038		- #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE 0x100000UL
1039		- #define FUNC_CFG_REQ_ENABLES_NUM_MSIX 0x200000UL
1040		- #define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE 0x400000UL
	1454	+ #define FUNC_CFG_REQ_ENABLES_MTU 0x1UL
	1455	+ #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL
	1456	+ #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL
	1457	+ #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL
	1458	+ #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL
	1459	+ #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL
	1460	+ #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL
	1461	+ #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL
	1462	+ #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL
	1463	+ #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL
	1464	+ #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL
	1465	+ #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL
	1466	+ #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL
	1467	+ #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL
	1468	+ #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL
	1469	+ #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL
	1470	+ #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL
	1471	+ #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL
	1472	+ #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL
	1473	+ #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL
	1474	+ #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE 0x100000UL
	1475	+ #define FUNC_CFG_REQ_ENABLES_NUM_MSIX 0x200000UL
	1476	+ #define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE 0x400000UL
	1477	+ #define FUNC_CFG_REQ_ENABLES_HOT_RESET_IF_SUPPORT 0x800000UL
	1478	+ #define FUNC_CFG_REQ_ENABLES_SCHQ_ID 0x1000000UL
	1479	+ #define FUNC_CFG_REQ_ENABLES_MPC_CHNLS 0x2000000UL
1041	1480	__le16 mtu;
1042	1481	__le16 mru;
1043	1482	__le16 num_rsscos_ctxs;
..	..	@@ -1111,6 +1550,19 @@
1111	1550	#define FUNC_CFG_REQ_OPTIONS_RSVD_MASK 0xf0UL
1112	1551	#define FUNC_CFG_REQ_OPTIONS_RSVD_SFT 4
1113	1552	__le16 num_mcast_filters;
	1553	+ __le16 schq_id;
	1554	+ __le16 mpc_chnls;
	1555	+ #define FUNC_CFG_REQ_MPC_CHNLS_TCE_ENABLE 0x1UL
	1556	+ #define FUNC_CFG_REQ_MPC_CHNLS_TCE_DISABLE 0x2UL
	1557	+ #define FUNC_CFG_REQ_MPC_CHNLS_RCE_ENABLE 0x4UL
	1558	+ #define FUNC_CFG_REQ_MPC_CHNLS_RCE_DISABLE 0x8UL
	1559	+ #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_ENABLE 0x10UL
	1560	+ #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_DISABLE 0x20UL
	1561	+ #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_ENABLE 0x40UL
	1562	+ #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_DISABLE 0x80UL
	1563	+ #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_ENABLE 0x100UL
	1564	+ #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_DISABLE 0x200UL
	1565	+ u8 unused_0[4];
1114	1566	};
1115	1567
1116	1568	/* hwrm_func_cfg_output (size:128b/16B) */
..	..	@@ -1131,7 +1583,12 @@
1131	1583	__le16 target_id;
1132	1584	__le64 resp_addr;
1133	1585	__le16 fid;
1134		- u8 unused_0[6];
	1586	+ u8 flags;
	1587	+ #define FUNC_QSTATS_REQ_FLAGS_UNUSED 0x0UL
	1588	+ #define FUNC_QSTATS_REQ_FLAGS_ROCE_ONLY 0x1UL
	1589	+ #define FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x2UL
	1590	+ #define FUNC_QSTATS_REQ_FLAGS_LAST FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK
	1591	+ u8 unused_0[5];
1135	1592	};
1136	1593
1137	1594	/* hwrm_func_qstats_output (size:1408b/176B) */
..	..	@@ -1160,6 +1617,59 @@
1160	1617	__le64 rx_agg_bytes;
1161	1618	__le64 rx_agg_events;
1162	1619	__le64 rx_agg_aborts;
	1620	+ u8 unused_0[7];
	1621	+ u8 valid;
	1622	+};
	1623	+
	1624	+/* hwrm_func_qstats_ext_input (size:256b/32B) */
	1625	+struct hwrm_func_qstats_ext_input {
	1626	+ __le16 req_type;
	1627	+ __le16 cmpl_ring;
	1628	+ __le16 seq_id;
	1629	+ __le16 target_id;
	1630	+ __le64 resp_addr;
	1631	+ __le16 fid;
	1632	+ u8 flags;
	1633	+ #define FUNC_QSTATS_EXT_REQ_FLAGS_UNUSED 0x0UL
	1634	+ #define FUNC_QSTATS_EXT_REQ_FLAGS_ROCE_ONLY 0x1UL
	1635	+ #define FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x2UL
	1636	+ #define FUNC_QSTATS_EXT_REQ_FLAGS_LAST FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK
	1637	+ u8 unused_0[1];
	1638	+ __le32 enables;
	1639	+ #define FUNC_QSTATS_EXT_REQ_ENABLES_SCHQ_ID 0x1UL
	1640	+ __le16 schq_id;
	1641	+ __le16 traffic_class;
	1642	+ u8 unused_1[4];
	1643	+};
	1644	+
	1645	+/* hwrm_func_qstats_ext_output (size:1536b/192B) */
	1646	+struct hwrm_func_qstats_ext_output {
	1647	+ __le16 error_code;
	1648	+ __le16 req_type;
	1649	+ __le16 seq_id;
	1650	+ __le16 resp_len;
	1651	+ __le64 rx_ucast_pkts;
	1652	+ __le64 rx_mcast_pkts;
	1653	+ __le64 rx_bcast_pkts;
	1654	+ __le64 rx_discard_pkts;
	1655	+ __le64 rx_error_pkts;
	1656	+ __le64 rx_ucast_bytes;
	1657	+ __le64 rx_mcast_bytes;
	1658	+ __le64 rx_bcast_bytes;
	1659	+ __le64 tx_ucast_pkts;
	1660	+ __le64 tx_mcast_pkts;
	1661	+ __le64 tx_bcast_pkts;
	1662	+ __le64 tx_error_pkts;
	1663	+ __le64 tx_discard_pkts;
	1664	+ __le64 tx_ucast_bytes;
	1665	+ __le64 tx_mcast_bytes;
	1666	+ __le64 tx_bcast_bytes;
	1667	+ __le64 rx_tpa_eligible_pkt;
	1668	+ __le64 rx_tpa_eligible_bytes;
	1669	+ __le64 rx_tpa_pkt;
	1670	+ __le64 rx_tpa_bytes;
	1671	+ __le64 rx_tpa_errors;
	1672	+ __le64 rx_tpa_events;
1163	1673	u8 unused_0[7];
1164	1674	u8 valid;
1165	1675	};
..	..	@@ -1214,9 +1724,13 @@
1214	1724	__le16 target_id;
1215	1725	__le64 resp_addr;
1216	1726	__le32 flags;
1217		- #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL
1218		- #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL
1219		- #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL
	1727	+ #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL
	1728	+ #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL
	1729	+ #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL
	1730	+ #define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE 0x8UL
	1731	+ #define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT 0x10UL
	1732	+ #define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT 0x20UL
	1733	+ #define FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT 0x40UL
1220	1734	__le32 enables;
1221	1735	#define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL
1222	1736	#define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL
..	..	@@ -1416,7 +1930,9 @@
1416	1930	__le16 min_hw_ring_grps;
1417	1931	__le16 max_hw_ring_grps;
1418	1932	__le16 max_tx_scheduler_inputs;
1419		- u8 unused_0[7];
	1933	+ __le16 flags;
	1934	+ #define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED 0x1UL
	1935	+ u8 unused_0[5];
1420	1936	u8 valid;
1421	1937	};
1422	1938
..	..	@@ -1445,7 +1961,9 @@
1445	1961	__le16 max_stat_ctx;
1446	1962	__le16 min_hw_ring_grps;
1447	1963	__le16 max_hw_ring_grps;
1448		- u8 unused_0[4];
	1964	+ __le16 flags;
	1965	+ #define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED 0x1UL
	1966	+ u8 unused_0[2];
1449	1967	};
1450	1968
1451	1969	/* hwrm_func_vf_resource_cfg_output (size:256b/32B) */
..	..	@@ -1475,7 +1993,7 @@
1475	1993	__le64 resp_addr;
1476	1994	};
1477	1995
1478		-/* hwrm_func_backing_store_qcaps_output (size:576b/72B) */
	1996	+/* hwrm_func_backing_store_qcaps_output (size:640b/80B) */
1479	1997	struct hwrm_func_backing_store_qcaps_output {
1480	1998	__le16 error_code;
1481	1999	__le16 req_type;
..	..	@@ -1503,7 +2021,12 @@
1503	2021	__le16 mrav_entry_size;
1504	2022	__le16 tim_entry_size;
1505	2023	__le32 tim_max_entries;
1506		- u8 unused_0[3];
	2024	+ __le16 mrav_num_entries_units;
	2025	+ u8 tqm_entries_multiple;
	2026	+ u8 ctx_kind_initializer;
	2027	+ __le32 rsvd;
	2028	+ __le16 rsvd1;
	2029	+ u8 tqm_fp_rings_count;
1507	2030	u8 valid;
1508	2031	};
1509	2032
..	..	@@ -1515,7 +2038,8 @@
1515	2038	__le16 target_id;
1516	2039	__le64 resp_addr;
1517	2040	__le32 flags;
1518		- #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE 0x1UL
	2041	+ #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE 0x1UL
	2042	+ #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT 0x2UL
1519	2043	__le32 enables;
1520	2044	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP 0x1UL
1521	2045	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ 0x2UL
..	..	@@ -1846,6 +2370,99 @@
1846	2370	u8 valid;
1847	2371	};
1848	2372
	2373	+/* hwrm_error_recovery_qcfg_input (size:192b/24B) */
	2374	+struct hwrm_error_recovery_qcfg_input {
	2375	+ __le16 req_type;
	2376	+ __le16 cmpl_ring;
	2377	+ __le16 seq_id;
	2378	+ __le16 target_id;
	2379	+ __le64 resp_addr;
	2380	+ u8 unused_0[8];
	2381	+};
	2382	+
	2383	+/* hwrm_error_recovery_qcfg_output (size:1664b/208B) */
	2384	+struct hwrm_error_recovery_qcfg_output {
	2385	+ __le16 error_code;
	2386	+ __le16 req_type;
	2387	+ __le16 seq_id;
	2388	+ __le16 resp_len;
	2389	+ __le32 flags;
	2390	+ #define ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST 0x1UL
	2391	+ #define ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU 0x2UL
	2392	+ __le32 driver_polling_freq;
	2393	+ __le32 master_func_wait_period;
	2394	+ __le32 normal_func_wait_period;
	2395	+ __le32 master_func_wait_period_after_reset;
	2396	+ __le32 max_bailout_time_after_reset;
	2397	+ __le32 fw_health_status_reg;
	2398	+ #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK 0x3UL
	2399	+ #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT 0
	2400	+ #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG 0x0UL
	2401	+ #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC 0x1UL
	2402	+ #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 0x2UL
	2403	+ #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 0x3UL
	2404	+ #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1
	2405	+ #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_MASK 0xfffffffcUL
	2406	+ #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SFT 2
	2407	+ __le32 fw_heartbeat_reg;
	2408	+ #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_MASK 0x3UL
	2409	+ #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_SFT 0
	2410	+ #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG 0x0UL
	2411	+ #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_GRC 0x1UL
	2412	+ #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 0x2UL
	2413	+ #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 0x3UL
	2414	+ #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1
	2415	+ #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_MASK 0xfffffffcUL
	2416	+ #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SFT 2
	2417	+ __le32 fw_reset_cnt_reg;
	2418	+ #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_MASK 0x3UL
	2419	+ #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_SFT 0
	2420	+ #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL
	2421	+ #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_GRC 0x1UL
	2422	+ #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 0x2UL
	2423	+ #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 0x3UL
	2424	+ #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1
	2425	+ #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_MASK 0xfffffffcUL
	2426	+ #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SFT 2
	2427	+ __le32 reset_inprogress_reg;
	2428	+ #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_MASK 0x3UL
	2429	+ #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_SFT 0
	2430	+ #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG 0x0UL
	2431	+ #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_GRC 0x1UL
	2432	+ #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 0x2UL
	2433	+ #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 0x3UL
	2434	+ #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1
	2435	+ #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_MASK 0xfffffffcUL
	2436	+ #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SFT 2
	2437	+ __le32 reset_inprogress_reg_mask;
	2438	+ u8 unused_0[3];
	2439	+ u8 reg_array_cnt;
	2440	+ __le32 reset_reg[16];
	2441	+ #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_MASK 0x3UL
	2442	+ #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_SFT 0
	2443	+ #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_PCIE_CFG 0x0UL
	2444	+ #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_GRC 0x1UL
	2445	+ #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR0 0x2UL
	2446	+ #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 0x3UL
	2447	+ #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1
	2448	+ #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_MASK 0xfffffffcUL
	2449	+ #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SFT 2
	2450	+ __le32 reset_reg_val[16];
	2451	+ u8 delay_after_reset[16];
	2452	+ __le32 err_recovery_cnt_reg;
	2453	+ #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK 0x3UL
	2454	+ #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT 0
	2455	+ #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL
	2456	+ #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC 0x1UL
	2457	+ #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 0x2UL
	2458	+ #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 0x3UL
	2459	+ #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1
	2460	+ #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_MASK 0xfffffffcUL
	2461	+ #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SFT 2
	2462	+ u8 unused_1[3];
	2463	+ u8 valid;
	2464	+};
	2465	+
1849	2466	/* hwrm_func_drv_if_change_input (size:192b/24B) */
1850	2467	struct hwrm_func_drv_if_change_input {
1851	2468	__le16 req_type;
..	..	@@ -1865,7 +2482,8 @@
1865	2482	__le16 seq_id;
1866	2483	__le16 resp_len;
1867	2484	__le32 flags;
1868		- #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE 0x1UL
	2485	+ #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE 0x1UL
	2486	+ #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE 0x2UL
1869	2487	u8 unused_0[3];
1870	2488	u8 valid;
1871	2489	};
..	..	@@ -1878,33 +2496,43 @@
1878	2496	__le16 target_id;
1879	2497	__le64 resp_addr;
1880	2498	__le32 flags;
1881		- #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL
1882		- #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL
1883		- #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL
1884		- #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL
1885		- #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL
1886		- #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL
1887		- #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL
1888		- #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL
1889		- #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL
1890		- #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL
1891		- #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL
1892		- #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL
1893		- #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL
1894		- #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL
1895		- #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL
	2499	+ #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL
	2500	+ #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL
	2501	+ #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL
	2502	+ #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL
	2503	+ #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL
	2504	+ #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL
	2505	+ #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL
	2506	+ #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL
	2507	+ #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL
	2508	+ #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL
	2509	+ #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL
	2510	+ #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL
	2511	+ #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL
	2512	+ #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL
	2513	+ #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL
	2514	+ #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE 0x8000UL
	2515	+ #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE 0x10000UL
	2516	+ #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE 0x20000UL
	2517	+ #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE 0x40000UL
	2518	+ #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE 0x80000UL
	2519	+ #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE 0x100000UL
	2520	+ #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE 0x200000UL
	2521	+ #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE 0x400000UL
1896	2522	__le32 enables;
1897		- #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL
1898		- #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL
1899		- #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL
1900		- #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL
1901		- #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL
1902		- #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL
1903		- #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL
1904		- #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL
1905		- #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL
1906		- #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL
1907		- #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL
	2523	+ #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL
	2524	+ #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL
	2525	+ #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL
	2526	+ #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL
	2527	+ #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL
	2528	+ #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL
	2529	+ #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL
	2530	+ #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL
	2531	+ #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL
	2532	+ #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL
	2533	+ #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL
	2534	+ #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED 0x800UL
	2535	+ #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK 0x1000UL
1908	2536	__le16 port_id;
1909	2537	__le16 force_link_speed;
1910	2538	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL
..	..	@@ -1987,11 +2615,19 @@
1987	2615	#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL
1988	2616	#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL
1989	2617	#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL
1990		- u8 unused_2[2];
	2618	+ __le16 force_pam4_link_speed;
	2619	+ #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL
	2620	+ #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL
	2621	+ #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL
	2622	+ #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB
1991	2623	__le32 tx_lpi_timer;
1992	2624	#define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL
1993	2625	#define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0
1994		- __le32 unused_3;
	2626	+ __le16 auto_link_pam4_speed_mask;
	2627	+ #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_50G 0x1UL
	2628	+ #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_100G 0x2UL
	2629	+ #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_200G 0x4UL
	2630	+ u8 unused_2[2];
1995	2631	};
1996	2632
1997	2633	/* hwrm_port_phy_cfg_output (size:128b/16B) */
..	..	@@ -2036,7 +2672,22 @@
2036	2672	#define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL
2037	2673	#define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL
2038	2674	#define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_LINK
2039		- u8 unused_0;
	2675	+ u8 active_fec_signal_mode;
	2676	+ #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK 0xfUL
	2677	+ #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_SFT 0
	2678	+ #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ 0x0UL
	2679	+ #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 0x1UL
	2680	+ #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4
	2681	+ #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK 0xf0UL
	2682	+ #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_SFT 4
	2683	+ #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE (0x0UL << 4)
	2684	+ #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE (0x1UL << 4)
	2685	+ #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE (0x2UL << 4)
	2686	+ #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE (0x3UL << 4)
	2687	+ #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE (0x4UL << 4)
	2688	+ #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE (0x5UL << 4)
	2689	+ #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE (0x6UL << 4)
	2690	+ #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_LAST PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE
2040	2691	__le16 link_speed;
2041	2692	#define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL
2042	2693	#define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL
..	..	@@ -2048,6 +2699,7 @@
2048	2699	#define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL
2049	2700	#define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL
2050	2701	#define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL
	2702	+ #define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL
2051	2703	#define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL
2052	2704	#define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB
2053	2705	u8 duplex_cfg;
..	..	@@ -2143,6 +2795,7 @@
2143	2795	#define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL
2144	2796	#define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL
2145	2797	#define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL
	2798	+ #define PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT 0x5UL
2146	2799	#define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL
2147	2800	#define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE
2148	2801	__le32 preemphasis;
..	..	@@ -2178,7 +2831,11 @@
2178	2831	#define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL
2179	2832	#define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL
2180	2833	#define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL
2181		- #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX
	2834	+ #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4 0x1cUL
	2835	+ #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4 0x1dUL
	2836	+ #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4 0x1eUL
	2837	+ #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 0x1fUL
	2838	+ #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4
2182	2839	u8 media_type;
2183	2840	#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL
2184	2841	#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL
..	..	@@ -2252,13 +2909,21 @@
2252	2909	#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24)
2253	2910	#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28
2254	2911	__le16 fec_cfg;
2255		- #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL
2256		- #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL
2257		- #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL
2258		- #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL
2259		- #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL
2260		- #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL
2261		- #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL
	2912	+ #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL
	2913	+ #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL
	2914	+ #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL
	2915	+ #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL
	2916	+ #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL
	2917	+ #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL
	2918	+ #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL
	2919	+ #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_SUPPORTED 0x80UL
	2920	+ #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED 0x100UL
	2921	+ #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_SUPPORTED 0x200UL
	2922	+ #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED 0x400UL
	2923	+ #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED 0x800UL
	2924	+ #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED 0x1000UL
	2925	+ #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED 0x2000UL
	2926	+ #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED 0x4000UL
2262	2927	u8 duplex_state;
2263	2928	#define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL
2264	2929	#define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL
..	..	@@ -2267,11 +2932,27 @@
2267	2932	#define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT 0x1UL
2268	2933	char phy_vendor_name[16];
2269	2934	char phy_vendor_partnumber[16];
2270		- u8 unused_2[7];
	2935	+ __le16 support_pam4_speeds;
	2936	+ #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G 0x1UL
	2937	+ #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G 0x2UL
	2938	+ #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G 0x4UL
	2939	+ __le16 force_pam4_link_speed;
	2940	+ #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL
	2941	+ #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL
	2942	+ #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL
	2943	+ #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB
	2944	+ __le16 auto_pam4_link_speed_mask;
	2945	+ #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_50G 0x1UL
	2946	+ #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_100G 0x2UL
	2947	+ #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_200G 0x4UL
	2948	+ u8 link_partner_pam4_adv_speeds;
	2949	+ #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB 0x1UL
	2950	+ #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB 0x2UL
	2951	+ #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB 0x4UL
2271	2952	u8 valid;
2272	2953	};
2273	2954
2274		-/* hwrm_port_mac_cfg_input (size:320b/40B) */
	2955	+/* hwrm_port_mac_cfg_input (size:384b/48B) */
2275	2956	struct hwrm_port_mac_cfg_input {
2276	2957	__le16 req_type;
2277	2958	__le16 cmpl_ring;
..	..	@@ -2292,6 +2973,7 @@
2292	2973	#define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL
2293	2974	#define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL
2294	2975	#define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL
	2976	+ #define PORT_MAC_CFG_REQ_FLAGS_PTP_ONE_STEP_TX_TS 0x2000UL
2295	2977	__le32 enables;
2296	2978	#define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL
2297	2979	#define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL
..	..	@@ -2301,6 +2983,7 @@
2301	2983	#define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL
2302	2984	#define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL
2303	2985	#define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL
	2986	+ #define PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB 0x200UL
2304	2987	__le16 port_id;
2305	2988	u8 ipg;
2306	2989	u8 lpbk;
..	..	@@ -2333,6 +3016,8 @@
2333	3016	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL
2334	3017	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5
2335	3018	u8 unused_0[3];
	3019	+ __s32 ptp_freq_adj_ppb;
	3020	+ u8 unused_1[4];
2336	3021	};
2337	3022
2338	3023	/* hwrm_port_mac_cfg_output (size:128b/16B) */
..	..	@@ -2371,8 +3056,9 @@
2371	3056	__le16 seq_id;
2372	3057	__le16 resp_len;
2373	3058	u8 flags;
2374		- #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL
2375		- #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x2UL
	3059	+ #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL
	3060	+ #define PORT_MAC_PTP_QCFG_RESP_FLAGS_ONE_STEP_TX_TS 0x4UL
	3061	+ #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x8UL
2376	3062	u8 unused_0[3];
2377	3063	__le32 rx_ts_reg_off_lower;
2378	3064	__le32 rx_ts_reg_off_upper;
..	..	@@ -2526,7 +3212,11 @@
2526	3212	__le16 target_id;
2527	3213	__le64 resp_addr;
2528	3214	__le16 port_id;
2529		- u8 unused_0[6];
	3215	+ u8 flags;
	3216	+ #define PORT_QSTATS_REQ_FLAGS_UNUSED 0x0UL
	3217	+ #define PORT_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL
	3218	+ #define PORT_QSTATS_REQ_FLAGS_LAST PORT_QSTATS_REQ_FLAGS_COUNTER_MASK
	3219	+ u8 unused_0[5];
2530	3220	__le64 tx_stat_host_addr;
2531	3221	__le64 rx_stat_host_addr;
2532	3222	};
..	..	@@ -2579,7 +3269,7 @@
2579	3269	__le64 pfc_pri7_tx_transitions;
2580	3270	};
2581	3271
2582		-/* rx_port_stats_ext (size:2368b/296B) */
	3272	+/* rx_port_stats_ext (size:3648b/456B) */
2583	3273	struct rx_port_stats_ext {
2584	3274	__le64 link_down_events;
2585	3275	__le64 continuous_pause_events;
..	..	@@ -2618,6 +3308,26 @@
2618	3308	__le64 pfc_pri6_rx_transitions;
2619	3309	__le64 pfc_pri7_rx_duration_us;
2620	3310	__le64 pfc_pri7_rx_transitions;
	3311	+ __le64 rx_bits;
	3312	+ __le64 rx_buffer_passed_threshold;
	3313	+ __le64 rx_pcs_symbol_err;
	3314	+ __le64 rx_corrected_bits;
	3315	+ __le64 rx_discard_bytes_cos0;
	3316	+ __le64 rx_discard_bytes_cos1;
	3317	+ __le64 rx_discard_bytes_cos2;
	3318	+ __le64 rx_discard_bytes_cos3;
	3319	+ __le64 rx_discard_bytes_cos4;
	3320	+ __le64 rx_discard_bytes_cos5;
	3321	+ __le64 rx_discard_bytes_cos6;
	3322	+ __le64 rx_discard_bytes_cos7;
	3323	+ __le64 rx_discard_packets_cos0;
	3324	+ __le64 rx_discard_packets_cos1;
	3325	+ __le64 rx_discard_packets_cos2;
	3326	+ __le64 rx_discard_packets_cos3;
	3327	+ __le64 rx_discard_packets_cos4;
	3328	+ __le64 rx_discard_packets_cos5;
	3329	+ __le64 rx_discard_packets_cos6;
	3330	+ __le64 rx_discard_packets_cos7;
2621	3331	};
2622	3332
2623	3333	/* hwrm_port_qstats_ext_input (size:320b/40B) */
..	..	@@ -2630,7 +3340,11 @@
2630	3340	__le16 port_id;
2631	3341	__le16 tx_stat_size;
2632	3342	__le16 rx_stat_size;
2633		- u8 unused_0[2];
	3343	+ u8 flags;
	3344	+ #define PORT_QSTATS_EXT_REQ_FLAGS_UNUSED 0x0UL
	3345	+ #define PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x1UL
	3346	+ #define PORT_QSTATS_EXT_REQ_FLAGS_LAST PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK
	3347	+ u8 unused_0;
2634	3348	__le64 tx_stat_host_addr;
2635	3349	__le64 rx_stat_host_addr;
2636	3350	};
..	..	@@ -2644,7 +3358,8 @@
2644	3358	__le16 tx_stat_size;
2645	3359	__le16 rx_stat_size;
2646	3360	__le16 total_active_cos_queues;
2647		- u8 unused_0;
	3361	+ u8 flags;
	3362	+ #define PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED 0x1UL
2648	3363	u8 valid;
2649	3364	};
2650	3365
..	..	@@ -2677,6 +3392,47 @@
2677	3392	u8 valid;
2678	3393	};
2679	3394
	3395	+/* hwrm_port_ecn_qstats_input (size:256b/32B) */
	3396	+struct hwrm_port_ecn_qstats_input {
	3397	+ __le16 req_type;
	3398	+ __le16 cmpl_ring;
	3399	+ __le16 seq_id;
	3400	+ __le16 target_id;
	3401	+ __le64 resp_addr;
	3402	+ __le16 port_id;
	3403	+ __le16 ecn_stat_buf_size;
	3404	+ u8 flags;
	3405	+ #define PORT_ECN_QSTATS_REQ_FLAGS_UNUSED 0x0UL
	3406	+ #define PORT_ECN_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL
	3407	+ #define PORT_ECN_QSTATS_REQ_FLAGS_LAST PORT_ECN_QSTATS_REQ_FLAGS_COUNTER_MASK
	3408	+ u8 unused_0[3];
	3409	+ __le64 ecn_stat_host_addr;
	3410	+};
	3411	+
	3412	+/* hwrm_port_ecn_qstats_output (size:128b/16B) */
	3413	+struct hwrm_port_ecn_qstats_output {
	3414	+ __le16 error_code;
	3415	+ __le16 req_type;
	3416	+ __le16 seq_id;
	3417	+ __le16 resp_len;
	3418	+ __le16 ecn_stat_buf_size;
	3419	+ u8 mark_en;
	3420	+ u8 unused_0[4];
	3421	+ u8 valid;
	3422	+};
	3423	+
	3424	+/* port_stats_ecn (size:512b/64B) */
	3425	+struct port_stats_ecn {
	3426	+ __le64 mark_cnt_cos0;
	3427	+ __le64 mark_cnt_cos1;
	3428	+ __le64 mark_cnt_cos2;
	3429	+ __le64 mark_cnt_cos3;
	3430	+ __le64 mark_cnt_cos4;
	3431	+ __le64 mark_cnt_cos5;
	3432	+ __le64 mark_cnt_cos6;
	3433	+ __le64 mark_cnt_cos7;
	3434	+};
	3435	+
2680	3436	/* hwrm_port_clr_stats_input (size:192b/24B) */
2681	3437	struct hwrm_port_clr_stats_input {
2682	3438	__le16 req_type;
..	..	@@ -2685,7 +3441,9 @@
2685	3441	__le16 target_id;
2686	3442	__le64 resp_addr;
2687	3443	__le16 port_id;
2688		- u8 unused_0[6];
	3444	+ u8 flags;
	3445	+ #define PORT_CLR_STATS_REQ_FLAGS_ROCE_COUNTERS 0x1UL
	3446	+ u8 unused_0[5];
2689	3447	};
2690	3448
2691	3449	/* hwrm_port_clr_stats_output (size:128b/16B) */
..	..	@@ -2717,6 +3475,35 @@
2717	3475	u8 valid;
2718	3476	};
2719	3477
	3478	+/* hwrm_port_ts_query_input (size:192b/24B) */
	3479	+struct hwrm_port_ts_query_input {
	3480	+ __le16 req_type;
	3481	+ __le16 cmpl_ring;
	3482	+ __le16 seq_id;
	3483	+ __le16 target_id;
	3484	+ __le64 resp_addr;
	3485	+ __le32 flags;
	3486	+ #define PORT_TS_QUERY_REQ_FLAGS_PATH 0x1UL
	3487	+ #define PORT_TS_QUERY_REQ_FLAGS_PATH_TX 0x0UL
	3488	+ #define PORT_TS_QUERY_REQ_FLAGS_PATH_RX 0x1UL
	3489	+ #define PORT_TS_QUERY_REQ_FLAGS_PATH_LAST PORT_TS_QUERY_REQ_FLAGS_PATH_RX
	3490	+ #define PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME 0x2UL
	3491	+ __le16 port_id;
	3492	+ u8 unused_0[2];
	3493	+};
	3494	+
	3495	+/* hwrm_port_ts_query_output (size:192b/24B) */
	3496	+struct hwrm_port_ts_query_output {
	3497	+ __le16 error_code;
	3498	+ __le16 req_type;
	3499	+ __le16 seq_id;
	3500	+ __le16 resp_len;
	3501	+ __le64 ptp_msg_ts;
	3502	+ __le16 ptp_msg_seqid;
	3503	+ u8 unused_0[5];
	3504	+ u8 valid;
	3505	+};
	3506	+
2720	3507	/* hwrm_port_phy_qcaps_input (size:192b/24B) */
2721	3508	struct hwrm_port_phy_qcaps_input {
2722	3509	__le16 req_type;
..	..	@@ -2728,17 +3515,21 @@
2728	3515	u8 unused_0[6];
2729	3516	};
2730	3517
2731		-/* hwrm_port_phy_qcaps_output (size:192b/24B) */
	3518	+/* hwrm_port_phy_qcaps_output (size:256b/32B) */
2732	3519	struct hwrm_port_phy_qcaps_output {
2733	3520	__le16 error_code;
2734	3521	__le16 req_type;
2735	3522	__le16 seq_id;
2736	3523	__le16 resp_len;
2737	3524	u8 flags;
2738		- #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL
2739		- #define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED 0x2UL
2740		- #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_MASK 0xfcUL
2741		- #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_SFT 2
	3525	+ #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL
	3526	+ #define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED 0x2UL
	3527	+ #define PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED 0x4UL
	3528	+ #define PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED 0x8UL
	3529	+ #define PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET 0x10UL
	3530	+ #define PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED 0x20UL
	3531	+ #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_MASK 0xc0UL
	3532	+ #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_SFT 6
2742	3533	u8 port_cnt;
2743	3534	#define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL
2744	3535	#define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL
..	..	@@ -2792,8 +3583,18 @@
2792	3583	__le32 valid_tx_lpi_timer_high;
2793	3584	#define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL
2794	3585	#define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0
2795		- #define PORT_PHY_QCAPS_RESP_VALID_MASK 0xff000000UL
2796		- #define PORT_PHY_QCAPS_RESP_VALID_SFT 24
	3586	+ #define PORT_PHY_QCAPS_RESP_RSVD_MASK 0xff000000UL
	3587	+ #define PORT_PHY_QCAPS_RESP_RSVD_SFT 24
	3588	+ __le16 supported_pam4_speeds_auto_mode;
	3589	+ #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G 0x1UL
	3590	+ #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G 0x2UL
	3591	+ #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G 0x4UL
	3592	+ __le16 supported_pam4_speeds_force_mode;
	3593	+ #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G 0x1UL
	3594	+ #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G 0x2UL
	3595	+ #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G 0x4UL
	3596	+ u8 unused_0[3];
	3597	+ u8 valid;
2797	3598	};
2798	3599
2799	3600	/* hwrm_port_phy_i2c_read_input (size:320b/40B) */
..	..	@@ -2823,6 +3624,60 @@
2823	3624	__le16 resp_len;
2824	3625	__le32 data[16];
2825	3626	u8 unused_0[7];
	3627	+ u8 valid;
	3628	+};
	3629	+
	3630	+/* hwrm_port_phy_mdio_write_input (size:320b/40B) */
	3631	+struct hwrm_port_phy_mdio_write_input {
	3632	+ __le16 req_type;
	3633	+ __le16 cmpl_ring;
	3634	+ __le16 seq_id;
	3635	+ __le16 target_id;
	3636	+ __le64 resp_addr;
	3637	+ __le32 unused_0[2];
	3638	+ __le16 port_id;
	3639	+ u8 phy_addr;
	3640	+ u8 dev_addr;
	3641	+ __le16 reg_addr;
	3642	+ __le16 reg_data;
	3643	+ u8 cl45_mdio;
	3644	+ u8 unused_1[7];
	3645	+};
	3646	+
	3647	+/* hwrm_port_phy_mdio_write_output (size:128b/16B) */
	3648	+struct hwrm_port_phy_mdio_write_output {
	3649	+ __le16 error_code;
	3650	+ __le16 req_type;
	3651	+ __le16 seq_id;
	3652	+ __le16 resp_len;
	3653	+ u8 unused_0[7];
	3654	+ u8 valid;
	3655	+};
	3656	+
	3657	+/* hwrm_port_phy_mdio_read_input (size:256b/32B) */
	3658	+struct hwrm_port_phy_mdio_read_input {
	3659	+ __le16 req_type;
	3660	+ __le16 cmpl_ring;
	3661	+ __le16 seq_id;
	3662	+ __le16 target_id;
	3663	+ __le64 resp_addr;
	3664	+ __le32 unused_0[2];
	3665	+ __le16 port_id;
	3666	+ u8 phy_addr;
	3667	+ u8 dev_addr;
	3668	+ __le16 reg_addr;
	3669	+ u8 cl45_mdio;
	3670	+ u8 unused_1;
	3671	+};
	3672	+
	3673	+/* hwrm_port_phy_mdio_read_output (size:128b/16B) */
	3674	+struct hwrm_port_phy_mdio_read_output {
	3675	+ __le16 error_code;
	3676	+ __le16 req_type;
	3677	+ __le16 seq_id;
	3678	+ __le16 resp_len;
	3679	+ __le16 reg_data;
	3680	+ u8 unused_0[5];
2826	3681	u8 valid;
2827	3682	};
2828	3683
..	..	@@ -3178,7 +4033,7 @@
3178	4033	u8 unused_0;
3179	4034	};
3180	4035
3181		-/* hwrm_queue_qportcfg_output (size:256b/32B) */
	4036	+/* hwrm_queue_qportcfg_output (size:1344b/168B) */
3182	4037	struct hwrm_queue_qportcfg_output {
3183	4038	__le16 error_code;
3184	4039	__le16 req_type;
..	..	@@ -3264,6 +4119,49 @@
3264	4119	#define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
3265	4120	#define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL
3266	4121	#define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN
	4122	+ u8 unused_0;
	4123	+ char qid0_name[16];
	4124	+ char qid1_name[16];
	4125	+ char qid2_name[16];
	4126	+ char qid3_name[16];
	4127	+ char qid4_name[16];
	4128	+ char qid5_name[16];
	4129	+ char qid6_name[16];
	4130	+ char qid7_name[16];
	4131	+ u8 unused_1[7];
	4132	+ u8 valid;
	4133	+};
	4134	+
	4135	+/* hwrm_queue_qcfg_input (size:192b/24B) */
	4136	+struct hwrm_queue_qcfg_input {
	4137	+ __le16 req_type;
	4138	+ __le16 cmpl_ring;
	4139	+ __le16 seq_id;
	4140	+ __le16 target_id;
	4141	+ __le64 resp_addr;
	4142	+ __le32 flags;
	4143	+ #define QUEUE_QCFG_REQ_FLAGS_PATH 0x1UL
	4144	+ #define QUEUE_QCFG_REQ_FLAGS_PATH_TX 0x0UL
	4145	+ #define QUEUE_QCFG_REQ_FLAGS_PATH_RX 0x1UL
	4146	+ #define QUEUE_QCFG_REQ_FLAGS_PATH_LAST QUEUE_QCFG_REQ_FLAGS_PATH_RX
	4147	+ __le32 queue_id;
	4148	+};
	4149	+
	4150	+/* hwrm_queue_qcfg_output (size:128b/16B) */
	4151	+struct hwrm_queue_qcfg_output {
	4152	+ __le16 error_code;
	4153	+ __le16 req_type;
	4154	+ __le16 seq_id;
	4155	+ __le16 resp_len;
	4156	+ __le32 queue_len;
	4157	+ u8 service_profile;
	4158	+ #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSY 0x0UL
	4159	+ #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSLESS 0x1UL
	4160	+ #define QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 0xffUL
	4161	+ #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LAST QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN
	4162	+ u8 queue_cfg_info;
	4163	+ #define QUEUE_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL
	4164	+ u8 unused_0;
3267	4165	u8 valid;
3268	4166	};
3269	4167
..	..	@@ -3322,14 +4220,22 @@
3322	4220	__le16 seq_id;
3323	4221	__le16 resp_len;
3324	4222	__le32 flags;
3325		- #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL
3326		- #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL
3327		- #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL
3328		- #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL
3329		- #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL
3330		- #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL
3331		- #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL
3332		- #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL
	4223	+ #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL
	4224	+ #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL
	4225	+ #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL
	4226	+ #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL
	4227	+ #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL
	4228	+ #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL
	4229	+ #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL
	4230	+ #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL
	4231	+ #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL
	4232	+ #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL
	4233	+ #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL
	4234	+ #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL
	4235	+ #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL
	4236	+ #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL
	4237	+ #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL
	4238	+ #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL
3333	4239	u8 unused_0[3];
3334	4240	u8 valid;
3335	4241	};
..	..	@@ -3342,14 +4248,22 @@
3342	4248	__le16 target_id;
3343	4249	__le64 resp_addr;
3344	4250	__le32 flags;
3345		- #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL
3346		- #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL
3347		- #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL
3348		- #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL
3349		- #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL
3350		- #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL
3351		- #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL
3352		- #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL
	4251	+ #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL
	4252	+ #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL
	4253	+ #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL
	4254	+ #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL
	4255	+ #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL
	4256	+ #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL
	4257	+ #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL
	4258	+ #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL
	4259	+ #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL
	4260	+ #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL
	4261	+ #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL
	4262	+ #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL
	4263	+ #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL
	4264	+ #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL
	4265	+ #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL
	4266	+ #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL
3353	4267	__le16 port_id;
3354	4268	u8 unused_0[2];
3355	4269	};
..	..	@@ -4264,7 +5178,7 @@
4264	5178	u8 valid;
4265	5179	};
4266	5180
4267		-/* hwrm_vnic_cfg_input (size:320b/40B) */
	5181	+/* hwrm_vnic_cfg_input (size:384b/48B) */
4268	5182	struct hwrm_vnic_cfg_input {
4269	5183	__le16 req_type;
4270	5184	__le16 cmpl_ring;
..	..	@@ -4287,6 +5201,8 @@
4287	5201	#define VNIC_CFG_REQ_ENABLES_MRU 0x10UL
4288	5202	#define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID 0x20UL
4289	5203	#define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID 0x40UL
	5204	+ #define VNIC_CFG_REQ_ENABLES_QUEUE_ID 0x80UL
	5205	+ #define VNIC_CFG_REQ_ENABLES_RX_CSUM_V2_MODE 0x100UL
4290	5206	__le16 vnic_id;
4291	5207	__le16 dflt_ring_grp;
4292	5208	__le16 rss_rule;
..	..	@@ -4295,6 +5211,13 @@
4295	5211	__le16 mru;
4296	5212	__le16 default_rx_ring_id;
4297	5213	__le16 default_cmpl_ring_id;
	5214	+ __le16 queue_id;
	5215	+ u8 rx_csum_v2_mode;
	5216	+ #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_DEFAULT 0x0UL
	5217	+ #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_ALL_OK 0x1UL
	5218	+ #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 0x2UL
	5219	+ #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_LAST VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX
	5220	+ u8 unused0[5];
4298	5221	};
4299	5222
4300	5223	/* hwrm_vnic_cfg_output (size:128b/16B) */
..	..	@@ -4335,7 +5258,10 @@
4335	5258	#define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL
4336	5259	#define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP 0x40UL
4337	5260	#define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP 0x80UL
4338		- u8 unused_1[7];
	5261	+ #define VNIC_QCAPS_RESP_FLAGS_COS_ASSIGNMENT_CAP 0x100UL
	5262	+ #define VNIC_QCAPS_RESP_FLAGS_RX_CMPL_V2_CAP 0x200UL
	5263	+ __le16 max_aggs_supported;
	5264	+ u8 unused_1[5];
4339	5265	u8 valid;
4340	5266	};
4341	5267
..	..	@@ -4355,6 +5281,7 @@
4355	5281	#define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL
4356	5282	#define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL
4357	5283	#define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL
	5284	+ #define VNIC_TPA_CFG_REQ_FLAGS_AGG_PACK_AS_GRO 0x100UL
4358	5285	__le32 enables;
4359	5286	#define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL
4360	5287	#define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL
..	..	@@ -4476,6 +5403,15 @@
4476	5403	u8 valid;
4477	5404	};
4478	5405
	5406	+/* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */
	5407	+struct hwrm_vnic_rss_cfg_cmd_err {
	5408	+ u8 code;
	5409	+ #define VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL
	5410	+ #define VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 0x1UL
	5411	+ #define VNIC_RSS_CFG_CMD_ERR_CODE_LAST VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY
	5412	+ u8 unused_0[7];
	5413	+};
	5414	+
4479	5415	/* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */
4480	5416	struct hwrm_vnic_plcmodes_cfg_input {
4481	5417	__le16 req_type;
..	..	@@ -4490,15 +5426,18 @@
4490	5426	#define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL
4491	5427	#define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL
4492	5428	#define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL
	5429	+ #define VNIC_PLCMODES_CFG_REQ_FLAGS_VIRTIO_PLACEMENT 0x40UL
4493	5430	__le32 enables;
4494	5431	#define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL
4495	5432	#define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL
4496	5433	#define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL
	5434	+ #define VNIC_PLCMODES_CFG_REQ_ENABLES_MAX_BDS_VALID 0x8UL
4497	5435	__le32 vnic_id;
4498	5436	__le16 jumbo_thresh;
4499	5437	__le16 hds_offset;
4500	5438	__le16 hds_threshold;
4501		- u8 unused_0[6];
	5439	+ __le16 max_bds;
	5440	+ u8 unused_0[4];
4502	5441	};
4503	5442
4504	5443	/* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */
..	..	@@ -4566,6 +5505,8 @@
4566	5505	#define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID 0x40UL
4567	5506	#define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID 0x80UL
4568	5507	#define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL
	5508	+ #define RING_ALLOC_REQ_ENABLES_SCHQ_ID 0x200UL
	5509	+ #define RING_ALLOC_REQ_ENABLES_MPC_CHNLS_TYPE 0x400UL
4569	5510	u8 ring_type;
4570	5511	#define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL
4571	5512	#define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL
..	..	@@ -4574,12 +5515,14 @@
4574	5515	#define RING_ALLOC_REQ_RING_TYPE_RX_AGG 0x4UL
4575	5516	#define RING_ALLOC_REQ_RING_TYPE_NQ 0x5UL
4576	5517	#define RING_ALLOC_REQ_RING_TYPE_LAST RING_ALLOC_REQ_RING_TYPE_NQ
4577		- u8 unused_0[3];
	5518	+ u8 unused_0;
	5519	+ __le16 flags;
	5520	+ #define RING_ALLOC_REQ_FLAGS_RX_SOP_PAD 0x1UL
4578	5521	__le64 page_tbl_addr;
4579	5522	__le32 fbo;
4580	5523	u8 page_size;
4581	5524	u8 page_tbl_depth;
4582		- u8 unused_1[2];
	5525	+ __le16 schq_id;
4583	5526	__le32 length;
4584	5527	__le16 logical_id;
4585	5528	__le16 cmpl_ring_id;
..	..	@@ -4623,7 +5566,14 @@
4623	5566	#define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL
4624	5567	#define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL
4625	5568	#define RING_ALLOC_REQ_INT_MODE_LAST RING_ALLOC_REQ_INT_MODE_POLL
4626		- u8 unused_4[3];
	5569	+ u8 mpc_chnls_type;
	5570	+ #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TCE 0x0UL
	5571	+ #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RCE 0x1UL
	5572	+ #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TE_CFA 0x2UL
	5573	+ #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RE_CFA 0x3UL
	5574	+ #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 0x4UL
	5575	+ #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_LAST RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE
	5576	+ u8 unused_4[2];
4627	5577	__le64 cq_handle;
4628	5578	};
4629	5579
..	..	@@ -4666,6 +5616,36 @@
4666	5616	__le16 seq_id;
4667	5617	__le16 resp_len;
4668	5618	u8 unused_0[7];
	5619	+ u8 valid;
	5620	+};
	5621	+
	5622	+/* hwrm_ring_reset_input (size:192b/24B) */
	5623	+struct hwrm_ring_reset_input {
	5624	+ __le16 req_type;
	5625	+ __le16 cmpl_ring;
	5626	+ __le16 seq_id;
	5627	+ __le16 target_id;
	5628	+ __le64 resp_addr;
	5629	+ u8 ring_type;
	5630	+ #define RING_RESET_REQ_RING_TYPE_L2_CMPL 0x0UL
	5631	+ #define RING_RESET_REQ_RING_TYPE_TX 0x1UL
	5632	+ #define RING_RESET_REQ_RING_TYPE_RX 0x2UL
	5633	+ #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL
	5634	+ #define RING_RESET_REQ_RING_TYPE_RX_RING_GRP 0x6UL
	5635	+ #define RING_RESET_REQ_RING_TYPE_LAST RING_RESET_REQ_RING_TYPE_RX_RING_GRP
	5636	+ u8 unused_0;
	5637	+ __le16 ring_id;
	5638	+ u8 unused_1[4];
	5639	+};
	5640	+
	5641	+/* hwrm_ring_reset_output (size:128b/16B) */
	5642	+struct hwrm_ring_reset_output {
	5643	+ __le16 error_code;
	5644	+ __le16 req_type;
	5645	+ __le16 seq_id;
	5646	+ __le16 resp_len;
	5647	+ u8 unused_0[4];
	5648	+ u8 consumer_idx[3];
4669	5649	u8 valid;
4670	5650	};
4671	5651
..	..	@@ -4723,7 +5703,11 @@
4723	5703	__le16 target_id;
4724	5704	__le64 resp_addr;
4725	5705	__le16 ring_id;
4726		- u8 unused_0[6];
	5706	+ __le16 flags;
	5707	+ #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_MASK 0x3UL
	5708	+ #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_SFT 0
	5709	+ #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL
	5710	+ u8 unused_0[4];
4727	5711	};
4728	5712
4729	5713	/* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */
..	..	@@ -4830,6 +5814,11 @@
4830	5814	u8 valid;
4831	5815	};
4832	5816
	5817	+#define DEFAULT_FLOW_ID 0xFFFFFFFFUL
	5818	+#define ROCEV1_FLOW_ID 0xFFFFFFFEUL
	5819	+#define ROCEV2_FLOW_ID 0xFFFFFFFDUL
	5820	+#define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL
	5821	+
4833	5822	/* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */
4834	5823	struct hwrm_cfa_l2_filter_alloc_input {
4835	5824	__le16 req_type;
..	..	@@ -4838,13 +5827,21 @@
4838	5827	__le16 target_id;
4839	5828	__le64 resp_addr;
4840	5829	__le32 flags;
4841		- #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL
4842		- #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX 0x0UL
4843		- #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL
4844		- #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX
4845		- #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL
4846		- #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL
4847		- #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL
	5830	+ #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL
	5831	+ #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX 0x0UL
	5832	+ #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL
	5833	+ #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX
	5834	+ #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL
	5835	+ #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL
	5836	+ #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL
	5837	+ #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_MASK 0x30UL
	5838	+ #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_SFT 4
	5839	+ #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 4)
	5840	+ #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 4)
	5841	+ #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 4)
	5842	+ #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE
	5843	+ #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_XDP_DISABLE 0x40UL
	5844	+ #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_SOURCE_VALID 0x80UL
4848	5845	__le32 enables;
4849	5846	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL
4850	5847	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL
..	..	@@ -4863,8 +5860,11 @@
4863	5860	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL
4864	5861	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL
4865	5862	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL
	5863	+ #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_NUM_VLANS 0x20000UL
	5864	+ #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_NUM_VLANS 0x40000UL
4866	5865	u8 l2_addr[6];
4867		- u8 unused_0[2];
	5866	+ u8 num_vlans;
	5867	+ u8 t_num_vlans;
4868	5868	u8 l2_addr_mask[6];
4869	5869	__le16 l2_ovlan;
4870	5870	__le16 l2_ovlan_mask;
..	..	@@ -4891,18 +5891,21 @@
4891	5891	u8 unused_3;
4892	5892	__le32 src_id;
4893	5893	u8 tunnel_type;
4894		- #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
4895		- #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
4896		- #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
4897		- #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
4898		- #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
4899		- #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
4900		- #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
4901		- #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
4902		- #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
4903		- #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
4904		- #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
4905		- #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
	5894	+ #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
	5895	+ #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
	5896	+ #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
	5897	+ #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
	5898	+ #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
	5899	+ #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
	5900	+ #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
	5901	+ #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
	5902	+ #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
	5903	+ #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
	5904	+ #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
	5905	+ #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
	5906	+ #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
	5907	+ #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
	5908	+ #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
4906	5909	u8 unused_4;
4907	5910	__le16 dst_id;
4908	5911	__le16 mirror_vnic_id;
..	..	@@ -4926,6 +5929,16 @@
4926	5929	__le16 resp_len;
4927	5930	__le64 l2_filter_id;
4928	5931	__le32 flow_id;
	5932	+ #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL
	5933	+ #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0
	5934	+ #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL
	5935	+ #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30)
	5936	+ #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30)
	5937	+ #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT
	5938	+ #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL
	5939	+ #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31)
	5940	+ #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31)
	5941	+ #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX
4929	5942	u8 unused_0[3];
4930	5943	u8 valid;
4931	5944	};
..	..	@@ -4958,11 +5971,17 @@
4958	5971	__le16 target_id;
4959	5972	__le64 resp_addr;
4960	5973	__le32 flags;
4961		- #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL
4962		- #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL
4963		- #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL
4964		- #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX
4965		- #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL
	5974	+ #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL
	5975	+ #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL
	5976	+ #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL
	5977	+ #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX
	5978	+ #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL
	5979	+ #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_MASK 0xcUL
	5980	+ #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_SFT 2
	5981	+ #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 2)
	5982	+ #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 2)
	5983	+ #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 2)
	5984	+ #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE
4966	5985	__le32 enables;
4967	5986	#define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL
4968	5987	#define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL
..	..	@@ -5054,18 +6073,21 @@
5054	6073	u8 l3_addr_type;
5055	6074	u8 t_l3_addr_type;
5056	6075	u8 tunnel_type;
5057		- #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
5058		- #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
5059		- #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
5060		- #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
5061		- #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
5062		- #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
5063		- #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
5064		- #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
5065		- #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
5066		- #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
5067		- #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
5068		- #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
	6076	+ #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
	6077	+ #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
	6078	+ #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
	6079	+ #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
	6080	+ #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
	6081	+ #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
	6082	+ #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
	6083	+ #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
	6084	+ #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
	6085	+ #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
	6086	+ #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
	6087	+ #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
	6088	+ #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
	6089	+ #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
	6090	+ #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
5069	6091	u8 tunnel_flags;
5070	6092	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR 0x1UL
5071	6093	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 0x2UL
..	..	@@ -5083,6 +6105,16 @@
5083	6105	__le16 resp_len;
5084	6106	__le64 tunnel_filter_id;
5085	6107	__le32 flow_id;
	6108	+ #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL
	6109	+ #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0
	6110	+ #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL
	6111	+ #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30)
	6112	+ #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30)
	6113	+ #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT
	6114	+ #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL
	6115	+ #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31)
	6116	+ #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31)
	6117	+ #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX
5086	6118	u8 unused_0[3];
5087	6119	u8 valid;
5088	6120	};
..	..	@@ -5140,7 +6172,7 @@
5140	6172	__be32 dest_ip_addr[4];
5141	6173	};
5142	6174
5143		-/* hwrm_cfa_encap_data_vxlan (size:576b/72B) */
	6175	+/* hwrm_cfa_encap_data_vxlan (size:640b/80B) */
5144	6176	struct hwrm_cfa_encap_data_vxlan {
5145	6177	u8 src_mac_addr[6];
5146	6178	__le16 unused_0;
..	..	@@ -5159,6 +6191,10 @@
5159	6191	__be16 src_port;
5160	6192	__be16 dst_port;
5161	6193	__be32 vni;
	6194	+ u8 hdr_rsvd0[3];
	6195	+ u8 hdr_rsvd1;
	6196	+ u8 hdr_flags;
	6197	+ u8 unused[3];
5162	6198	};
5163	6199
5164	6200	/* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */
..	..	@@ -5170,16 +6206,21 @@
5170	6206	__le64 resp_addr;
5171	6207	__le32 flags;
5172	6208	#define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
	6209	+ #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_EXTERNAL 0x2UL
5173	6210	u8 encap_type;
5174		- #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL
5175		- #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL
5176		- #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL
5177		- #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL
5178		- #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL
5179		- #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL
5180		- #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL
5181		- #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL
5182		- #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE
	6211	+ #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL
	6212	+ #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL
	6213	+ #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL
	6214	+ #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL
	6215	+ #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL
	6216	+ #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL
	6217	+ #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL
	6218	+ #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL
	6219	+ #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_V4 0x9UL
	6220	+ #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE_V1 0xaUL
	6221	+ #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE 0xbUL
	6222	+ #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 0xcUL
	6223	+ #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6
5183	6224	u8 unused_0[3];
5184	6225	__le32 encap_data[20];
5185	6226	};
..	..	@@ -5224,9 +6265,12 @@
5224	6265	__le16 target_id;
5225	6266	__le64 resp_addr;
5226	6267	__le32 flags;
5227		- #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
5228		- #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL
5229		- #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL
	6268	+ #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
	6269	+ #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL
	6270	+ #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL
	6271	+ #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_FID 0x8UL
	6272	+ #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_ARP_REPLY 0x10UL
	6273	+ #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX 0x20UL
5230	6274	__le32 enables;
5231	6275	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL
5232	6276	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL
..	..	@@ -5247,6 +6291,7 @@
5247	6291	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL
5248	6292	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL
5249	6293	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL
	6294	+ #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_RFS_RING_TBL_IDX 0x80000UL
5250	6295	__le64 l2_filter_id;
5251	6296	u8 src_macaddr[6];
5252	6297	__be16 ethertype;
..	..	@@ -5263,18 +6308,21 @@
5263	6308	__le16 dst_id;
5264	6309	__le16 mirror_vnic_id;
5265	6310	u8 tunnel_type;
5266		- #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
5267		- #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
5268		- #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
5269		- #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
5270		- #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
5271		- #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
5272		- #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
5273		- #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
5274		- #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
5275		- #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
5276		- #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
5277		- #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
	6311	+ #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
	6312	+ #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
	6313	+ #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
	6314	+ #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
	6315	+ #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
	6316	+ #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
	6317	+ #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
	6318	+ #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
	6319	+ #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
	6320	+ #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
	6321	+ #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
	6322	+ #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
	6323	+ #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
	6324	+ #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
	6325	+ #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
5278	6326	u8 pri_hint;
5279	6327	#define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL
5280	6328	#define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL
..	..	@@ -5301,6 +6349,16 @@
5301	6349	__le16 resp_len;
5302	6350	__le64 ntuple_filter_id;
5303	6351	__le32 flow_id;
	6352	+ #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL
	6353	+ #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0
	6354	+ #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL
	6355	+ #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30)
	6356	+ #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30)
	6357	+ #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT
	6358	+ #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL
	6359	+ #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31)
	6360	+ #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31)
	6361	+ #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX
5304	6362	u8 unused_0[3];
5305	6363	u8 valid;
5306	6364	};
..	..	@@ -5345,7 +6403,9 @@
5345	6403	#define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL
5346	6404	#define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL
5347	6405	#define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL
5348		- u8 unused_0[4];
	6406	+ __le32 flags;
	6407	+ #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_FID 0x1UL
	6408	+ #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_RFS_RING_IDX 0x2UL
5349	6409	__le64 ntuple_filter_id;
5350	6410	__le32 new_dst_id;
5351	6411	__le32 new_mirror_vnic_id;
..	..	@@ -5394,18 +6454,21 @@
5394	6454	#define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL
5395	6455	__be32 tunnel_id;
5396	6456	u8 tunnel_type;
5397		- #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
5398		- #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
5399		- #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
5400		- #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
5401		- #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
5402		- #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
5403		- #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
5404		- #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
5405		- #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
5406		- #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
5407		- #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
5408		- #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
	6457	+ #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
	6458	+ #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
	6459	+ #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
	6460	+ #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
	6461	+ #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
	6462	+ #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
	6463	+ #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
	6464	+ #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
	6465	+ #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
	6466	+ #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
	6467	+ #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
	6468	+ #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
	6469	+ #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
	6470	+ #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
	6471	+ #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
5409	6472	u8 unused_0;
5410	6473	__le16 unused_1;
5411	6474	u8 src_macaddr[6];
..	..	@@ -5476,32 +6539,40 @@
5476	6539	__le16 target_id;
5477	6540	__le64 resp_addr;
5478	6541	__le16 flags;
5479		- #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL
5480		- #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL
5481		- #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1
5482		- #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1)
5483		- #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1)
5484		- #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1)
5485		- #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO
5486		- #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL
5487		- #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3
5488		- #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3)
5489		- #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3)
5490		- #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3)
5491		- #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6
	6542	+ #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL
	6543	+ #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL
	6544	+ #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1
	6545	+ #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1)
	6546	+ #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1)
	6547	+ #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1)
	6548	+ #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO
	6549	+ #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL
	6550	+ #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3
	6551	+ #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3)
	6552	+ #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3)
	6553	+ #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3)
	6554	+ #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6
	6555	+ #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_TX 0x40UL
	6556	+ #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_RX 0x80UL
	6557	+ #define CFA_FLOW_ALLOC_REQ_FLAGS_MATCH_VXLAN_IP_VNI 0x100UL
	6558	+ #define CFA_FLOW_ALLOC_REQ_FLAGS_VHOST_ID_USE_VLAN 0x200UL
5492	6559	__le16 src_fid;
5493	6560	__le32 tunnel_handle;
5494	6561	__le16 action_flags;
5495		- #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL
5496		- #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL
5497		- #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL
5498		- #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL
5499		- #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL
5500		- #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL
5501		- #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL
5502		- #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL
5503		- #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL
5504		- #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL
	6562	+ #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL
	6563	+ #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL
	6564	+ #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL
	6565	+ #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL
	6566	+ #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL
	6567	+ #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL
	6568	+ #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL
	6569	+ #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL
	6570	+ #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL
	6571	+ #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL
	6572	+ #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL_IP 0x400UL
	6573	+ #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FLOW_AGING_ENABLED 0x800UL
	6574	+ #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_PRI_HINT 0x1000UL
	6575	+ #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC 0x2000UL
5505	6576	__le16 dst_fid;
5506	6577	__be16 l2_rewrite_vlan_tpid;
5507	6578	__be16 l2_rewrite_vlan_tci;
..	..	@@ -5525,21 +6596,65 @@
5525	6596	__be16 nat_port;
5526	6597	__be16 l2_rewrite_smac[3];
5527	6598	u8 ip_proto;
5528		- u8 unused_0;
	6599	+ u8 tunnel_type;
	6600	+ #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
	6601	+ #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
	6602	+ #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
	6603	+ #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
	6604	+ #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
	6605	+ #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
	6606	+ #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
	6607	+ #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
	6608	+ #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
	6609	+ #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
	6610	+ #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
	6611	+ #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
	6612	+ #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
	6613	+ #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
	6614	+ #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
5529	6615	};
5530	6616
5531		-/* hwrm_cfa_flow_alloc_output (size:128b/16B) */
	6617	+/* hwrm_cfa_flow_alloc_output (size:256b/32B) */
5532	6618	struct hwrm_cfa_flow_alloc_output {
5533	6619	__le16 error_code;
5534	6620	__le16 req_type;
5535	6621	__le16 seq_id;
5536	6622	__le16 resp_len;
5537	6623	__le16 flow_handle;
5538		- u8 unused_0[5];
	6624	+ u8 unused_0[2];
	6625	+ __le32 flow_id;
	6626	+ #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL
	6627	+ #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_SFT 0
	6628	+ #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL
	6629	+ #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30)
	6630	+ #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30)
	6631	+ #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT
	6632	+ #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL
	6633	+ #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31)
	6634	+ #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31)
	6635	+ #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX
	6636	+ __le64 ext_flow_handle;
	6637	+ __le32 flow_counter_id;
	6638	+ u8 unused_1[3];
5539	6639	u8 valid;
5540	6640	};
5541	6641
5542		-/* hwrm_cfa_flow_free_input (size:192b/24B) */
	6642	+/* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */
	6643	+struct hwrm_cfa_flow_alloc_cmd_err {
	6644	+ u8 code;
	6645	+ #define CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL
	6646	+ #define CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM 0x1UL
	6647	+ #define CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD 0x2UL
	6648	+ #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER 0x3UL
	6649	+ #define CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM 0x4UL
	6650	+ #define CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION 0x5UL
	6651	+ #define CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS 0x6UL
	6652	+ #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 0x7UL
	6653	+ #define CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB
	6654	+ u8 unused_0[7];
	6655	+};
	6656	+
	6657	+/* hwrm_cfa_flow_free_input (size:256b/32B) */
5543	6658	struct hwrm_cfa_flow_free_input {
5544	6659	__le16 req_type;
5545	6660	__le16 cmpl_ring;
..	..	@@ -5547,7 +6662,9 @@
5547	6662	__le16 target_id;
5548	6663	__le64 resp_addr;
5549	6664	__le16 flow_handle;
5550		- u8 unused_0[6];
	6665	+ __le16 unused_0;
	6666	+ __le32 flow_counter_id;
	6667	+ __le64 ext_flow_handle;
5551	6668	};
5552	6669
5553	6670	/* hwrm_cfa_flow_free_output (size:256b/32B) */
..	..	@@ -5562,7 +6679,52 @@
5562	6679	u8 valid;
5563	6680	};
5564	6681
5565		-/* hwrm_cfa_flow_stats_input (size:320b/40B) */
	6682	+/* hwrm_cfa_flow_info_input (size:256b/32B) */
	6683	+struct hwrm_cfa_flow_info_input {
	6684	+ __le16 req_type;
	6685	+ __le16 cmpl_ring;
	6686	+ __le16 seq_id;
	6687	+ __le16 target_id;
	6688	+ __le64 resp_addr;
	6689	+ __le16 flow_handle;
	6690	+ #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_MASK 0xfffUL
	6691	+ #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_SFT 0
	6692	+ #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT 0x1000UL
	6693	+ #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT 0x2000UL
	6694	+ #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT 0x4000UL
	6695	+ #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_DIR_RX 0x8000UL
	6696	+ u8 unused_0[6];
	6697	+ __le64 ext_flow_handle;
	6698	+};
	6699	+
	6700	+/* hwrm_cfa_flow_info_output (size:5632b/704B) */
	6701	+struct hwrm_cfa_flow_info_output {
	6702	+ __le16 error_code;
	6703	+ __le16 req_type;
	6704	+ __le16 seq_id;
	6705	+ __le16 resp_len;
	6706	+ u8 flags;
	6707	+ #define CFA_FLOW_INFO_RESP_FLAGS_PATH_TX 0x1UL
	6708	+ #define CFA_FLOW_INFO_RESP_FLAGS_PATH_RX 0x2UL
	6709	+ u8 profile;
	6710	+ __le16 src_fid;
	6711	+ __le16 dst_fid;
	6712	+ __le16 l2_ctxt_id;
	6713	+ __le64 em_info;
	6714	+ __le64 tcam_info;
	6715	+ __le64 vfp_tcam_info;
	6716	+ __le16 ar_id;
	6717	+ __le16 flow_handle;
	6718	+ __le32 tunnel_handle;
	6719	+ __le16 flow_timer;
	6720	+ u8 unused_0[6];
	6721	+ __le32 flow_key_data[130];
	6722	+ __le32 flow_action_info[30];
	6723	+ u8 unused_1[7];
	6724	+ u8 valid;
	6725	+};
	6726	+
	6727	+/* hwrm_cfa_flow_stats_input (size:640b/80B) */
5566	6728	struct hwrm_cfa_flow_stats_input {
5567	6729	__le16 req_type;
5568	6730	__le16 cmpl_ring;
..	..	@@ -5581,6 +6743,16 @@
5581	6743	__le16 flow_handle_8;
5582	6744	__le16 flow_handle_9;
5583	6745	u8 unused_0[2];
	6746	+ __le32 flow_id_0;
	6747	+ __le32 flow_id_1;
	6748	+ __le32 flow_id_2;
	6749	+ __le32 flow_id_3;
	6750	+ __le32 flow_id_4;
	6751	+ __le32 flow_id_5;
	6752	+ __le32 flow_id_6;
	6753	+ __le32 flow_id_7;
	6754	+ __le32 flow_id_8;
	6755	+ __le32 flow_id_9;
5584	6756	};
5585	6757
5586	6758	/* hwrm_cfa_flow_stats_output (size:1408b/176B) */
..	..	@@ -5638,7 +6810,7 @@
5638	6810	u8 valid;
5639	6811	};
5640	6812
5641		-/* hwrm_cfa_vfr_free_input (size:384b/48B) */
	6813	+/* hwrm_cfa_vfr_free_input (size:448b/56B) */
5642	6814	struct hwrm_cfa_vfr_free_input {
5643	6815	__le16 req_type;
5644	6816	__le16 cmpl_ring;
..	..	@@ -5646,6 +6818,9 @@
5646	6818	__le16 target_id;
5647	6819	__le64 resp_addr;
5648	6820	char vfr_name[32];
	6821	+ __le16 vf_id;
	6822	+ __le16 reserved;
	6823	+ u8 unused_0[4];
5649	6824	};
5650	6825
5651	6826	/* hwrm_cfa_vfr_free_output (size:128b/16B) */
..	..	@@ -5658,6 +6833,180 @@
5658	6833	u8 valid;
5659	6834	};
5660	6835
	6836	+/* hwrm_cfa_eem_qcaps_input (size:192b/24B) */
	6837	+struct hwrm_cfa_eem_qcaps_input {
	6838	+ __le16 req_type;
	6839	+ __le16 cmpl_ring;
	6840	+ __le16 seq_id;
	6841	+ __le16 target_id;
	6842	+ __le64 resp_addr;
	6843	+ __le32 flags;
	6844	+ #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_TX 0x1UL
	6845	+ #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_RX 0x2UL
	6846	+ #define CFA_EEM_QCAPS_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL
	6847	+ __le32 unused_0;
	6848	+};
	6849	+
	6850	+/* hwrm_cfa_eem_qcaps_output (size:320b/40B) */
	6851	+struct hwrm_cfa_eem_qcaps_output {
	6852	+ __le16 error_code;
	6853	+ __le16 req_type;
	6854	+ __le16 seq_id;
	6855	+ __le16 resp_len;
	6856	+ __le32 flags;
	6857	+ #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_TX 0x1UL
	6858	+ #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_RX 0x2UL
	6859	+ #define CFA_EEM_QCAPS_RESP_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x4UL
	6860	+ #define CFA_EEM_QCAPS_RESP_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x8UL
	6861	+ __le32 unused_0;
	6862	+ __le32 supported;
	6863	+ #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY0_TABLE 0x1UL
	6864	+ #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY1_TABLE 0x2UL
	6865	+ #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_RECORD_TABLE 0x4UL
	6866	+ #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE 0x8UL
	6867	+ #define CFA_EEM_QCAPS_RESP_SUPPORTED_FID_TABLE 0x10UL
	6868	+ __le32 max_entries_supported;
	6869	+ __le16 key_entry_size;
	6870	+ __le16 record_entry_size;
	6871	+ __le16 efc_entry_size;
	6872	+ __le16 fid_entry_size;
	6873	+ u8 unused_1[7];
	6874	+ u8 valid;
	6875	+};
	6876	+
	6877	+/* hwrm_cfa_eem_cfg_input (size:384b/48B) */
	6878	+struct hwrm_cfa_eem_cfg_input {
	6879	+ __le16 req_type;
	6880	+ __le16 cmpl_ring;
	6881	+ __le16 seq_id;
	6882	+ __le16 target_id;
	6883	+ __le64 resp_addr;
	6884	+ __le32 flags;
	6885	+ #define CFA_EEM_CFG_REQ_FLAGS_PATH_TX 0x1UL
	6886	+ #define CFA_EEM_CFG_REQ_FLAGS_PATH_RX 0x2UL
	6887	+ #define CFA_EEM_CFG_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL
	6888	+ #define CFA_EEM_CFG_REQ_FLAGS_SECONDARY_PF 0x8UL
	6889	+ __le16 group_id;
	6890	+ __le16 unused_0;
	6891	+ __le32 num_entries;
	6892	+ __le32 unused_1;
	6893	+ __le16 key0_ctx_id;
	6894	+ __le16 key1_ctx_id;
	6895	+ __le16 record_ctx_id;
	6896	+ __le16 efc_ctx_id;
	6897	+ __le16 fid_ctx_id;
	6898	+ __le16 unused_2;
	6899	+ __le32 unused_3;
	6900	+};
	6901	+
	6902	+/* hwrm_cfa_eem_cfg_output (size:128b/16B) */
	6903	+struct hwrm_cfa_eem_cfg_output {
	6904	+ __le16 error_code;
	6905	+ __le16 req_type;
	6906	+ __le16 seq_id;
	6907	+ __le16 resp_len;
	6908	+ u8 unused_0[7];
	6909	+ u8 valid;
	6910	+};
	6911	+
	6912	+/* hwrm_cfa_eem_qcfg_input (size:192b/24B) */
	6913	+struct hwrm_cfa_eem_qcfg_input {
	6914	+ __le16 req_type;
	6915	+ __le16 cmpl_ring;
	6916	+ __le16 seq_id;
	6917	+ __le16 target_id;
	6918	+ __le64 resp_addr;
	6919	+ __le32 flags;
	6920	+ #define CFA_EEM_QCFG_REQ_FLAGS_PATH_TX 0x1UL
	6921	+ #define CFA_EEM_QCFG_REQ_FLAGS_PATH_RX 0x2UL
	6922	+ __le32 unused_0;
	6923	+};
	6924	+
	6925	+/* hwrm_cfa_eem_qcfg_output (size:256b/32B) */
	6926	+struct hwrm_cfa_eem_qcfg_output {
	6927	+ __le16 error_code;
	6928	+ __le16 req_type;
	6929	+ __le16 seq_id;
	6930	+ __le16 resp_len;
	6931	+ __le32 flags;
	6932	+ #define CFA_EEM_QCFG_RESP_FLAGS_PATH_TX 0x1UL
	6933	+ #define CFA_EEM_QCFG_RESP_FLAGS_PATH_RX 0x2UL
	6934	+ #define CFA_EEM_QCFG_RESP_FLAGS_PREFERRED_OFFLOAD 0x4UL
	6935	+ __le32 num_entries;
	6936	+ __le16 key0_ctx_id;
	6937	+ __le16 key1_ctx_id;
	6938	+ __le16 record_ctx_id;
	6939	+ __le16 efc_ctx_id;
	6940	+ __le16 fid_ctx_id;
	6941	+ u8 unused_2[5];
	6942	+ u8 valid;
	6943	+};
	6944	+
	6945	+/* hwrm_cfa_eem_op_input (size:192b/24B) */
	6946	+struct hwrm_cfa_eem_op_input {
	6947	+ __le16 req_type;
	6948	+ __le16 cmpl_ring;
	6949	+ __le16 seq_id;
	6950	+ __le16 target_id;
	6951	+ __le64 resp_addr;
	6952	+ __le32 flags;
	6953	+ #define CFA_EEM_OP_REQ_FLAGS_PATH_TX 0x1UL
	6954	+ #define CFA_EEM_OP_REQ_FLAGS_PATH_RX 0x2UL
	6955	+ __le16 unused_0;
	6956	+ __le16 op;
	6957	+ #define CFA_EEM_OP_REQ_OP_RESERVED 0x0UL
	6958	+ #define CFA_EEM_OP_REQ_OP_EEM_DISABLE 0x1UL
	6959	+ #define CFA_EEM_OP_REQ_OP_EEM_ENABLE 0x2UL
	6960	+ #define CFA_EEM_OP_REQ_OP_EEM_CLEANUP 0x3UL
	6961	+ #define CFA_EEM_OP_REQ_OP_LAST CFA_EEM_OP_REQ_OP_EEM_CLEANUP
	6962	+};
	6963	+
	6964	+/* hwrm_cfa_eem_op_output (size:128b/16B) */
	6965	+struct hwrm_cfa_eem_op_output {
	6966	+ __le16 error_code;
	6967	+ __le16 req_type;
	6968	+ __le16 seq_id;
	6969	+ __le16 resp_len;
	6970	+ u8 unused_0[7];
	6971	+ u8 valid;
	6972	+};
	6973	+
	6974	+/* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */
	6975	+struct hwrm_cfa_adv_flow_mgnt_qcaps_input {
	6976	+ __le16 req_type;
	6977	+ __le16 cmpl_ring;
	6978	+ __le16 seq_id;
	6979	+ __le16 target_id;
	6980	+ __le64 resp_addr;
	6981	+ __le32 unused_0[4];
	6982	+};
	6983	+
	6984	+/* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */
	6985	+struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
	6986	+ __le16 error_code;
	6987	+ __le16 req_type;
	6988	+ __le16 seq_id;
	6989	+ __le16 resp_len;
	6990	+ __le32 flags;
	6991	+ #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_16BIT_SUPPORTED 0x1UL
	6992	+ #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_64BIT_SUPPORTED 0x2UL
	6993	+ #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_BATCH_DELETE_SUPPORTED 0x4UL
	6994	+ #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_RESET_ALL_SUPPORTED 0x8UL
	6995	+ #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED 0x10UL
	6996	+ #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TX_EEM_FLOW_SUPPORTED 0x20UL
	6997	+ #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RX_EEM_FLOW_SUPPORTED 0x40UL
	6998	+ #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED 0x80UL
	6999	+ #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED 0x100UL
	7000	+ #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_UNTAGGED_VLAN_SUPPORTED 0x200UL
	7001	+ #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_XDP_SUPPORTED 0x400UL
	7002	+ #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED 0x800UL
	7003	+ #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED 0x1000UL
	7004	+ #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED 0x2000UL
	7005	+ #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED 0x4000UL
	7006	+ u8 unused_0[3];
	7007	+ u8 valid;
	7008	+};
	7009	+
5661	7010	/* hwrm_tunnel_dst_port_query_input (size:192b/24B) */
5662	7011	struct hwrm_tunnel_dst_port_query_input {
5663	7012	__le16 req_type;
..	..	@@ -5666,11 +7015,13 @@
5666	7015	__le16 target_id;
5667	7016	__le64 resp_addr;
5668	7017	u8 tunnel_type;
5669		- #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL
5670		- #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL
5671		- #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
5672		- #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
5673		- #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1
	7018	+ #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL
	7019	+ #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL
	7020	+ #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
	7021	+ #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
	7022	+ #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
	7023	+ #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
	7024	+ #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6
5674	7025	u8 unused_0[7];
5675	7026	};
5676	7027
..	..	@@ -5694,11 +7045,13 @@
5694	7045	__le16 target_id;
5695	7046	__le64 resp_addr;
5696	7047	u8 tunnel_type;
5697		- #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
5698		- #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
5699		- #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
5700		- #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
5701		- #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1
	7048	+ #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
	7049	+ #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
	7050	+ #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
	7051	+ #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
	7052	+ #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
	7053	+ #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
	7054	+ #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6
5702	7055	u8 unused_0;
5703	7056	__be16 tunnel_dst_port_val;
5704	7057	u8 unused_1[4];
..	..	@@ -5723,11 +7076,13 @@
5723	7076	__le16 target_id;
5724	7077	__le64 resp_addr;
5725	7078	u8 tunnel_type;
5726		- #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL
5727		- #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL
5728		- #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
5729		- #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
5730		- #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1
	7079	+ #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL
	7080	+ #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL
	7081	+ #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
	7082	+ #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
	7083	+ #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
	7084	+ #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
	7085	+ #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6
5731	7086	u8 unused_0;
5732	7087	__le16 tunnel_dst_port_id;
5733	7088	u8 unused_1[4];
..	..	@@ -5749,15 +7104,15 @@
5749	7104	__le64 rx_mcast_pkts;
5750	7105	__le64 rx_bcast_pkts;
5751	7106	__le64 rx_discard_pkts;
5752		- __le64 rx_drop_pkts;
	7107	+ __le64 rx_error_pkts;
5753	7108	__le64 rx_ucast_bytes;
5754	7109	__le64 rx_mcast_bytes;
5755	7110	__le64 rx_bcast_bytes;
5756	7111	__le64 tx_ucast_pkts;
5757	7112	__le64 tx_mcast_pkts;
5758	7113	__le64 tx_bcast_pkts;
	7114	+ __le64 tx_error_pkts;
5759	7115	__le64 tx_discard_pkts;
5760		- __le64 tx_drop_pkts;
5761	7116	__le64 tx_ucast_bytes;
5762	7117	__le64 tx_mcast_bytes;
5763	7118	__le64 tx_bcast_bytes;
..	..	@@ -5765,6 +7120,32 @@
5765	7120	__le64 tpa_bytes;
5766	7121	__le64 tpa_events;
5767	7122	__le64 tpa_aborts;
	7123	+};
	7124	+
	7125	+/* ctx_hw_stats_ext (size:1408b/176B) */
	7126	+struct ctx_hw_stats_ext {
	7127	+ __le64 rx_ucast_pkts;
	7128	+ __le64 rx_mcast_pkts;
	7129	+ __le64 rx_bcast_pkts;
	7130	+ __le64 rx_discard_pkts;
	7131	+ __le64 rx_error_pkts;
	7132	+ __le64 rx_ucast_bytes;
	7133	+ __le64 rx_mcast_bytes;
	7134	+ __le64 rx_bcast_bytes;
	7135	+ __le64 tx_ucast_pkts;
	7136	+ __le64 tx_mcast_pkts;
	7137	+ __le64 tx_bcast_pkts;
	7138	+ __le64 tx_error_pkts;
	7139	+ __le64 tx_discard_pkts;
	7140	+ __le64 tx_ucast_bytes;
	7141	+ __le64 tx_mcast_bytes;
	7142	+ __le64 tx_bcast_bytes;
	7143	+ __le64 rx_tpa_eligible_pkt;
	7144	+ __le64 rx_tpa_eligible_bytes;
	7145	+ __le64 rx_tpa_pkt;
	7146	+ __le64 rx_tpa_bytes;
	7147	+ __le64 rx_tpa_errors;
	7148	+ __le64 rx_tpa_events;
5768	7149	};
5769	7150
5770	7151	/* hwrm_stat_ctx_alloc_input (size:256b/32B) */
..	..	@@ -5778,7 +7159,8 @@
5778	7159	__le32 update_period_ms;
5779	7160	u8 stat_ctx_flags;
5780	7161	#define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL
5781		- u8 unused_0[3];
	7162	+ u8 unused_0;
	7163	+ __le16 stats_dma_length;
5782	7164	};
5783	7165
5784	7166	/* hwrm_stat_ctx_alloc_output (size:128b/16B) */
..	..	@@ -5822,7 +7204,9 @@
5822	7204	__le16 target_id;
5823	7205	__le64 resp_addr;
5824	7206	__le32 stat_ctx_id;
5825		- u8 unused_0[4];
	7207	+ u8 flags;
	7208	+ #define STAT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL
	7209	+ u8 unused_0[3];
5826	7210	};
5827	7211
5828	7212	/* hwrm_stat_ctx_query_output (size:1408b/176B) */
..	..	@@ -5834,16 +7218,16 @@
5834	7218	__le64 tx_ucast_pkts;
5835	7219	__le64 tx_mcast_pkts;
5836	7220	__le64 tx_bcast_pkts;
5837		- __le64 tx_err_pkts;
5838		- __le64 tx_drop_pkts;
	7221	+ __le64 tx_discard_pkts;
	7222	+ __le64 tx_error_pkts;
5839	7223	__le64 tx_ucast_bytes;
5840	7224	__le64 tx_mcast_bytes;
5841	7225	__le64 tx_bcast_bytes;
5842	7226	__le64 rx_ucast_pkts;
5843	7227	__le64 rx_mcast_pkts;
5844	7228	__le64 rx_bcast_pkts;
5845		- __le64 rx_err_pkts;
5846		- __le64 rx_drop_pkts;
	7229	+ __le64 rx_discard_pkts;
	7230	+ __le64 rx_error_pkts;
5847	7231	__le64 rx_ucast_bytes;
5848	7232	__le64 rx_mcast_bytes;
5849	7233	__le64 rx_bcast_bytes;
..	..	@@ -5851,6 +7235,51 @@
5851	7235	__le64 rx_agg_bytes;
5852	7236	__le64 rx_agg_events;
5853	7237	__le64 rx_agg_aborts;
	7238	+ u8 unused_0[7];
	7239	+ u8 valid;
	7240	+};
	7241	+
	7242	+/* hwrm_stat_ext_ctx_query_input (size:192b/24B) */
	7243	+struct hwrm_stat_ext_ctx_query_input {
	7244	+ __le16 req_type;
	7245	+ __le16 cmpl_ring;
	7246	+ __le16 seq_id;
	7247	+ __le16 target_id;
	7248	+ __le64 resp_addr;
	7249	+ __le32 stat_ctx_id;
	7250	+ u8 flags;
	7251	+ #define STAT_EXT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL
	7252	+ u8 unused_0[3];
	7253	+};
	7254	+
	7255	+/* hwrm_stat_ext_ctx_query_output (size:1536b/192B) */
	7256	+struct hwrm_stat_ext_ctx_query_output {
	7257	+ __le16 error_code;
	7258	+ __le16 req_type;
	7259	+ __le16 seq_id;
	7260	+ __le16 resp_len;
	7261	+ __le64 rx_ucast_pkts;
	7262	+ __le64 rx_mcast_pkts;
	7263	+ __le64 rx_bcast_pkts;
	7264	+ __le64 rx_discard_pkts;
	7265	+ __le64 rx_error_pkts;
	7266	+ __le64 rx_ucast_bytes;
	7267	+ __le64 rx_mcast_bytes;
	7268	+ __le64 rx_bcast_bytes;
	7269	+ __le64 tx_ucast_pkts;
	7270	+ __le64 tx_mcast_pkts;
	7271	+ __le64 tx_bcast_pkts;
	7272	+ __le64 tx_error_pkts;
	7273	+ __le64 tx_discard_pkts;
	7274	+ __le64 tx_ucast_bytes;
	7275	+ __le64 tx_mcast_bytes;
	7276	+ __le64 tx_bcast_bytes;
	7277	+ __le64 rx_tpa_eligible_pkt;
	7278	+ __le64 rx_tpa_eligible_bytes;
	7279	+ __le64 rx_tpa_pkt;
	7280	+ __le64 rx_tpa_bytes;
	7281	+ __le64 rx_tpa_errors;
	7282	+ __le64 rx_tpa_events;
5854	7283	u8 unused_0[7];
5855	7284	u8 valid;
5856	7285	};
..	..	@@ -5922,22 +7351,26 @@
5922	7351	__le16 target_id;
5923	7352	__le64 resp_addr;
5924	7353	u8 embedded_proc_type;
5925		- #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL
5926		- #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL
5927		- #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL
5928		- #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL
5929		- #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL
5930		- #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL
5931		- #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL
5932		- #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 0x7UL
5933		- #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT
	7354	+ #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL
	7355	+ #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL
	7356	+ #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL
	7357	+ #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL
	7358	+ #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL
	7359	+ #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL
	7360	+ #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL
	7361	+ #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 0x7UL
	7362	+ #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 0x8UL
	7363	+ #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION
5934	7364	u8 selfrst_status;
5935		- #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL
5936		- #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL
5937		- #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL
5938		- #define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST
	7365	+ #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL
	7366	+ #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL
	7367	+ #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL
	7368	+ #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL
	7369	+ #define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE
5939	7370	u8 host_idx;
5940		- u8 unused_0[5];
	7371	+ u8 flags;
	7372	+ #define FW_RESET_REQ_FLAGS_RESET_GRACEFUL 0x1UL
	7373	+ u8 unused_0[4];
5941	7374	};
5942	7375
5943	7376	/* hwrm_fw_reset_output (size:128b/16B) */
..	..	@@ -5947,10 +7380,11 @@
5947	7380	__le16 seq_id;
5948	7381	__le16 resp_len;
5949	7382	u8 selfrst_status;
5950		- #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL
5951		- #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL
5952		- #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL
5953		- #define FW_RESET_RESP_SELFRST_STATUS_LAST FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST
	7383	+ #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL
	7384	+ #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL
	7385	+ #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL
	7386	+ #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL
	7387	+ #define FW_RESET_RESP_SELFRST_STATUS_LAST FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE
5954	7388	u8 unused_0[6];
5955	7389	u8 valid;
5956	7390	};
..	..	@@ -5984,7 +7418,8 @@
5984	7418	#define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL
5985	7419	#define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL
5986	7420	#define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL
5987		- #define FW_QSTATUS_RESP_SELFRST_STATUS_LAST FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST
	7421	+ #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 0x3UL
	7422	+ #define FW_QSTATUS_RESP_SELFRST_STATUS_LAST FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER
5988	7423	u8 unused_0[6];
5989	7424	u8 valid;
5990	7425	};
..	..	@@ -6007,8 +7442,8 @@
6007	7442	u8 unused_0;
6008	7443	__le16 millisecond;
6009	7444	__le16 zone;
6010		- #define FW_SET_TIME_REQ_ZONE_UTC 0x0UL
6011		- #define FW_SET_TIME_REQ_ZONE_UNKNOWN 0xffffUL
	7445	+ #define FW_SET_TIME_REQ_ZONE_UTC 0
	7446	+ #define FW_SET_TIME_REQ_ZONE_UNKNOWN 65535
6012	7447	#define FW_SET_TIME_REQ_ZONE_LAST FW_SET_TIME_REQ_ZONE_UNKNOWN
6013	7448	u8 unused_1[4];
6014	7449	};
..	..	@@ -6033,6 +7468,7 @@
6033	7468	#define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL
6034	7469	#define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL
6035	7470	#define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL
	7471	+ #define STRUCT_HDR_STRUCT_ID_POWER_BKUP 0x427UL
6036	7472	#define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL
6037	7473	#define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL
6038	7474	#define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL
..	..	@@ -6247,7 +7683,14 @@
6247	7683	__le16 seq_id;
6248	7684	__le16 resp_len;
6249	7685	u8 temp;
6250		- u8 unused_0[6];
	7686	+ u8 phy_temp;
	7687	+ u8 om_temp;
	7688	+ u8 flags;
	7689	+ #define TEMP_MONITOR_QUERY_RESP_FLAGS_TEMP_NOT_AVAILABLE 0x1UL
	7690	+ #define TEMP_MONITOR_QUERY_RESP_FLAGS_PHY_TEMP_NOT_AVAILABLE 0x2UL
	7691	+ #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_NOT_PRESENT 0x4UL
	7692	+ #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_TEMP_NOT_AVAILABLE 0x8UL
	7693	+ u8 unused_0[3];
6251	7694	u8 valid;
6252	7695	};
6253	7696
..	..	@@ -6390,6 +7833,100 @@
6390	7833	u8 valid;
6391	7834	};
6392	7835
	7836	+/* hwrm_dbg_read_direct_input (size:256b/32B) */
	7837	+struct hwrm_dbg_read_direct_input {
	7838	+ __le16 req_type;
	7839	+ __le16 cmpl_ring;
	7840	+ __le16 seq_id;
	7841	+ __le16 target_id;
	7842	+ __le64 resp_addr;
	7843	+ __le64 host_dest_addr;
	7844	+ __le32 read_addr;
	7845	+ __le32 read_len32;
	7846	+};
	7847	+
	7848	+/* hwrm_dbg_read_direct_output (size:128b/16B) */
	7849	+struct hwrm_dbg_read_direct_output {
	7850	+ __le16 error_code;
	7851	+ __le16 req_type;
	7852	+ __le16 seq_id;
	7853	+ __le16 resp_len;
	7854	+ __le32 crc32;
	7855	+ u8 unused_0[3];
	7856	+ u8 valid;
	7857	+};
	7858	+
	7859	+/* hwrm_dbg_qcaps_input (size:192b/24B) */
	7860	+struct hwrm_dbg_qcaps_input {
	7861	+ __le16 req_type;
	7862	+ __le16 cmpl_ring;
	7863	+ __le16 seq_id;
	7864	+ __le16 target_id;
	7865	+ __le64 resp_addr;
	7866	+ __le16 fid;
	7867	+ u8 unused_0[6];
	7868	+};
	7869	+
	7870	+/* hwrm_dbg_qcaps_output (size:192b/24B) */
	7871	+struct hwrm_dbg_qcaps_output {
	7872	+ __le16 error_code;
	7873	+ __le16 req_type;
	7874	+ __le16 seq_id;
	7875	+ __le16 resp_len;
	7876	+ __le16 fid;
	7877	+ u8 unused_0[2];
	7878	+ __le32 coredump_component_disable_caps;
	7879	+ #define DBG_QCAPS_RESP_COREDUMP_COMPONENT_DISABLE_CAPS_NVRAM 0x1UL
	7880	+ __le32 flags;
	7881	+ #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_NVM 0x1UL
	7882	+ #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_HOST_DDR 0x2UL
	7883	+ #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_SOC_DDR 0x4UL
	7884	+ u8 unused_1[3];
	7885	+ u8 valid;
	7886	+};
	7887	+
	7888	+/* hwrm_dbg_qcfg_input (size:192b/24B) */
	7889	+struct hwrm_dbg_qcfg_input {
	7890	+ __le16 req_type;
	7891	+ __le16 cmpl_ring;
	7892	+ __le16 seq_id;
	7893	+ __le16 target_id;
	7894	+ __le64 resp_addr;
	7895	+ __le16 fid;
	7896	+ __le16 flags;
	7897	+ #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_MASK 0x3UL
	7898	+ #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_SFT 0
	7899	+ #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_NVM 0x0UL
	7900	+ #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_HOST_DDR 0x1UL
	7901	+ #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR 0x2UL
	7902	+ #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_LAST DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR
	7903	+ __le32 coredump_component_disable_flags;
	7904	+ #define DBG_QCFG_REQ_COREDUMP_COMPONENT_DISABLE_FLAGS_NVRAM 0x1UL
	7905	+};
	7906	+
	7907	+/* hwrm_dbg_qcfg_output (size:256b/32B) */
	7908	+struct hwrm_dbg_qcfg_output {
	7909	+ __le16 error_code;
	7910	+ __le16 req_type;
	7911	+ __le16 seq_id;
	7912	+ __le16 resp_len;
	7913	+ __le16 fid;
	7914	+ u8 unused_0[2];
	7915	+ __le32 coredump_size;
	7916	+ __le32 flags;
	7917	+ #define DBG_QCFG_RESP_FLAGS_UART_LOG 0x1UL
	7918	+ #define DBG_QCFG_RESP_FLAGS_UART_LOG_SECONDARY 0x2UL
	7919	+ #define DBG_QCFG_RESP_FLAGS_FW_TRACE 0x4UL
	7920	+ #define DBG_QCFG_RESP_FLAGS_FW_TRACE_SECONDARY 0x8UL
	7921	+ #define DBG_QCFG_RESP_FLAGS_DEBUG_NOTIFY 0x10UL
	7922	+ #define DBG_QCFG_RESP_FLAGS_JTAG_DEBUG 0x20UL
	7923	+ __le16 async_cmpl_ring;
	7924	+ u8 unused_2[2];
	7925	+ __le32 crashdump_size;
	7926	+ u8 unused_3[3];
	7927	+ u8 valid;
	7928	+};
	7929	+
6393	7930	/* coredump_segment_record (size:128b/16B) */
6394	7931	struct coredump_segment_record {
6395	7932	__le16 component_id;
..	..	@@ -6398,7 +7935,10 @@
6398	7935	u8 version_hi;
6399	7936	u8 version_low;
6400	7937	u8 seg_flags;
6401		- u8 unused_0[7];
	7938	+ u8 compress_flags;
	7939	+ #define SFLAG_COMPRESSED_ZLIB 0x1UL
	7940	+ u8 unused_0[2];
	7941	+ __le32 segment_len;
6402	7942	};
6403	7943
6404	7944	/* hwrm_dbg_coredump_list_input (size:256b/32B) */
..	..	@@ -6411,7 +7951,9 @@
6411	7951	__le64 host_dest_addr;
6412	7952	__le32 host_buf_len;
6413	7953	__le16 seq_no;
6414		- u8 unused_0[2];
	7954	+ u8 flags;
	7955	+ #define DBG_COREDUMP_LIST_REQ_FLAGS_CRASHDUMP 0x1UL
	7956	+ u8 unused_0[1];
6415	7957	};
6416	7958
6417	7959	/* hwrm_dbg_coredump_list_output (size:128b/16B) */
..	..	@@ -6495,6 +8037,36 @@
6495	8037	u8 unused_0;
6496	8038	__le16 data_len;
6497	8039	u8 unused_1[3];
	8040	+ u8 valid;
	8041	+};
	8042	+
	8043	+/* hwrm_dbg_ring_info_get_input (size:192b/24B) */
	8044	+struct hwrm_dbg_ring_info_get_input {
	8045	+ __le16 req_type;
	8046	+ __le16 cmpl_ring;
	8047	+ __le16 seq_id;
	8048	+ __le16 target_id;
	8049	+ __le64 resp_addr;
	8050	+ u8 ring_type;
	8051	+ #define DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL 0x0UL
	8052	+ #define DBG_RING_INFO_GET_REQ_RING_TYPE_TX 0x1UL
	8053	+ #define DBG_RING_INFO_GET_REQ_RING_TYPE_RX 0x2UL
	8054	+ #define DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 0x3UL
	8055	+ #define DBG_RING_INFO_GET_REQ_RING_TYPE_LAST DBG_RING_INFO_GET_REQ_RING_TYPE_NQ
	8056	+ u8 unused_0[3];
	8057	+ __le32 fw_ring_id;
	8058	+};
	8059	+
	8060	+/* hwrm_dbg_ring_info_get_output (size:192b/24B) */
	8061	+struct hwrm_dbg_ring_info_get_output {
	8062	+ __le16 error_code;
	8063	+ __le16 req_type;
	8064	+ __le16 seq_id;
	8065	+ __le16 resp_len;
	8066	+ __le32 producer_index;
	8067	+ __le32 consumer_index;
	8068	+ __le32 cag_vector_ctrl;
	8069	+ u8 unused_0[3];
6498	8070	u8 valid;
6499	8071	};
6500	8072
..	..	@@ -6615,7 +8187,9 @@
6615	8187	__le64 resp_addr;
6616	8188	__le64 host_src_addr;
6617	8189	__le16 dir_idx;
6618		- u8 unused_0[2];
	8190	+ __le16 flags;
	8191	+ #define NVM_MODIFY_REQ_FLAGS_BATCH_MODE 0x1UL
	8192	+ #define NVM_MODIFY_REQ_FLAGS_BATCH_LAST 0x2UL
6619	8193	__le32 offset;
6620	8194	__le32 len;
6621	8195	u8 unused_1[4];
..	..	@@ -6699,7 +8273,7 @@
6699	8273	__le64 resp_addr;
6700	8274	};
6701	8275
6702		-/* hwrm_nvm_get_dev_info_output (size:256b/32B) */
	8276	+/* hwrm_nvm_get_dev_info_output (size:640b/80B) */
6703	8277	struct hwrm_nvm_get_dev_info_output {
6704	8278	__le16 error_code;
6705	8279	__le16 req_type;
..	..	@@ -6711,7 +8285,25 @@
6711	8285	__le32 nvram_size;
6712	8286	__le32 reserved_size;
6713	8287	__le32 available_size;
6714		- u8 unused_0[3];
	8288	+ u8 nvm_cfg_ver_maj;
	8289	+ u8 nvm_cfg_ver_min;
	8290	+ u8 nvm_cfg_ver_upd;
	8291	+ u8 flags;
	8292	+ #define NVM_GET_DEV_INFO_RESP_FLAGS_FW_VER_VALID 0x1UL
	8293	+ char pkg_name[16];
	8294	+ __le16 hwrm_fw_major;
	8295	+ __le16 hwrm_fw_minor;
	8296	+ __le16 hwrm_fw_build;
	8297	+ __le16 hwrm_fw_patch;
	8298	+ __le16 mgmt_fw_major;
	8299	+ __le16 mgmt_fw_minor;
	8300	+ __le16 mgmt_fw_build;
	8301	+ __le16 mgmt_fw_patch;
	8302	+ __le16 roce_fw_major;
	8303	+ __le16 roce_fw_minor;
	8304	+ __le16 roce_fw_build;
	8305	+ __le16 roce_fw_patch;
	8306	+ u8 unused_0[7];
6715	8307	u8 valid;
6716	8308	};
6717	8309
..	..	@@ -6779,6 +8371,7 @@
6779	8371	#define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL
6780	8372	#define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL
6781	8373	#define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL
	8374	+ #define NVM_INSTALL_UPDATE_REQ_FLAGS_VERIFY_ONLY 0x8UL
6782	8375	u8 unused_0[2];
6783	8376	};
6784	8377
..	..	@@ -6891,6 +8484,9 @@
6891	8484	#define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_AES256 (0x2UL << 1)
6892	8485	#define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH (0x3UL << 1)
6893	8486	#define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH
	8487	+ #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_MASK 0x70UL
	8488	+ #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_SFT 4
	8489	+ #define NVM_SET_VARIABLE_REQ_FLAGS_FACTORY_DEFAULT 0x80UL
6894	8490	u8 unused_0;
6895	8491	};
6896	8492
..	..	@@ -6955,7 +8551,14 @@
6955	8551	char test5_name[32];
6956	8552	char test6_name[32];
6957	8553	char test7_name[32];
6958		- u8 unused_2[7];
	8554	+ u8 eyescope_target_BER_support;
	8555	+ #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E8_SUPPORTED 0x0UL
	8556	+ #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E9_SUPPORTED 0x1UL
	8557	+ #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E10_SUPPORTED 0x2UL
	8558	+ #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E11_SUPPORTED 0x3UL
	8559	+ #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 0x4UL
	8560	+ #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_LAST SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED
	8561	+ u8 unused_2[6];
6959	8562	u8 valid;
6960	8563	};
6961	8564
..	..	@@ -7019,4 +8622,54 @@
7019	8622	u8 valid;
7020	8623	};
7021	8624
	8625	+/* db_push_info (size:64b/8B) */
	8626	+struct db_push_info {
	8627	+ u32 push_size_push_index;
	8628	+ #define DB_PUSH_INFO_PUSH_INDEX_MASK 0xffffffUL
	8629	+ #define DB_PUSH_INFO_PUSH_INDEX_SFT 0
	8630	+ #define DB_PUSH_INFO_PUSH_SIZE_MASK 0x1f000000UL
	8631	+ #define DB_PUSH_INFO_PUSH_SIZE_SFT 24
	8632	+ u32 reserved32;
	8633	+};
	8634	+
	8635	+/* fw_status_reg (size:32b/4B) */
	8636	+struct fw_status_reg {
	8637	+ u32 fw_status;
	8638	+ #define FW_STATUS_REG_CODE_MASK 0xffffUL
	8639	+ #define FW_STATUS_REG_CODE_SFT 0
	8640	+ #define FW_STATUS_REG_CODE_READY 0x8000UL
	8641	+ #define FW_STATUS_REG_CODE_LAST FW_STATUS_REG_CODE_READY
	8642	+ #define FW_STATUS_REG_IMAGE_DEGRADED 0x10000UL
	8643	+ #define FW_STATUS_REG_RECOVERABLE 0x20000UL
	8644	+ #define FW_STATUS_REG_CRASHDUMP_ONGOING 0x40000UL
	8645	+ #define FW_STATUS_REG_CRASHDUMP_COMPLETE 0x80000UL
	8646	+ #define FW_STATUS_REG_SHUTDOWN 0x100000UL
	8647	+ #define FW_STATUS_REG_CRASHED_NO_MASTER 0x200000UL
	8648	+};
	8649	+
	8650	+/* hcomm_status (size:64b/8B) */
	8651	+struct hcomm_status {
	8652	+ u32 sig_ver;
	8653	+ #define HCOMM_STATUS_VER_MASK 0xffUL
	8654	+ #define HCOMM_STATUS_VER_SFT 0
	8655	+ #define HCOMM_STATUS_VER_LATEST 0x1UL
	8656	+ #define HCOMM_STATUS_VER_LAST HCOMM_STATUS_VER_LATEST
	8657	+ #define HCOMM_STATUS_SIGNATURE_MASK 0xffffff00UL
	8658	+ #define HCOMM_STATUS_SIGNATURE_SFT 8
	8659	+ #define HCOMM_STATUS_SIGNATURE_VAL (0x484353UL << 8)
	8660	+ #define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL
	8661	+ u32 fw_status_loc;
	8662	+ #define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK 0x3UL
	8663	+ #define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0
	8664	+ #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG 0x0UL
	8665	+ #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC 0x1UL
	8666	+ #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 0x2UL
	8667	+ #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 0x3UL
	8668	+ #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1
	8669	+ #define HCOMM_STATUS_TRUE_OFFSET_MASK 0xfffffffcUL
	8670	+ #define HCOMM_STATUS_TRUE_OFFSET_SFT 2
	8671	+};
	8672	+
	8673	+#define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL
	8674	+
7022	8675	#endif /* _BNXT_HSI_H_ */