~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,7 +1,7 @@
1	1	/* Broadcom NetXtreme-C/E network driver.
2	2	*
3	3	* Copyright (c) 2014-2016 Broadcom Corporation
4		- * Copyright (c) 2016-2018 Broadcom Limited
	4	+ * Copyright (c) 2016-2019 Broadcom Limited
5	5	*
6	6	* This program is free software; you can redistribute it and/or modify
7	7	* it under the terms of the GNU General Public License as published by
..	..	@@ -31,6 +31,7 @@
31	31	#include <asm/page.h>
32	32	#include <linux/time.h>
33	33	#include <linux/mii.h>
	34	+#include <linux/mdio.h>
34	35	#include <linux/if.h>
35	36	#include <linux/if_vlan.h>
36	37	#include <linux/if_bridge.h>
..	..	@@ -53,6 +54,7 @@
53	54	#include <net/pkt_cls.h>
54	55	#include <linux/hwmon.h>
55	56	#include <linux/hwmon-sysfs.h>
	57	+#include <net/page_pool.h>
56	58
57	59	#include "bnxt_hsi.h"
58	60	#include "bnxt.h"
..	..	@@ -67,13 +69,11 @@
67	69	#include "bnxt_debugfs.h"
68	70
69	71	#define BNXT_TX_TIMEOUT (5 * HZ)
70		-
71		-static const char version[] =
72		- "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
	72	+#define BNXT_DEF_MSG_ENABLE (NETIF_MSG_DRV \| NETIF_MSG_HW \| \
	73	+ NETIF_MSG_TX_ERR)
73	74
74	75	MODULE_LICENSE("GPL");
75	76	MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
76		-MODULE_VERSION(DRV_MODULE_VERSION);
77	77
78	78	#define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
79	79	#define BNXT_RX_DMA_OFFSET NET_SKB_PAD
..	..	@@ -111,12 +111,22 @@
111	111	BCM57452,
112	112	BCM57454,
113	113	BCM5745x_NPAR,
	114	+ BCM57508,
	115	+ BCM57504,
	116	+ BCM57502,
	117	+ BCM57508_NPAR,
	118	+ BCM57504_NPAR,
	119	+ BCM57502_NPAR,
114	120	BCM58802,
115	121	BCM58804,
116	122	BCM58808,
117	123	NETXTREME_E_VF,
118	124	NETXTREME_C_VF,
119	125	NETXTREME_S_VF,
	126	+ NETXTREME_C_VF_HV,
	127	+ NETXTREME_E_VF_HV,
	128	+ NETXTREME_E_P5_VF,
	129	+ NETXTREME_E_P5_VF_HV,
120	130	};
121	131
122	132	/* indexed by enum above */
..	..	@@ -152,12 +162,22 @@
152	162	[BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
153	163	[BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
154	164	[BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" },
	165	+ [BCM57508] = { "Broadcom BCM57508 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },
	166	+ [BCM57504] = { "Broadcom BCM57504 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },
	167	+ [BCM57502] = { "Broadcom BCM57502 NetXtreme-E 10Gb/25Gb/50Gb Ethernet" },
	168	+ [BCM57508_NPAR] = { "Broadcom BCM57508 NetXtreme-E Ethernet Partition" },
	169	+ [BCM57504_NPAR] = { "Broadcom BCM57504 NetXtreme-E Ethernet Partition" },
	170	+ [BCM57502_NPAR] = { "Broadcom BCM57502 NetXtreme-E Ethernet Partition" },
155	171	[BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" },
156	172	[BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
157	173	[BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
158	174	[NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" },
159	175	[NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" },
160	176	[NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" },
	177	+ [NETXTREME_C_VF_HV] = { "Broadcom NetXtreme-C Virtual Function for Hyper-V" },
	178	+ [NETXTREME_E_VF_HV] = { "Broadcom NetXtreme-E Virtual Function for Hyper-V" },
	179	+ [NETXTREME_E_P5_VF] = { "Broadcom BCM5750X NetXtreme-E Ethernet Virtual Function" },
	180	+ [NETXTREME_E_P5_VF_HV] = { "Broadcom BCM5750X NetXtreme-E Virtual Function for Hyper-V" },
161	181	};
162	182
163	183	static const struct pci_device_id bnxt_pci_tbl[] = {
..	..	@@ -196,17 +216,38 @@
196	216	{ PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
197	217	{ PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 },
198	218	{ PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 },
	219	+ { PCI_VDEVICE(BROADCOM, 0x1750), .driver_data = BCM57508 },
	220	+ { PCI_VDEVICE(BROADCOM, 0x1751), .driver_data = BCM57504 },
	221	+ { PCI_VDEVICE(BROADCOM, 0x1752), .driver_data = BCM57502 },
	222	+ { PCI_VDEVICE(BROADCOM, 0x1800), .driver_data = BCM57508_NPAR },
	223	+ { PCI_VDEVICE(BROADCOM, 0x1801), .driver_data = BCM57504_NPAR },
	224	+ { PCI_VDEVICE(BROADCOM, 0x1802), .driver_data = BCM57502_NPAR },
	225	+ { PCI_VDEVICE(BROADCOM, 0x1803), .driver_data = BCM57508_NPAR },
	226	+ { PCI_VDEVICE(BROADCOM, 0x1804), .driver_data = BCM57504_NPAR },
	227	+ { PCI_VDEVICE(BROADCOM, 0x1805), .driver_data = BCM57502_NPAR },
199	228	{ PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 },
200	229	{ PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 },
201	230	#ifdef CONFIG_BNXT_SRIOV
202	231	{ PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF },
	232	+ { PCI_VDEVICE(BROADCOM, 0x1607), .driver_data = NETXTREME_E_VF_HV },
	233	+ { PCI_VDEVICE(BROADCOM, 0x1608), .driver_data = NETXTREME_E_VF_HV },
203	234	{ PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF },
	235	+ { PCI_VDEVICE(BROADCOM, 0x16bd), .driver_data = NETXTREME_E_VF_HV },
204	236	{ PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
	237	+ { PCI_VDEVICE(BROADCOM, 0x16c2), .driver_data = NETXTREME_C_VF_HV },
	238	+ { PCI_VDEVICE(BROADCOM, 0x16c3), .driver_data = NETXTREME_C_VF_HV },
	239	+ { PCI_VDEVICE(BROADCOM, 0x16c4), .driver_data = NETXTREME_E_VF_HV },
	240	+ { PCI_VDEVICE(BROADCOM, 0x16c5), .driver_data = NETXTREME_E_VF_HV },
205	241	{ PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
206	242	{ PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
207	243	{ PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
208	244	{ PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
209	245	{ PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
	246	+ { PCI_VDEVICE(BROADCOM, 0x16e6), .driver_data = NETXTREME_C_VF_HV },
	247	+ { PCI_VDEVICE(BROADCOM, 0x1806), .driver_data = NETXTREME_E_P5_VF },
	248	+ { PCI_VDEVICE(BROADCOM, 0x1807), .driver_data = NETXTREME_E_P5_VF },
	249	+ { PCI_VDEVICE(BROADCOM, 0x1808), .driver_data = NETXTREME_E_P5_VF_HV },
	250	+ { PCI_VDEVICE(BROADCOM, 0x1809), .driver_data = NETXTREME_E_P5_VF_HV },
210	251	{ PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF },
211	252	#endif
212	253	{ 0 }
..	..	@@ -223,10 +264,16 @@
223	264
224	265	static const u16 bnxt_async_events_arr[] = {
225	266	ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
	267	+ ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE,
226	268	ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
227	269	ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
228	270	ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
229	271	ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
	272	+ ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE,
	273	+ ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY,
	274	+ ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY,
	275	+ ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION,
	276	+ ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG,
230	277	};
231	278
232	279	static struct workqueue_struct *bnxt_pf_wq;
..	..	@@ -234,21 +281,54 @@
234	281	static bool bnxt_vf_pciid(enum board_idx idx)
235	282	{
236	283	return (idx == NETXTREME_C_VF \|\| idx == NETXTREME_E_VF \|\|
237		- idx == NETXTREME_S_VF);
	284	+ idx == NETXTREME_S_VF \|\| idx == NETXTREME_C_VF_HV \|\|
	285	+ idx == NETXTREME_E_VF_HV \|\| idx == NETXTREME_E_P5_VF \|\|
	286	+ idx == NETXTREME_E_P5_VF_HV);
238	287	}
239	288
240	289	#define DB_CP_REARM_FLAGS (DB_KEY_CP \| DB_IDX_VALID)
241	290	#define DB_CP_FLAGS (DB_KEY_CP \| DB_IDX_VALID \| DB_IRQ_DIS)
242	291	#define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP \| DB_IRQ_DIS)
243	292
244		-#define BNXT_CP_DB_REARM(db, raw_cons) \
245		- writel(DB_CP_REARM_FLAGS \| RING_CMP(raw_cons), db)
246		-
247		-#define BNXT_CP_DB(db, raw_cons) \
248		- writel(DB_CP_FLAGS \| RING_CMP(raw_cons), db)
249		-
250	293	#define BNXT_CP_DB_IRQ_DIS(db) \
251	294	writel(DB_CP_IRQ_DIS_FLAGS, db)
	295	+
	296	+#define BNXT_DB_CQ(db, idx) \
	297	+ writel(DB_CP_FLAGS \| RING_CMP(idx), (db)->doorbell)
	298	+
	299	+#define BNXT_DB_NQ_P5(db, idx) \
	300	+ writeq((db)->db_key64 \| DBR_TYPE_NQ \| RING_CMP(idx), (db)->doorbell)
	301	+
	302	+#define BNXT_DB_CQ_ARM(db, idx) \
	303	+ writel(DB_CP_REARM_FLAGS \| RING_CMP(idx), (db)->doorbell)
	304	+
	305	+#define BNXT_DB_NQ_ARM_P5(db, idx) \
	306	+ writeq((db)->db_key64 \| DBR_TYPE_NQ_ARM \| RING_CMP(idx), (db)->doorbell)
	307	+
	308	+static void bnxt_db_nq(struct bnxt bp, struct bnxt_db_info db, u32 idx)
	309	+{
	310	+ if (bp->flags & BNXT_FLAG_CHIP_P5)
	311	+ BNXT_DB_NQ_P5(db, idx);
	312	+ else
	313	+ BNXT_DB_CQ(db, idx);
	314	+}
	315	+
	316	+static void bnxt_db_nq_arm(struct bnxt bp, struct bnxt_db_info db, u32 idx)
	317	+{
	318	+ if (bp->flags & BNXT_FLAG_CHIP_P5)
	319	+ BNXT_DB_NQ_ARM_P5(db, idx);
	320	+ else
	321	+ BNXT_DB_CQ_ARM(db, idx);
	322	+}
	323	+
	324	+static void bnxt_db_cq(struct bnxt bp, struct bnxt_db_info db, u32 idx)
	325	+{
	326	+ if (bp->flags & BNXT_FLAG_CHIP_P5)
	327	+ writeq(db->db_key64 \| DBR_TYPE_CQ_ARMALL \| RING_CMP(idx),
	328	+ db->doorbell);
	329	+ else
	330	+ BNXT_DB_CQ(db, idx);
	331	+}
252	332
253	333	const u16 bnxt_lhint_arr[] = {
254	334	TX_BD_FLAGS_LHINT_512_AND_SMALLER,
..	..	@@ -280,6 +360,13 @@
280	360	return 0;
281	361
282	362	return md_dst->u.port_info.port_id;
	363	+}
	364	+
	365	+static void bnxt_txr_db_kick(struct bnxt bp, struct bnxt_tx_ring_info txr,
	366	+ u16 prod)
	367	+{
	368	+ bnxt_db_write(bp, &txr->tx_db, prod);
	369	+ txr->kick_pending = 0;
283	370	}
284	371
285	372	static bool bnxt_txr_netif_try_stop_queue(struct bnxt *bp,
..	..	@@ -320,6 +407,7 @@
320	407	i = skb_get_queue_mapping(skb);
321	408	if (unlikely(i >= bp->tx_nr_rings)) {
322	409	dev_kfree_skb_any(skb);
	410	+ atomic_long_inc(&dev->tx_dropped);
323	411	return NETDEV_TX_OK;
324	412	}
325	413
..	..	@@ -329,6 +417,10 @@
329	417
330	418	free_size = bnxt_tx_avail(bp, txr);
331	419	if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
	420	+ /* We must have raced with NAPI cleanup */
	421	+ if (net_ratelimit() && txr->kick_pending)
	422	+ netif_warn(bp, tx_err, dev,
	423	+ "bnxt: ring busy w/ flush pending!\n");
332	424	if (bnxt_txr_netif_try_stop_queue(bp, txr, txq))
333	425	return NETDEV_TX_BUSY;
334	426	}
..	..	@@ -361,6 +453,7 @@
361	453	struct tx_push_buffer *tx_push_buf = txr->tx_push;
362	454	struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
363	455	struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
	456	+ void __iomem *db = txr->tx_db.doorbell;
364	457	void *pdata = tx_push_buf->data;
365	458	u64 *end;
366	459	int j, push_len;
..	..	@@ -418,12 +511,11 @@
418	511
419	512	push_len = (length + sizeof(*tx_push) + 7) / 8;
420	513	if (push_len > 16) {
421		- __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 16);
422		- __iowrite32_copy(txr->tx_doorbell + 4, tx_push_buf + 1,
	514	+ __iowrite64_copy(db, tx_push_buf, 16);
	515	+ __iowrite32_copy(db + 4, tx_push_buf + 1,
423	516	(push_len - 16) << 1);
424	517	} else {
425		- __iowrite64_copy(txr->tx_doorbell, tx_push_buf,
426		- push_len);
	518	+ __iowrite64_copy(db, tx_push_buf, push_len);
427	519	}
428	520
429	521	goto tx_done;
..	..	@@ -432,21 +524,16 @@
432	524	normal_tx:
433	525	if (length < BNXT_MIN_PKT_SIZE) {
434	526	pad = BNXT_MIN_PKT_SIZE - length;
435		- if (skb_pad(skb, pad)) {
	527	+ if (skb_pad(skb, pad))
436	528	/* SKB already freed. */
437		- tx_buf->skb = NULL;
438		- return NETDEV_TX_OK;
439		- }
	529	+ goto tx_kick_pending;
440	530	length = BNXT_MIN_PKT_SIZE;
441	531	}
442	532
443	533	mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
444	534
445		- if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
446		- dev_kfree_skb_any(skb);
447		- tx_buf->skb = NULL;
448		- return NETDEV_TX_OK;
449		- }
	535	+ if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
	536	+ goto tx_free;
450	537
451	538	dma_unmap_addr_set(tx_buf, mapping, mapping);
452	539	flags = (len << TX_BD_LEN_SHIFT) \| TX_BD_TYPE_LONG_TX_BD \|
..	..	@@ -530,16 +617,16 @@
530	617	prod = NEXT_TX(prod);
531	618	txr->tx_prod = prod;
532	619
533		- if (!skb->xmit_more \|\| netif_xmit_stopped(txq))
534		- bnxt_db_write(bp, txr->tx_doorbell, DB_KEY_TX \| prod);
	620	+ if (!netdev_xmit_more() \|\| netif_xmit_stopped(txq))
	621	+ bnxt_txr_db_kick(bp, txr, prod);
	622	+ else
	623	+ txr->kick_pending = 1;
535	624
536	625	tx_done:
537	626
538		- mmiowb();
539		-
540	627	if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
541		- if (skb->xmit_more && !tx_buf->is_push)
542		- bnxt_db_write(bp, txr->tx_doorbell, DB_KEY_TX \| prod);
	628	+ if (netdev_xmit_more() && !tx_buf->is_push)
	629	+ bnxt_txr_db_kick(bp, txr, prod);
543	630
544	631	bnxt_txr_netif_try_stop_queue(bp, txr, txq);
545	632	}
..	..	@@ -551,7 +638,6 @@
551	638	/* start back at beginning and unmap skb */
552	639	prod = txr->tx_prod;
553	640	tx_buf = &txr->tx_buf_ring[prod];
554		- tx_buf->skb = NULL;
555	641	dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
556	642	skb_headlen(skb), PCI_DMA_TODEVICE);
557	643	prod = NEXT_TX(prod);
..	..	@@ -565,7 +651,13 @@
565	651	PCI_DMA_TODEVICE);
566	652	}
567	653
	654	+tx_free:
568	655	dev_kfree_skb_any(skb);
	656	+tx_kick_pending:
	657	+ if (txr->kick_pending)
	658	+ bnxt_txr_db_kick(bp, txr, txr->tx_prod);
	659	+ txr->tx_buf_ring[txr->tx_prod].skb = NULL;
	660	+ atomic_long_inc(&dev->tx_dropped);
569	661	return NETDEV_TX_OK;
570	662	}
571	663
..	..	@@ -631,19 +723,20 @@
631	723	}
632	724
633	725	static struct page __bnxt_alloc_rx_page(struct bnxt bp, dma_addr_t *mapping,
	726	+ struct bnxt_rx_ring_info *rxr,
634	727	gfp_t gfp)
635	728	{
636	729	struct device *dev = &bp->pdev->dev;
637	730	struct page *page;
638	731
639		- page = alloc_page(gfp);
	732	+ page = page_pool_dev_alloc_pages(rxr->page_pool);
640	733	if (!page)
641	734	return NULL;
642	735
643	736	*mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir,
644	737	DMA_ATTR_WEAK_ORDERING);
645	738	if (dma_mapping_error(dev, *mapping)) {
646		- __free_page(page);
	739	+ page_pool_recycle_direct(rxr->page_pool, page);
647	740	return NULL;
648	741	}
649	742	*mapping += bp->rx_dma_offset;
..	..	@@ -679,7 +772,8 @@
679	772	dma_addr_t mapping;
680	773
681	774	if (BNXT_RX_PAGE_MODE(bp)) {
682		- struct page *page = __bnxt_alloc_rx_page(bp, &mapping, gfp);
	775	+ struct page *page =
	776	+ __bnxt_alloc_rx_page(bp, &mapping, rxr, gfp);
683	777
684	778	if (!page)
685	779	return -ENOMEM;
..	..	@@ -788,15 +882,40 @@
788	882	return 0;
789	883	}
790	884
791		-static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
792		- u32 agg_bufs)
	885	+static struct rx_agg_cmp bnxt_get_agg(struct bnxt bp,
	886	+ struct bnxt_cp_ring_info *cpr,
	887	+ u16 cp_cons, u16 curr)
793	888	{
	889	+ struct rx_agg_cmp *agg;
	890	+
	891	+ cp_cons = RING_CMP(ADV_RAW_CMP(cp_cons, curr));
	892	+ agg = (struct rx_agg_cmp *)
	893	+ &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
	894	+ return agg;
	895	+}
	896	+
	897	+static struct rx_agg_cmp bnxt_get_tpa_agg_p5(struct bnxt bp,
	898	+ struct bnxt_rx_ring_info *rxr,
	899	+ u16 agg_id, u16 curr)
	900	+{
	901	+ struct bnxt_tpa_info *tpa_info = &rxr->rx_tpa[agg_id];
	902	+
	903	+ return &tpa_info->agg_arr[curr];
	904	+}
	905	+
	906	+static void bnxt_reuse_rx_agg_bufs(struct bnxt_cp_ring_info *cpr, u16 idx,
	907	+ u16 start, u32 agg_bufs, bool tpa)
	908	+{
	909	+ struct bnxt_napi *bnapi = cpr->bnapi;
794	910	struct bnxt *bp = bnapi->bp;
795		- struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
796	911	struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
797	912	u16 prod = rxr->rx_agg_prod;
798	913	u16 sw_prod = rxr->rx_sw_agg_prod;
	914	+ bool p5_tpa = false;
799	915	u32 i;
	916	+
	917	+ if ((bp->flags & BNXT_FLAG_CHIP_P5) && tpa)
	918	+ p5_tpa = true;
800	919
801	920	for (i = 0; i < agg_bufs; i++) {
802	921	u16 cons;
..	..	@@ -805,8 +924,10 @@
805	924	struct rx_bd *prod_bd;
806	925	struct page *page;
807	926
808		- agg = (struct rx_agg_cmp *)
809		- &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
	927	+ if (p5_tpa)
	928	+ agg = bnxt_get_tpa_agg_p5(bp, rxr, idx, start + i);
	929	+ else
	930	+ agg = bnxt_get_agg(bp, cpr, idx, start + i);
810	931	cons = agg->rx_agg_cmp_opaque;
811	932	__clear_bit(cons, rxr->rx_agg_bmap);
812	933
..	..	@@ -834,7 +955,6 @@
834	955
835	956	prod = NEXT_RX_AGG(prod);
836	957	sw_prod = NEXT_RX_AGG(sw_prod);
837		- cp_cons = NEXT_CMP(cp_cons);
838	958	}
839	959	rxr->rx_agg_prod = prod;
840	960	rxr->rx_sw_agg_prod = sw_prod;
..	..	@@ -848,7 +968,7 @@
848	968	{
849	969	unsigned int payload = offset_and_len >> 16;
850	970	unsigned int len = offset_and_len & 0xffff;
851		- struct skb_frag_struct *frag;
	971	+ skb_frag_t *frag;
852	972	struct page *page = data;
853	973	u16 prod = rxr->rx_prod;
854	974	struct sk_buff *skb;
..	..	@@ -862,9 +982,10 @@
862	982	dma_addr -= bp->rx_dma_offset;
863	983	dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir,
864	984	DMA_ATTR_WEAK_ORDERING);
	985	+ page_pool_release_page(rxr->page_pool, page);
865	986
866	987	if (unlikely(!payload))
867		- payload = eth_get_headlen(data_ptr, len);
	988	+ payload = eth_get_headlen(bp->dev, data_ptr, len);
868	989
869	990	skb = napi_alloc_skb(&rxr->bnapi->napi, payload);
870	991	if (!skb) {
..	..	@@ -879,7 +1000,7 @@
879	1000
880	1001	frag = &skb_shinfo(skb)->frags[0];
881	1002	skb_frag_size_sub(frag, payload);
882		- frag->page_offset += payload;
	1003	+ skb_frag_off_add(frag, payload);
883	1004	skb->data_len -= payload;
884	1005	skb->tail += payload;
885	1006
..	..	@@ -915,15 +1036,20 @@
915	1036	return skb;
916	1037	}
917	1038
918		-static struct sk_buff bnxt_rx_pages(struct bnxt bp, struct bnxt_napi *bnapi,
919		- struct sk_buff *skb, u16 cp_cons,
920		- u32 agg_bufs)
	1039	+static struct sk_buff bnxt_rx_pages(struct bnxt bp,
	1040	+ struct bnxt_cp_ring_info *cpr,
	1041	+ struct sk_buff *skb, u16 idx,
	1042	+ u32 agg_bufs, bool tpa)
921	1043	{
	1044	+ struct bnxt_napi *bnapi = cpr->bnapi;
922	1045	struct pci_dev *pdev = bp->pdev;
923		- struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
924	1046	struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
925	1047	u16 prod = rxr->rx_agg_prod;
	1048	+ bool p5_tpa = false;
926	1049	u32 i;
	1050	+
	1051	+ if ((bp->flags & BNXT_FLAG_CHIP_P5) && tpa)
	1052	+ p5_tpa = true;
927	1053
928	1054	for (i = 0; i < agg_bufs; i++) {
929	1055	u16 cons, frag_len;
..	..	@@ -932,8 +1058,10 @@
932	1058	struct page *page;
933	1059	dma_addr_t mapping;
934	1060
935		- agg = (struct rx_agg_cmp *)
936		- &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
	1061	+ if (p5_tpa)
	1062	+ agg = bnxt_get_tpa_agg_p5(bp, rxr, idx, i);
	1063	+ else
	1064	+ agg = bnxt_get_agg(bp, cpr, idx, i);
937	1065	cons = agg->rx_agg_cmp_opaque;
938	1066	frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
939	1067	RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
..	..	@@ -967,7 +1095,7 @@
967	1095	* allocated already.
968	1096	*/
969	1097	rxr->rx_agg_prod = prod;
970		- bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
	1098	+ bnxt_reuse_rx_agg_bufs(cpr, idx, i, agg_bufs - i, tpa);
971	1099	return NULL;
972	1100	}
973	1101
..	..	@@ -980,7 +1108,6 @@
980	1108	skb->truesize += PAGE_SIZE;
981	1109
982	1110	prod = NEXT_RX_AGG(prod);
983		- cp_cons = NEXT_CMP(cp_cons);
984	1111	}
985	1112	rxr->rx_agg_prod = prod;
986	1113	return skb;
..	..	@@ -1024,10 +1151,9 @@
1024	1151	return skb;
1025	1152	}
1026	1153
1027		-static int bnxt_discard_rx(struct bnxt bp, struct bnxt_napi bnapi,
	1154	+static int bnxt_discard_rx(struct bnxt bp, struct bnxt_cp_ring_info cpr,
1028	1155	u32 raw_cons, void cmp)
1029	1156	{
1030		- struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1031	1157	struct rx_cmp *rxcmp = cmp;
1032	1158	u32 tmp_raw_cons = *raw_cons;
1033	1159	u8 cmp_type, agg_bufs = 0;
..	..	@@ -1041,9 +1167,10 @@
1041	1167	} else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1042	1168	struct rx_tpa_end_cmp *tpa_end = cmp;
1043	1169
1044		- agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1045		- RX_TPA_END_CMP_AGG_BUFS) >>
1046		- RX_TPA_END_CMP_AGG_BUFS_SHIFT;
	1170	+ if (bp->flags & BNXT_FLAG_CHIP_P5)
	1171	+ return 0;
	1172	+
	1173	+ agg_bufs = TPA_END_AGG_BUFS(tpa_end);
1047	1174	}
1048	1175
1049	1176	if (agg_bufs) {
..	..	@@ -1054,6 +1181,17 @@
1054	1181	return 0;
1055	1182	}
1056	1183
	1184	+static void bnxt_queue_fw_reset_work(struct bnxt *bp, unsigned long delay)
	1185	+{
	1186	+ if (!(test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)))
	1187	+ return;
	1188	+
	1189	+ if (BNXT_PF(bp))
	1190	+ queue_delayed_work(bnxt_pf_wq, &bp->fw_reset_task, delay);
	1191	+ else
	1192	+ schedule_delayed_work(&bp->fw_reset_task, delay);
	1193	+}
	1194	+
1057	1195	static void bnxt_queue_sp_work(struct bnxt *bp)
1058	1196	{
1059	1197	if (BNXT_PF(bp))
..	..	@@ -1062,44 +1200,73 @@
1062	1200	schedule_work(&bp->sp_task);
1063	1201	}
1064	1202
1065		-static void bnxt_cancel_sp_work(struct bnxt *bp)
1066		-{
1067		- if (BNXT_PF(bp))
1068		- flush_workqueue(bnxt_pf_wq);
1069		- else
1070		- cancel_work_sync(&bp->sp_task);
1071		-}
1072		-
1073	1203	static void bnxt_sched_reset(struct bnxt bp, struct bnxt_rx_ring_info rxr)
1074	1204	{
1075	1205	if (!rxr->bnapi->in_reset) {
1076	1206	rxr->bnapi->in_reset = true;
1077		- set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
	1207	+ if (bp->flags & BNXT_FLAG_CHIP_P5)
	1208	+ set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
	1209	+ else
	1210	+ set_bit(BNXT_RST_RING_SP_EVENT, &bp->sp_event);
1078	1211	bnxt_queue_sp_work(bp);
1079	1212	}
1080	1213	rxr->rx_next_cons = 0xffff;
	1214	+}
	1215	+
	1216	+static u16 bnxt_alloc_agg_idx(struct bnxt_rx_ring_info *rxr, u16 agg_id)
	1217	+{
	1218	+ struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map;
	1219	+ u16 idx = agg_id & MAX_TPA_P5_MASK;
	1220	+
	1221	+ if (test_bit(idx, map->agg_idx_bmap))
	1222	+ idx = find_first_zero_bit(map->agg_idx_bmap,
	1223	+ BNXT_AGG_IDX_BMAP_SIZE);
	1224	+ __set_bit(idx, map->agg_idx_bmap);
	1225	+ map->agg_id_tbl[agg_id] = idx;
	1226	+ return idx;
	1227	+}
	1228	+
	1229	+static void bnxt_free_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
	1230	+{
	1231	+ struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map;
	1232	+
	1233	+ __clear_bit(idx, map->agg_idx_bmap);
	1234	+}
	1235	+
	1236	+static u16 bnxt_lookup_agg_idx(struct bnxt_rx_ring_info *rxr, u16 agg_id)
	1237	+{
	1238	+ struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map;
	1239	+
	1240	+ return map->agg_id_tbl[agg_id];
1081	1241	}
1082	1242
1083	1243	static void bnxt_tpa_start(struct bnxt bp, struct bnxt_rx_ring_info rxr,
1084	1244	struct rx_tpa_start_cmp *tpa_start,
1085	1245	struct rx_tpa_start_cmp_ext *tpa_start1)
1086	1246	{
1087		- u8 agg_id = TPA_START_AGG_ID(tpa_start);
1088		- u16 cons, prod;
1089		- struct bnxt_tpa_info *tpa_info;
1090	1247	struct bnxt_sw_rx_bd cons_rx_buf, prod_rx_buf;
	1248	+ struct bnxt_tpa_info *tpa_info;
	1249	+ u16 cons, prod, agg_id;
1091	1250	struct rx_bd *prod_bd;
1092	1251	dma_addr_t mapping;
1093	1252
	1253	+ if (bp->flags & BNXT_FLAG_CHIP_P5) {
	1254	+ agg_id = TPA_START_AGG_ID_P5(tpa_start);
	1255	+ agg_id = bnxt_alloc_agg_idx(rxr, agg_id);
	1256	+ } else {
	1257	+ agg_id = TPA_START_AGG_ID(tpa_start);
	1258	+ }
1094	1259	cons = tpa_start->rx_tpa_start_cmp_opaque;
1095	1260	prod = rxr->rx_prod;
1096	1261	cons_rx_buf = &rxr->rx_buf_ring[cons];
1097	1262	prod_rx_buf = &rxr->rx_buf_ring[prod];
1098	1263	tpa_info = &rxr->rx_tpa[agg_id];
1099	1264
1100		- if (unlikely(cons != rxr->rx_next_cons)) {
1101		- netdev_warn(bp->dev, "TPA cons %x != expected cons %x\n",
1102		- cons, rxr->rx_next_cons);
	1265	+ if (unlikely(cons != rxr->rx_next_cons \|\|
	1266	+ TPA_START_ERROR(tpa_start))) {
	1267	+ netdev_warn(bp->dev, "TPA cons %x, expected cons %x, error code %x\n",
	1268	+ cons, rxr->rx_next_cons,
	1269	+ TPA_START_ERROR_CODE(tpa_start1));
1103	1270	bnxt_sched_reset(bp, rxr);
1104	1271	return;
1105	1272	}
..	..	@@ -1138,12 +1305,12 @@
1138	1305	} else {
1139	1306	tpa_info->hash_type = PKT_HASH_TYPE_NONE;
1140	1307	tpa_info->gso_type = 0;
1141		- if (netif_msg_rx_err(bp))
1142		- netdev_warn(bp->dev, "TPA packet without valid hash\n");
	1308	+ netif_warn(bp, rx_err, bp->dev, "TPA packet without valid hash\n");
1143	1309	}
1144	1310	tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
1145	1311	tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
1146	1312	tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
	1313	+ tpa_info->agg_count = 0;
1147	1314
1148	1315	rxr->rx_prod = NEXT_RX(prod);
1149	1316	cons = NEXT_RX(cons);
..	..	@@ -1155,12 +1322,36 @@
1155	1322	cons_rx_buf->data = NULL;
1156	1323	}
1157	1324
1158		-static void bnxt_abort_tpa(struct bnxt bp, struct bnxt_napi bnapi,
1159		- u16 cp_cons, u32 agg_bufs)
	1325	+static void bnxt_abort_tpa(struct bnxt_cp_ring_info *cpr, u16 idx, u32 agg_bufs)
1160	1326	{
1161	1327	if (agg_bufs)
1162		- bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
	1328	+ bnxt_reuse_rx_agg_bufs(cpr, idx, 0, agg_bufs, true);
1163	1329	}
	1330	+
	1331	+#ifdef CONFIG_INET
	1332	+static void bnxt_gro_tunnel(struct sk_buff *skb, __be16 ip_proto)
	1333	+{
	1334	+ struct udphdr *uh = NULL;
	1335	+
	1336	+ if (ip_proto == htons(ETH_P_IP)) {
	1337	+ struct iphdr iph = (struct iphdr )skb->data;
	1338	+
	1339	+ if (iph->protocol == IPPROTO_UDP)
	1340	+ uh = (struct udphdr *)(iph + 1);
	1341	+ } else {
	1342	+ struct ipv6hdr iph = (struct ipv6hdr )skb->data;
	1343	+
	1344	+ if (iph->nexthdr == IPPROTO_UDP)
	1345	+ uh = (struct udphdr *)(iph + 1);
	1346	+ }
	1347	+ if (uh) {
	1348	+ if (uh->check)
	1349	+ skb_shinfo(skb)->gso_type \|= SKB_GSO_UDP_TUNNEL_CSUM;
	1350	+ else
	1351	+ skb_shinfo(skb)->gso_type \|= SKB_GSO_UDP_TUNNEL;
	1352	+ }
	1353	+}
	1354	+#endif
1164	1355
1165	1356	static struct sk_buff bnxt_gro_func_5731x(struct bnxt_tpa_info tpa_info,
1166	1357	int payload_off, int tcp_ts,
..	..	@@ -1219,28 +1410,39 @@
1219	1410	}
1220	1411
1221	1412	if (inner_mac_off) { /* tunnel */
1222		- struct udphdr *uh = NULL;
1223	1413	__be16 proto = ((__be16 )(skb->data + outer_ip_off -
1224	1414	ETH_HLEN - 2));
1225	1415
1226		- if (proto == htons(ETH_P_IP)) {
1227		- struct iphdr iph = (struct iphdr )skb->data;
	1416	+ bnxt_gro_tunnel(skb, proto);
	1417	+ }
	1418	+#endif
	1419	+ return skb;
	1420	+}
1228	1421
1229		- if (iph->protocol == IPPROTO_UDP)
1230		- uh = (struct udphdr *)(iph + 1);
1231		- } else {
1232		- struct ipv6hdr iph = (struct ipv6hdr )skb->data;
	1422	+static struct sk_buff bnxt_gro_func_5750x(struct bnxt_tpa_info tpa_info,
	1423	+ int payload_off, int tcp_ts,
	1424	+ struct sk_buff *skb)
	1425	+{
	1426	+#ifdef CONFIG_INET
	1427	+ u16 outer_ip_off, inner_ip_off, inner_mac_off;
	1428	+ u32 hdr_info = tpa_info->hdr_info;
	1429	+ int iphdr_len, nw_off;
1233	1430
1234		- if (iph->nexthdr == IPPROTO_UDP)
1235		- uh = (struct udphdr *)(iph + 1);
1236		- }
1237		- if (uh) {
1238		- if (uh->check)
1239		- skb_shinfo(skb)->gso_type \|=
1240		- SKB_GSO_UDP_TUNNEL_CSUM;
1241		- else
1242		- skb_shinfo(skb)->gso_type \|= SKB_GSO_UDP_TUNNEL;
1243		- }
	1431	+ inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
	1432	+ inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
	1433	+ outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
	1434	+
	1435	+ nw_off = inner_ip_off - ETH_HLEN;
	1436	+ skb_set_network_header(skb, nw_off);
	1437	+ iphdr_len = (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) ?
	1438	+ sizeof(struct ipv6hdr) : sizeof(struct iphdr);
	1439	+ skb_set_transport_header(skb, nw_off + iphdr_len);
	1440	+
	1441	+ if (inner_mac_off) { /* tunnel */
	1442	+ __be16 proto = ((__be16 )(skb->data + outer_ip_off -
	1443	+ ETH_HLEN - 2));
	1444	+
	1445	+ bnxt_gro_tunnel(skb, proto);
1244	1446	}
1245	1447	#endif
1246	1448	return skb;
..	..	@@ -1287,28 +1489,8 @@
1287	1489	return NULL;
1288	1490	}
1289	1491
1290		- if (nw_off) { /* tunnel */
1291		- struct udphdr *uh = NULL;
1292		-
1293		- if (skb->protocol == htons(ETH_P_IP)) {
1294		- struct iphdr iph = (struct iphdr )skb->data;
1295		-
1296		- if (iph->protocol == IPPROTO_UDP)
1297		- uh = (struct udphdr *)(iph + 1);
1298		- } else {
1299		- struct ipv6hdr iph = (struct ipv6hdr )skb->data;
1300		-
1301		- if (iph->nexthdr == IPPROTO_UDP)
1302		- uh = (struct udphdr *)(iph + 1);
1303		- }
1304		- if (uh) {
1305		- if (uh->check)
1306		- skb_shinfo(skb)->gso_type \|=
1307		- SKB_GSO_UDP_TUNNEL_CSUM;
1308		- else
1309		- skb_shinfo(skb)->gso_type \|= SKB_GSO_UDP_TUNNEL;
1310		- }
1311		- }
	1492	+ if (nw_off) /* tunnel */
	1493	+ bnxt_gro_tunnel(skb, skb->protocol);
1312	1494	#endif
1313	1495	return skb;
1314	1496	}
..	..	@@ -1331,9 +1513,10 @@
1331	1513	skb_shinfo(skb)->gso_size =
1332	1514	le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1333	1515	skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1334		- payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1335		- RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
1336		- RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
	1516	+ if (bp->flags & BNXT_FLAG_CHIP_P5)
	1517	+ payload_off = TPA_END_PAYLOAD_OFF_P5(tpa_end1);
	1518	+ else
	1519	+ payload_off = TPA_END_PAYLOAD_OFF(tpa_end);
1337	1520	skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1338	1521	if (likely(skb))
1339	1522	tcp_gro_complete(skb);
..	..	@@ -1353,51 +1536,68 @@
1353	1536	}
1354	1537
1355	1538	static inline struct sk_buff bnxt_tpa_end(struct bnxt bp,
1356		- struct bnxt_napi *bnapi,
	1539	+ struct bnxt_cp_ring_info *cpr,
1357	1540	u32 *raw_cons,
1358	1541	struct rx_tpa_end_cmp *tpa_end,
1359	1542	struct rx_tpa_end_cmp_ext *tpa_end1,
1360	1543	u8 *event)
1361	1544	{
1362		- struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
	1545	+ struct bnxt_napi *bnapi = cpr->bnapi;
1363	1546	struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1364		- u8 agg_id = TPA_END_AGG_ID(tpa_end);
1365	1547	u8 *data_ptr, agg_bufs;
1366		- u16 cp_cons = RING_CMP(*raw_cons);
1367	1548	unsigned int len;
1368	1549	struct bnxt_tpa_info *tpa_info;
1369	1550	dma_addr_t mapping;
1370	1551	struct sk_buff *skb;
	1552	+ u16 idx = 0, agg_id;
1371	1553	void *data;
	1554	+ bool gro;
1372	1555
1373	1556	if (unlikely(bnapi->in_reset)) {
1374		- int rc = bnxt_discard_rx(bp, bnapi, raw_cons, tpa_end);
	1557	+ int rc = bnxt_discard_rx(bp, cpr, raw_cons, tpa_end);
1375	1558
1376	1559	if (rc < 0)
1377	1560	return ERR_PTR(-EBUSY);
1378	1561	return NULL;
1379	1562	}
1380	1563
1381		- tpa_info = &rxr->rx_tpa[agg_id];
	1564	+ if (bp->flags & BNXT_FLAG_CHIP_P5) {
	1565	+ agg_id = TPA_END_AGG_ID_P5(tpa_end);
	1566	+ agg_id = bnxt_lookup_agg_idx(rxr, agg_id);
	1567	+ agg_bufs = TPA_END_AGG_BUFS_P5(tpa_end1);
	1568	+ tpa_info = &rxr->rx_tpa[agg_id];
	1569	+ if (unlikely(agg_bufs != tpa_info->agg_count)) {
	1570	+ netdev_warn(bp->dev, "TPA end agg_buf %d != expected agg_bufs %d\n",
	1571	+ agg_bufs, tpa_info->agg_count);
	1572	+ agg_bufs = tpa_info->agg_count;
	1573	+ }
	1574	+ tpa_info->agg_count = 0;
	1575	+ *event \|= BNXT_AGG_EVENT;
	1576	+ bnxt_free_agg_idx(rxr, agg_id);
	1577	+ idx = agg_id;
	1578	+ gro = !!(bp->flags & BNXT_FLAG_GRO);
	1579	+ } else {
	1580	+ agg_id = TPA_END_AGG_ID(tpa_end);
	1581	+ agg_bufs = TPA_END_AGG_BUFS(tpa_end);
	1582	+ tpa_info = &rxr->rx_tpa[agg_id];
	1583	+ idx = RING_CMP(*raw_cons);
	1584	+ if (agg_bufs) {
	1585	+ if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
	1586	+ return ERR_PTR(-EBUSY);
	1587	+
	1588	+ *event \|= BNXT_AGG_EVENT;
	1589	+ idx = NEXT_CMP(idx);
	1590	+ }
	1591	+ gro = !!TPA_END_GRO(tpa_end);
	1592	+ }
1382	1593	data = tpa_info->data;
1383	1594	data_ptr = tpa_info->data_ptr;
1384	1595	prefetch(data_ptr);
1385	1596	len = tpa_info->len;
1386	1597	mapping = tpa_info->mapping;
1387	1598
1388		- agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1389		- RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1390		-
1391		- if (agg_bufs) {
1392		- if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1393		- return ERR_PTR(-EBUSY);
1394		-
1395		- *event \|= BNXT_AGG_EVENT;
1396		- cp_cons = NEXT_CMP(cp_cons);
1397		- }
1398		-
1399	1599	if (unlikely(agg_bufs > MAX_SKB_FRAGS \|\| TPA_END_ERRORS(tpa_end1))) {
1400		- bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
	1600	+ bnxt_abort_tpa(cpr, idx, agg_bufs);
1401	1601	if (agg_bufs > MAX_SKB_FRAGS)
1402	1602	netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1403	1603	agg_bufs, (int)MAX_SKB_FRAGS);
..	..	@@ -1407,7 +1607,7 @@
1407	1607	if (len <= bp->rx_copy_thresh) {
1408	1608	skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping);
1409	1609	if (!skb) {
1410		- bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
	1610	+ bnxt_abort_tpa(cpr, idx, agg_bufs);
1411	1611	return NULL;
1412	1612	}
1413	1613	} else {
..	..	@@ -1416,7 +1616,7 @@
1416	1616
1417	1617	new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1418	1618	if (!new_data) {
1419		- bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
	1619	+ bnxt_abort_tpa(cpr, idx, agg_bufs);
1420	1620	return NULL;
1421	1621	}
1422	1622
..	..	@@ -1431,7 +1631,7 @@
1431	1631
1432	1632	if (!skb) {
1433	1633	kfree(data);
1434		- bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
	1634	+ bnxt_abort_tpa(cpr, idx, agg_bufs);
1435	1635	return NULL;
1436	1636	}
1437	1637	skb_reserve(skb, bp->rx_offset);
..	..	@@ -1439,7 +1639,7 @@
1439	1639	}
1440	1640
1441	1641	if (agg_bufs) {
1442		- skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
	1642	+ skb = bnxt_rx_pages(bp, cpr, skb, idx, agg_bufs, true);
1443	1643	if (!skb) {
1444	1644	/* Page reuse already handled by bnxt_rx_pages(). */
1445	1645	return NULL;
..	..	@@ -1453,12 +1653,17 @@
1453	1653	skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1454	1654
1455	1655	if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1456		- (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1457		- u16 vlan_proto = tpa_info->metadata >>
1458		- RX_CMP_FLAGS2_METADATA_TPID_SFT;
	1656	+ (skb->dev->features & BNXT_HW_FEATURE_VLAN_ALL_RX)) {
	1657	+ __be16 vlan_proto = htons(tpa_info->metadata >>
	1658	+ RX_CMP_FLAGS2_METADATA_TPID_SFT);
1459	1659	u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1460	1660
1461		- __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
	1661	+ if (eth_type_vlan(vlan_proto)) {
	1662	+ __vlan_hwaccel_put_tag(skb, vlan_proto, vtag);
	1663	+ } else {
	1664	+ dev_kfree_skb(skb);
	1665	+ return NULL;
	1666	+ }
1462	1667	}
1463	1668
1464	1669	skb_checksum_none_assert(skb);
..	..	@@ -1468,10 +1673,22 @@
1468	1673	(tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1469	1674	}
1470	1675
1471		- if (TPA_END_GRO(tpa_end))
	1676	+ if (gro)
1472	1677	skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
1473	1678
1474	1679	return skb;
	1680	+}
	1681	+
	1682	+static void bnxt_tpa_agg(struct bnxt bp, struct bnxt_rx_ring_info rxr,
	1683	+ struct rx_agg_cmp *rx_agg)
	1684	+{
	1685	+ u16 agg_id = TPA_AGG_AGG_ID(rx_agg);
	1686	+ struct bnxt_tpa_info *tpa_info;
	1687	+
	1688	+ agg_id = bnxt_lookup_agg_idx(rxr, agg_id);
	1689	+ tpa_info = &rxr->rx_tpa[agg_id];
	1690	+ BUG_ON(tpa_info->agg_count >= MAX_SKB_FRAGS);
	1691	+ tpa_info->agg_arr[tpa_info->agg_count++] = *rx_agg;
1475	1692	}
1476	1693
1477	1694	static void bnxt_deliver_skb(struct bnxt bp, struct bnxt_napi bnapi,
..	..	@@ -1493,10 +1710,10 @@
1493	1710	* -ENOMEM - packet aborted due to out of memory
1494	1711	* -EIO - packet aborted due to hw error indicated in BD
1495	1712	*/
1496		-static int bnxt_rx_pkt(struct bnxt bp, struct bnxt_napi bnapi, u32 *raw_cons,
1497		- u8 *event)
	1713	+static int bnxt_rx_pkt(struct bnxt bp, struct bnxt_cp_ring_info cpr,
	1714	+ u32 raw_cons, u8 event)
1498	1715	{
1499		- struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
	1716	+ struct bnxt_napi *bnapi = cpr->bnapi;
1500	1717	struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1501	1718	struct net_device *dev = bp->dev;
1502	1719	struct rx_cmp *rxcmp;
..	..	@@ -1515,6 +1732,13 @@
1515	1732	rxcmp = (struct rx_cmp *)
1516	1733	&cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1517	1734
	1735	+ cmp_type = RX_CMP_TYPE(rxcmp);
	1736	+
	1737	+ if (cmp_type == CMP_TYPE_RX_TPA_AGG_CMP) {
	1738	+ bnxt_tpa_agg(bp, rxr, (struct rx_agg_cmp *)rxcmp);
	1739	+ goto next_rx_no_prod_no_len;
	1740	+ }
	1741	+
1518	1742	tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1519	1743	cp_cons = RING_CMP(tmp_raw_cons);
1520	1744	rxcmp1 = (struct rx_cmp_ext *)
..	..	@@ -1523,8 +1747,10 @@
1523	1747	if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1524	1748	return -EBUSY;
1525	1749
1526		- cmp_type = RX_CMP_TYPE(rxcmp);
1527		-
	1750	+ /* The valid test of the entry must be done first before
	1751	+ * reading any further.
	1752	+ */
	1753	+ dma_rmb();
1528	1754	prod = rxr->rx_prod;
1529	1755
1530	1756	if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
..	..	@@ -1535,7 +1761,7 @@
1535	1761	goto next_rx_no_prod_no_len;
1536	1762
1537	1763	} else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1538		- skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
	1764	+ skb = bnxt_tpa_end(bp, cpr, &tmp_raw_cons,
1539	1765	(struct rx_tpa_end_cmp *)rxcmp,
1540	1766	(struct rx_tpa_end_cmp_ext *)rxcmp1, event);
1541	1767
..	..	@@ -1553,12 +1779,16 @@
1553	1779
1554	1780	cons = rxcmp->rx_cmp_opaque;
1555	1781	if (unlikely(cons != rxr->rx_next_cons)) {
1556		- int rc1 = bnxt_discard_rx(bp, bnapi, raw_cons, rxcmp);
	1782	+ int rc1 = bnxt_discard_rx(bp, cpr, &tmp_raw_cons, rxcmp);
1557	1783
1558		- netdev_warn(bp->dev, "RX cons %x != expected cons %x\n",
1559		- cons, rxr->rx_next_cons);
	1784	+ /* 0xffff is forced error, don't print it */
	1785	+ if (rxr->rx_next_cons != 0xffff)
	1786	+ netdev_warn(bp->dev, "RX cons %x != expected cons %x\n",
	1787	+ cons, rxr->rx_next_cons);
1560	1788	bnxt_sched_reset(bp, rxr);
1561		- return rc1;
	1789	+ if (rc1)
	1790	+ return rc1;
	1791	+ goto next_rx_no_prod_no_len;
1562	1792	}
1563	1793	rx_buf = &rxr->rx_buf_ring[cons];
1564	1794	data = rx_buf->data;
..	..	@@ -1583,12 +1813,18 @@
1583	1813
1584	1814	bnxt_reuse_rx_data(rxr, cons, data);
1585	1815	if (agg_bufs)
1586		- bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
	1816	+ bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0, agg_bufs,
	1817	+ false);
1587	1818
1588	1819	rc = -EIO;
1589	1820	if (rx_err & RX_CMPL_ERRORS_BUFFER_ERROR_MASK) {
1590		- netdev_warn(bp->dev, "RX buffer error %x\n", rx_err);
1591		- bnxt_sched_reset(bp, rxr);
	1821	+ bnapi->cp_ring.sw_stats.rx.rx_buf_errors++;
	1822	+ if (!(bp->flags & BNXT_FLAG_CHIP_P5) &&
	1823	+ !(bp->fw_cap & BNXT_FW_CAP_RING_MONITOR)) {
	1824	+ netdev_warn_once(bp->dev, "RX buffer error %x\n",
	1825	+ rx_err);
	1826	+ bnxt_sched_reset(bp, rxr);
	1827	+ }
1592	1828	}
1593	1829	goto next_rx_no_len;
1594	1830	}
..	..	@@ -1606,7 +1842,8 @@
1606	1842	bnxt_reuse_rx_data(rxr, cons, data);
1607	1843	if (!skb) {
1608	1844	if (agg_bufs)
1609		- bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
	1845	+ bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0,
	1846	+ agg_bufs, false);
1610	1847	rc = -ENOMEM;
1611	1848	goto next_rx;
1612	1849	}
..	..	@@ -1626,7 +1863,7 @@
1626	1863	}
1627	1864
1628	1865	if (agg_bufs) {
1629		- skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
	1866	+ skb = bnxt_rx_pages(bp, cpr, skb, cp_cons, agg_bufs, false);
1630	1867	if (!skb) {
1631	1868	rc = -ENOMEM;
1632	1869	goto next_rx;
..	..	@@ -1648,12 +1885,18 @@
1648	1885
1649	1886	if ((rxcmp1->rx_cmp_flags2 &
1650	1887	cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1651		- (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
	1888	+ (skb->dev->features & BNXT_HW_FEATURE_VLAN_ALL_RX)) {
1652	1889	u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1653	1890	u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1654		- u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
	1891	+ __be16 vlan_proto = htons(meta_data >>
	1892	+ RX_CMP_FLAGS2_METADATA_TPID_SFT);
1655	1893
1656		- __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
	1894	+ if (eth_type_vlan(vlan_proto)) {
	1895	+ __vlan_hwaccel_put_tag(skb, vlan_proto, vtag);
	1896	+ } else {
	1897	+ dev_kfree_skb(skb);
	1898	+ goto next_rx;
	1899	+ }
1657	1900	}
1658	1901
1659	1902	skb_checksum_none_assert(skb);
..	..	@@ -1665,7 +1908,7 @@
1665	1908	} else {
1666	1909	if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1667	1910	if (dev->features & NETIF_F_RXCSUM)
1668		- cpr->rx_l4_csum_errors++;
	1911	+ bnapi->cp_ring.sw_stats.rx.rx_l4_csum_errors++;
1669	1912	}
1670	1913	}
1671	1914
..	..	@@ -1689,10 +1932,10 @@
1689	1932	/* In netpoll mode, if we are using a combined completion ring, we need to
1690	1933	* discard the rx packets and recycle the buffers.
1691	1934	*/
1692		-static int bnxt_force_rx_discard(struct bnxt bp, struct bnxt_napi bnapi,
	1935	+static int bnxt_force_rx_discard(struct bnxt *bp,
	1936	+ struct bnxt_cp_ring_info *cpr,
1693	1937	u32 raw_cons, u8 event)
1694	1938	{
1695		- struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1696	1939	u32 tmp_raw_cons = *raw_cons;
1697	1940	struct rx_cmp_ext *rxcmp1;
1698	1941	struct rx_cmp *rxcmp;
..	..	@@ -1711,6 +1954,10 @@
1711	1954	if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1712	1955	return -EBUSY;
1713	1956
	1957	+ /* The valid test of the entry must be done first before
	1958	+ * reading any further.
	1959	+ */
	1960	+ dma_rmb();
1714	1961	cmp_type = RX_CMP_TYPE(rxcmp);
1715	1962	if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1716	1963	rxcmp1->rx_cmp_cfa_code_errors_v2 \|=
..	..	@@ -1722,22 +1969,73 @@
1722	1969	tpa_end1->rx_tpa_end_cmp_errors_v2 \|=
1723	1970	cpu_to_le32(RX_TPA_END_CMP_ERRORS);
1724	1971	}
1725		- return bnxt_rx_pkt(bp, bnapi, raw_cons, event);
	1972	+ return bnxt_rx_pkt(bp, cpr, raw_cons, event);
	1973	+}
	1974	+
	1975	+u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx)
	1976	+{
	1977	+ struct bnxt_fw_health *fw_health = bp->fw_health;
	1978	+ u32 reg = fw_health->regs[reg_idx];
	1979	+ u32 reg_type, reg_off, val = 0;
	1980	+
	1981	+ reg_type = BNXT_FW_HEALTH_REG_TYPE(reg);
	1982	+ reg_off = BNXT_FW_HEALTH_REG_OFF(reg);
	1983	+ switch (reg_type) {
	1984	+ case BNXT_FW_HEALTH_REG_TYPE_CFG:
	1985	+ pci_read_config_dword(bp->pdev, reg_off, &val);
	1986	+ break;
	1987	+ case BNXT_FW_HEALTH_REG_TYPE_GRC:
	1988	+ reg_off = fw_health->mapped_regs[reg_idx];
	1989	+ fallthrough;
	1990	+ case BNXT_FW_HEALTH_REG_TYPE_BAR0:
	1991	+ val = readl(bp->bar0 + reg_off);
	1992	+ break;
	1993	+ case BNXT_FW_HEALTH_REG_TYPE_BAR1:
	1994	+ val = readl(bp->bar1 + reg_off);
	1995	+ break;
	1996	+ }
	1997	+ if (reg_idx == BNXT_FW_RESET_INPROG_REG)
	1998	+ val &= fw_health->fw_reset_inprog_reg_mask;
	1999	+ return val;
	2000	+}
	2001	+
	2002	+static u16 bnxt_agg_ring_id_to_grp_idx(struct bnxt *bp, u16 ring_id)
	2003	+{
	2004	+ int i;
	2005	+
	2006	+ for (i = 0; i < bp->rx_nr_rings; i++) {
	2007	+ u16 grp_idx = bp->rx_ring[i].bnapi->index;
	2008	+ struct bnxt_ring_grp_info *grp_info;
	2009	+
	2010	+ grp_info = &bp->grp_info[grp_idx];
	2011	+ if (grp_info->agg_fw_ring_id == ring_id)
	2012	+ return grp_idx;
	2013	+ }
	2014	+ return INVALID_HW_RING_ID;
1726	2015	}
1727	2016
1728	2017	#define BNXT_GET_EVENT_PORT(data) \
1729	2018	((data) & \
1730	2019	ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1731	2020
	2021	+#define BNXT_EVENT_RING_TYPE(data2) \
	2022	+ ((data2) & \
	2023	+ ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK)
	2024	+
	2025	+#define BNXT_EVENT_RING_TYPE_RX(data2) \
	2026	+ (BNXT_EVENT_RING_TYPE(data2) == \
	2027	+ ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX)
	2028	+
1732	2029	static int bnxt_async_event_process(struct bnxt *bp,
1733	2030	struct hwrm_async_event_cmpl *cmpl)
1734	2031	{
1735	2032	u16 event_id = le16_to_cpu(cmpl->event_id);
	2033	+ u32 data1 = le32_to_cpu(cmpl->event_data1);
	2034	+ u32 data2 = le32_to_cpu(cmpl->event_data2);
1736	2035
1737	2036	/* TODO CHIMP_FW: Define event id's for link change, error etc */
1738	2037	switch (event_id) {
1739	2038	case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
1740		- u32 data1 = le32_to_cpu(cmpl->event_data1);
1741	2039	struct bnxt_link_info *link_info = &bp->link_info;
1742	2040
1743	2041	if (BNXT_VF(bp))
..	..	@@ -1755,7 +2053,11 @@
1755	2053	}
1756	2054	set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
1757	2055	}
1758		- /* fall through */
	2056	+ fallthrough;
	2057	+ case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE:
	2058	+ case ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE:
	2059	+ set_bit(BNXT_LINK_CFG_CHANGE_SP_EVENT, &bp->sp_event);
	2060	+ fallthrough;
1759	2061	case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1760	2062	set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1761	2063	break;
..	..	@@ -1763,7 +2065,6 @@
1763	2065	set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
1764	2066	break;
1765	2067	case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
1766		- u32 data1 = le32_to_cpu(cmpl->event_data1);
1767	2068	u16 port_id = BNXT_GET_EVENT_PORT(data1);
1768	2069
1769	2070	if (BNXT_VF(bp))
..	..	@@ -1780,6 +2081,93 @@
1780	2081	goto async_event_process_exit;
1781	2082	set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
1782	2083	break;
	2084	+ case ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY: {
	2085	+ char *fatal_str = "non-fatal";
	2086	+
	2087	+ if (!bp->fw_health)
	2088	+ goto async_event_process_exit;
	2089	+
	2090	+ bp->fw_reset_timestamp = jiffies;
	2091	+ bp->fw_reset_min_dsecs = cmpl->timestamp_lo;
	2092	+ if (!bp->fw_reset_min_dsecs)
	2093	+ bp->fw_reset_min_dsecs = BNXT_DFLT_FW_RST_MIN_DSECS;
	2094	+ bp->fw_reset_max_dsecs = le16_to_cpu(cmpl->timestamp_hi);
	2095	+ if (!bp->fw_reset_max_dsecs)
	2096	+ bp->fw_reset_max_dsecs = BNXT_DFLT_FW_RST_MAX_DSECS;
	2097	+ if (EVENT_DATA1_RESET_NOTIFY_FATAL(data1)) {
	2098	+ fatal_str = "fatal";
	2099	+ set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state);
	2100	+ }
	2101	+ netif_warn(bp, hw, bp->dev,
	2102	+ "Firmware %s reset event, data1: 0x%x, data2: 0x%x, min wait %u ms, max wait %u ms\n",
	2103	+ fatal_str, data1, data2,
	2104	+ bp->fw_reset_min_dsecs * 100,
	2105	+ bp->fw_reset_max_dsecs * 100);
	2106	+ set_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event);
	2107	+ break;
	2108	+ }
	2109	+ case ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY: {
	2110	+ struct bnxt_fw_health *fw_health = bp->fw_health;
	2111	+
	2112	+ if (!fw_health)
	2113	+ goto async_event_process_exit;
	2114	+
	2115	+ if (!EVENT_DATA1_RECOVERY_ENABLED(data1)) {
	2116	+ fw_health->enabled = false;
	2117	+ netif_info(bp, drv, bp->dev,
	2118	+ "Error recovery info: error recovery[0]\n");
	2119	+ break;
	2120	+ }
	2121	+ fw_health->master = EVENT_DATA1_RECOVERY_MASTER_FUNC(data1);
	2122	+ fw_health->tmr_multiplier =
	2123	+ DIV_ROUND_UP(fw_health->polling_dsecs * HZ,
	2124	+ bp->current_interval * 10);
	2125	+ fw_health->tmr_counter = fw_health->tmr_multiplier;
	2126	+ if (!fw_health->enabled)
	2127	+ fw_health->last_fw_heartbeat =
	2128	+ bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG);
	2129	+ fw_health->last_fw_reset_cnt =
	2130	+ bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG);
	2131	+ netif_info(bp, drv, bp->dev,
	2132	+ "Error recovery info: error recovery[1], master[%d], reset count[%u], health status: 0x%x\n",
	2133	+ fw_health->master, fw_health->last_fw_reset_cnt,
	2134	+ bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG));
	2135	+ if (!fw_health->enabled) {
	2136	+ /* Make sure tmr_counter is set and visible to
	2137	+ * bnxt_health_check() before setting enabled to true.
	2138	+ */
	2139	+ smp_wmb();
	2140	+ fw_health->enabled = true;
	2141	+ }
	2142	+ goto async_event_process_exit;
	2143	+ }
	2144	+ case ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION:
	2145	+ netif_notice(bp, hw, bp->dev,
	2146	+ "Received firmware debug notification, data1: 0x%x, data2: 0x%x\n",
	2147	+ data1, data2);
	2148	+ goto async_event_process_exit;
	2149	+ case ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG: {
	2150	+ struct bnxt_rx_ring_info *rxr;
	2151	+ u16 grp_idx;
	2152	+
	2153	+ if (bp->flags & BNXT_FLAG_CHIP_P5)
	2154	+ goto async_event_process_exit;
	2155	+
	2156	+ netdev_warn(bp->dev, "Ring monitor event, ring type %lu id 0x%x\n",
	2157	+ BNXT_EVENT_RING_TYPE(data2), data1);
	2158	+ if (!BNXT_EVENT_RING_TYPE_RX(data2))
	2159	+ goto async_event_process_exit;
	2160	+
	2161	+ grp_idx = bnxt_agg_ring_id_to_grp_idx(bp, data1);
	2162	+ if (grp_idx == INVALID_HW_RING_ID) {
	2163	+ netdev_warn(bp->dev, "Unknown RX agg ring id 0x%x\n",
	2164	+ data1);
	2165	+ goto async_event_process_exit;
	2166	+ }
	2167	+ rxr = bp->bnapi[grp_idx]->rx_ring;
	2168	+ bnxt_sched_reset(bp, rxr);
	2169	+ goto async_event_process_exit;
	2170	+ }
1783	2171	default:
1784	2172	goto async_event_process_exit;
1785	2173	}
..	..	@@ -1800,7 +2188,7 @@
1800	2188	case CMPL_BASE_TYPE_HWRM_DONE:
1801	2189	seq_id = le16_to_cpu(h_cmpl->sequence_id);
1802	2190	if (seq_id == bp->hwrm_intr_seq_id)
1803		- bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
	2191	+ bp->hwrm_intr_seq_id = (u16)~bp->hwrm_intr_seq_id;
1804	2192	else
1805	2193	netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1806	2194	break;
..	..	@@ -1873,7 +2261,7 @@
1873	2261	}
1874	2262
1875	2263	/* disable ring IRQ */
1876		- BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
	2264	+ BNXT_CP_DB_IRQ_DIS(cpr->cp_db.doorbell);
1877	2265
1878	2266	/* Return here if interrupt is shared and is disabled. */
1879	2267	if (unlikely(atomic_read(&bp->intr_sem) != 0))
..	..	@@ -1883,9 +2271,10 @@
1883	2271	return IRQ_HANDLED;
1884	2272	}
1885	2273
1886		-static int bnxt_poll_work(struct bnxt bp, struct bnxt_napi bnapi, int budget)
	2274	+static int __bnxt_poll_work(struct bnxt bp, struct bnxt_cp_ring_info cpr,
	2275	+ int budget)
1887	2276	{
1888		- struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
	2277	+ struct bnxt_napi *bnapi = cpr->bnapi;
1889	2278	u32 raw_cons = cpr->cp_raw_cons;
1890	2279	u32 cons;
1891	2280	int tx_pkts = 0;
..	..	@@ -1893,6 +2282,8 @@
1893	2282	u8 event = 0;
1894	2283	struct tx_cmp *txcmp;
1895	2284
	2285	+ cpr->has_more_work = 0;
	2286	+ cpr->had_work_done = 1;
1896	2287	while (1) {
1897	2288	int rc;
1898	2289
..	..	@@ -1912,13 +2303,15 @@
1912	2303	if (unlikely(tx_pkts >= bp->tx_wake_thresh)) {
1913	2304	rx_pkts = budget;
1914	2305	raw_cons = NEXT_RAW_CMP(raw_cons);
	2306	+ if (budget)
	2307	+ cpr->has_more_work = 1;
1915	2308	break;
1916	2309	}
1917	2310	} else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1918	2311	if (likely(budget))
1919		- rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event);
	2312	+ rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event);
1920	2313	else
1921		- rc = bnxt_force_rx_discard(bp, bnapi, &raw_cons,
	2314	+ rc = bnxt_force_rx_discard(bp, cpr, &raw_cons,
1922	2315	&event);
1923	2316	if (likely(rc >= 0))
1924	2317	rx_pkts += rc;
..	..	@@ -1941,39 +2334,63 @@
1941	2334	}
1942	2335	raw_cons = NEXT_RAW_CMP(raw_cons);
1943	2336
1944		- if (rx_pkts && rx_pkts == budget)
	2337	+ if (rx_pkts && rx_pkts == budget) {
	2338	+ cpr->has_more_work = 1;
1945	2339	break;
	2340	+ }
1946	2341	}
	2342	+
	2343	+ if (event & BNXT_REDIRECT_EVENT)
	2344	+ xdp_do_flush_map();
1947	2345
1948	2346	if (event & BNXT_TX_EVENT) {
1949	2347	struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
1950		- void __iomem *db = txr->tx_doorbell;
1951	2348	u16 prod = txr->tx_prod;
1952	2349
1953	2350	/* Sync BD data before updating doorbell */
1954	2351	wmb();
1955	2352
1956		- bnxt_db_write_relaxed(bp, db, DB_KEY_TX \| prod);
	2353	+ bnxt_db_write_relaxed(bp, &txr->tx_db, prod);
1957	2354	}
1958	2355
1959	2356	cpr->cp_raw_cons = raw_cons;
	2357	+ bnapi->tx_pkts += tx_pkts;
	2358	+ bnapi->events \|= event;
	2359	+ return rx_pkts;
	2360	+}
	2361	+
	2362	+static void __bnxt_poll_work_done(struct bnxt bp, struct bnxt_napi bnapi)
	2363	+{
	2364	+ if (bnapi->tx_pkts) {
	2365	+ bnapi->tx_int(bp, bnapi, bnapi->tx_pkts);
	2366	+ bnapi->tx_pkts = 0;
	2367	+ }
	2368	+
	2369	+ if ((bnapi->events & BNXT_RX_EVENT) && !(bnapi->in_reset)) {
	2370	+ struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
	2371	+
	2372	+ if (bnapi->events & BNXT_AGG_EVENT)
	2373	+ bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
	2374	+ bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
	2375	+ }
	2376	+ bnapi->events = 0;
	2377	+}
	2378	+
	2379	+static int bnxt_poll_work(struct bnxt bp, struct bnxt_cp_ring_info cpr,
	2380	+ int budget)
	2381	+{
	2382	+ struct bnxt_napi *bnapi = cpr->bnapi;
	2383	+ int rx_pkts;
	2384	+
	2385	+ rx_pkts = __bnxt_poll_work(bp, cpr, budget);
	2386	+
1960	2387	/* ACK completion ring before freeing tx ring and producing new
1961	2388	* buffers in rx/agg rings to prevent overflowing the completion
1962	2389	* ring.
1963	2390	*/
1964		- BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
	2391	+ bnxt_db_cq(bp, &cpr->cp_db, cpr->cp_raw_cons);
1965	2392
1966		- if (tx_pkts)
1967		- bnapi->tx_int(bp, bnapi, tx_pkts);
1968		-
1969		- if (event & BNXT_RX_EVENT) {
1970		- struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1971		-
1972		- bnxt_db_write(bp, rxr->rx_doorbell, DB_KEY_RX \| rxr->rx_prod);
1973		- if (event & BNXT_AGG_EVENT)
1974		- bnxt_db_write(bp, rxr->rx_agg_doorbell,
1975		- DB_KEY_RX \| rxr->rx_agg_prod);
1976		- }
	2393	+ __bnxt_poll_work_done(bp, bnapi);
1977	2394	return rx_pkts;
1978	2395	}
1979	2396
..	..	@@ -1999,6 +2416,10 @@
1999	2416	if (!TX_CMP_VALID(txcmp, raw_cons))
2000	2417	break;
2001	2418
	2419	+ /* The valid test of the entry must be done first before
	2420	+ * reading any further.
	2421	+ */
	2422	+ dma_rmb();
2002	2423	if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
2003	2424	tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
2004	2425	cp_cons = RING_CMP(tmp_raw_cons);
..	..	@@ -2012,7 +2433,7 @@
2012	2433	rxcmp1->rx_cmp_cfa_code_errors_v2 \|=
2013	2434	cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
2014	2435
2015		- rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event);
	2436	+ rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event);
2016	2437	if (likely(rc == -EIO) && budget)
2017	2438	rx_pkts++;
2018	2439	else if (rc == -EBUSY) /* partial completion */
..	..	@@ -2031,16 +2452,15 @@
2031	2452	}
2032	2453
2033	2454	cpr->cp_raw_cons = raw_cons;
2034		- BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
2035		- bnxt_db_write(bp, rxr->rx_doorbell, DB_KEY_RX \| rxr->rx_prod);
	2455	+ BNXT_DB_CQ(&cpr->cp_db, cpr->cp_raw_cons);
	2456	+ bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
2036	2457
2037	2458	if (event & BNXT_AGG_EVENT)
2038		- bnxt_db_write(bp, rxr->rx_agg_doorbell,
2039		- DB_KEY_RX \| rxr->rx_agg_prod);
	2459	+ bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
2040	2460
2041	2461	if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
2042	2462	napi_complete_done(napi, rx_pkts);
2043		- BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
	2463	+ BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2044	2464	}
2045	2465	return rx_pkts;
2046	2466	}
..	..	@@ -2053,32 +2473,126 @@
2053	2473	int work_done = 0;
2054	2474
2055	2475	while (1) {
2056		- work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
	2476	+ work_done += bnxt_poll_work(bp, cpr, budget - work_done);
2057	2477
2058	2478	if (work_done >= budget) {
2059	2479	if (!budget)
2060		- BNXT_CP_DB_REARM(cpr->cp_doorbell,
2061		- cpr->cp_raw_cons);
	2480	+ BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2062	2481	break;
2063	2482	}
2064	2483
2065	2484	if (!bnxt_has_work(bp, cpr)) {
2066	2485	if (napi_complete_done(napi, work_done))
2067		- BNXT_CP_DB_REARM(cpr->cp_doorbell,
2068		- cpr->cp_raw_cons);
	2486	+ BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2069	2487	break;
2070	2488	}
2071	2489	}
2072	2490	if (bp->flags & BNXT_FLAG_DIM) {
2073		- struct net_dim_sample dim_sample;
	2491	+ struct dim_sample dim_sample = {};
2074	2492
2075		- net_dim_sample(cpr->event_ctr,
2076		- cpr->rx_packets,
2077		- cpr->rx_bytes,
2078		- &dim_sample);
	2493	+ dim_update_sample(cpr->event_ctr,
	2494	+ cpr->rx_packets,
	2495	+ cpr->rx_bytes,
	2496	+ &dim_sample);
2079	2497	net_dim(&cpr->dim, dim_sample);
2080	2498	}
2081		- mmiowb();
	2499	+ return work_done;
	2500	+}
	2501	+
	2502	+static int __bnxt_poll_cqs(struct bnxt bp, struct bnxt_napi bnapi, int budget)
	2503	+{
	2504	+ struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
	2505	+ int i, work_done = 0;
	2506	+
	2507	+ for (i = 0; i < 2; i++) {
	2508	+ struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i];
	2509	+
	2510	+ if (cpr2) {
	2511	+ work_done += __bnxt_poll_work(bp, cpr2,
	2512	+ budget - work_done);
	2513	+ cpr->has_more_work \|= cpr2->has_more_work;
	2514	+ }
	2515	+ }
	2516	+ return work_done;
	2517	+}
	2518	+
	2519	+static void __bnxt_poll_cqs_done(struct bnxt bp, struct bnxt_napi bnapi,
	2520	+ u64 dbr_type)
	2521	+{
	2522	+ struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
	2523	+ int i;
	2524	+
	2525	+ for (i = 0; i < 2; i++) {
	2526	+ struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i];
	2527	+ struct bnxt_db_info *db;
	2528	+
	2529	+ if (cpr2 && cpr2->had_work_done) {
	2530	+ db = &cpr2->cp_db;
	2531	+ writeq(db->db_key64 \| dbr_type \|
	2532	+ RING_CMP(cpr2->cp_raw_cons), db->doorbell);
	2533	+ cpr2->had_work_done = 0;
	2534	+ }
	2535	+ }
	2536	+ __bnxt_poll_work_done(bp, bnapi);
	2537	+}
	2538	+
	2539	+static int bnxt_poll_p5(struct napi_struct *napi, int budget)
	2540	+{
	2541	+ struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
	2542	+ struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
	2543	+ u32 raw_cons = cpr->cp_raw_cons;
	2544	+ struct bnxt *bp = bnapi->bp;
	2545	+ struct nqe_cn *nqcmp;
	2546	+ int work_done = 0;
	2547	+ u32 cons;
	2548	+
	2549	+ if (cpr->has_more_work) {
	2550	+ cpr->has_more_work = 0;
	2551	+ work_done = __bnxt_poll_cqs(bp, bnapi, budget);
	2552	+ }
	2553	+ while (1) {
	2554	+ cons = RING_CMP(raw_cons);
	2555	+ nqcmp = &cpr->nq_desc_ring[CP_RING(cons)][CP_IDX(cons)];
	2556	+
	2557	+ if (!NQ_CMP_VALID(nqcmp, raw_cons)) {
	2558	+ if (cpr->has_more_work)
	2559	+ break;
	2560	+
	2561	+ __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL);
	2562	+ cpr->cp_raw_cons = raw_cons;
	2563	+ if (napi_complete_done(napi, work_done))
	2564	+ BNXT_DB_NQ_ARM_P5(&cpr->cp_db,
	2565	+ cpr->cp_raw_cons);
	2566	+ return work_done;
	2567	+ }
	2568	+
	2569	+ /* The valid test of the entry must be done first before
	2570	+ * reading any further.
	2571	+ */
	2572	+ dma_rmb();
	2573	+
	2574	+ if (nqcmp->type == cpu_to_le16(NQ_CN_TYPE_CQ_NOTIFICATION)) {
	2575	+ u32 idx = le32_to_cpu(nqcmp->cq_handle_low);
	2576	+ struct bnxt_cp_ring_info *cpr2;
	2577	+
	2578	+ /* No more budget for RX work */
	2579	+ if (budget && work_done >= budget && idx == BNXT_RX_HDL)
	2580	+ break;
	2581	+
	2582	+ cpr2 = cpr->cp_ring_arr[idx];
	2583	+ work_done += __bnxt_poll_work(bp, cpr2,
	2584	+ budget - work_done);
	2585	+ cpr->has_more_work \|= cpr2->has_more_work;
	2586	+ } else {
	2587	+ bnxt_hwrm_handler(bp, (struct tx_cmp *)nqcmp);
	2588	+ }
	2589	+ raw_cons = NEXT_RAW_CMP(raw_cons);
	2590	+ }
	2591	+ __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ);
	2592	+ if (raw_cons != cpr->cp_raw_cons) {
	2593	+ cpr->cp_raw_cons = raw_cons;
	2594	+ BNXT_DB_NQ_P5(&cpr->cp_db, raw_cons);
	2595	+ }
2082	2596	return work_done;
2083	2597	}
2084	2598
..	..	@@ -2095,11 +2609,28 @@
2095	2609	struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2096	2610	int j;
2097	2611
	2612	+ if (!txr->tx_buf_ring)
	2613	+ continue;
	2614	+
2098	2615	for (j = 0; j < max_idx;) {
2099	2616	struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
2100		- struct sk_buff *skb = tx_buf->skb;
	2617	+ struct sk_buff *skb;
2101	2618	int k, last;
2102	2619
	2620	+ if (i < bp->tx_nr_rings_xdp &&
	2621	+ tx_buf->action == XDP_REDIRECT) {
	2622	+ dma_unmap_single(&pdev->dev,
	2623	+ dma_unmap_addr(tx_buf, mapping),
	2624	+ dma_unmap_len(tx_buf, len),
	2625	+ PCI_DMA_TODEVICE);
	2626	+ xdp_return_frame(tx_buf->xdpf);
	2627	+ tx_buf->action = 0;
	2628	+ tx_buf->xdpf = NULL;
	2629	+ j++;
	2630	+ continue;
	2631	+ }
	2632	+
	2633	+ skb = tx_buf->skb;
2103	2634	if (!skb) {
2104	2635	j++;
2105	2636	continue;
..	..	@@ -2136,89 +2667,101 @@
2136	2667	}
2137	2668	}
2138	2669
	2670	+static void bnxt_free_one_rx_ring_skbs(struct bnxt *bp, int ring_nr)
	2671	+{
	2672	+ struct bnxt_rx_ring_info *rxr = &bp->rx_ring[ring_nr];
	2673	+ struct pci_dev *pdev = bp->pdev;
	2674	+ struct bnxt_tpa_idx_map *map;
	2675	+ int i, max_idx, max_agg_idx;
	2676	+
	2677	+ max_idx = bp->rx_nr_pages * RX_DESC_CNT;
	2678	+ max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
	2679	+ if (!rxr->rx_tpa)
	2680	+ goto skip_rx_tpa_free;
	2681	+
	2682	+ for (i = 0; i < bp->max_tpa; i++) {
	2683	+ struct bnxt_tpa_info *tpa_info = &rxr->rx_tpa[i];
	2684	+ u8 *data = tpa_info->data;
	2685	+
	2686	+ if (!data)
	2687	+ continue;
	2688	+
	2689	+ dma_unmap_single_attrs(&pdev->dev, tpa_info->mapping,
	2690	+ bp->rx_buf_use_size, bp->rx_dir,
	2691	+ DMA_ATTR_WEAK_ORDERING);
	2692	+
	2693	+ tpa_info->data = NULL;
	2694	+
	2695	+ kfree(data);
	2696	+ }
	2697	+
	2698	+skip_rx_tpa_free:
	2699	+ if (!rxr->rx_buf_ring)
	2700	+ goto skip_rx_buf_free;
	2701	+
	2702	+ for (i = 0; i < max_idx; i++) {
	2703	+ struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[i];
	2704	+ dma_addr_t mapping = rx_buf->mapping;
	2705	+ void *data = rx_buf->data;
	2706	+
	2707	+ if (!data)
	2708	+ continue;
	2709	+
	2710	+ rx_buf->data = NULL;
	2711	+ if (BNXT_RX_PAGE_MODE(bp)) {
	2712	+ mapping -= bp->rx_dma_offset;
	2713	+ dma_unmap_page_attrs(&pdev->dev, mapping, PAGE_SIZE,
	2714	+ bp->rx_dir,
	2715	+ DMA_ATTR_WEAK_ORDERING);
	2716	+ page_pool_recycle_direct(rxr->page_pool, data);
	2717	+ } else {
	2718	+ dma_unmap_single_attrs(&pdev->dev, mapping,
	2719	+ bp->rx_buf_use_size, bp->rx_dir,
	2720	+ DMA_ATTR_WEAK_ORDERING);
	2721	+ kfree(data);
	2722	+ }
	2723	+ }
	2724	+
	2725	+skip_rx_buf_free:
	2726	+ if (!rxr->rx_agg_ring)
	2727	+ goto skip_rx_agg_free;
	2728	+
	2729	+ for (i = 0; i < max_agg_idx; i++) {
	2730	+ struct bnxt_sw_rx_agg_bd *rx_agg_buf = &rxr->rx_agg_ring[i];
	2731	+ struct page *page = rx_agg_buf->page;
	2732	+
	2733	+ if (!page)
	2734	+ continue;
	2735	+
	2736	+ dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping,
	2737	+ BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE,
	2738	+ DMA_ATTR_WEAK_ORDERING);
	2739	+
	2740	+ rx_agg_buf->page = NULL;
	2741	+ __clear_bit(i, rxr->rx_agg_bmap);
	2742	+
	2743	+ __free_page(page);
	2744	+ }
	2745	+
	2746	+skip_rx_agg_free:
	2747	+ if (rxr->rx_page) {
	2748	+ __free_page(rxr->rx_page);
	2749	+ rxr->rx_page = NULL;
	2750	+ }
	2751	+ map = rxr->rx_tpa_idx_map;
	2752	+ if (map)
	2753	+ memset(map->agg_idx_bmap, 0, sizeof(map->agg_idx_bmap));
	2754	+}
	2755	+
2139	2756	static void bnxt_free_rx_skbs(struct bnxt *bp)
2140	2757	{
2141		- int i, max_idx, max_agg_idx;
2142		- struct pci_dev *pdev = bp->pdev;
	2758	+ int i;
2143	2759
2144	2760	if (!bp->rx_ring)
2145	2761	return;
2146	2762
2147		- max_idx = bp->rx_nr_pages * RX_DESC_CNT;
2148		- max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
2149		- for (i = 0; i < bp->rx_nr_rings; i++) {
2150		- struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2151		- int j;
2152		-
2153		- if (rxr->rx_tpa) {
2154		- for (j = 0; j < MAX_TPA; j++) {
2155		- struct bnxt_tpa_info *tpa_info =
2156		- &rxr->rx_tpa[j];
2157		- u8 *data = tpa_info->data;
2158		-
2159		- if (!data)
2160		- continue;
2161		-
2162		- dma_unmap_single_attrs(&pdev->dev,
2163		- tpa_info->mapping,
2164		- bp->rx_buf_use_size,
2165		- bp->rx_dir,
2166		- DMA_ATTR_WEAK_ORDERING);
2167		-
2168		- tpa_info->data = NULL;
2169		-
2170		- kfree(data);
2171		- }
2172		- }
2173		-
2174		- for (j = 0; j < max_idx; j++) {
2175		- struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
2176		- dma_addr_t mapping = rx_buf->mapping;
2177		- void *data = rx_buf->data;
2178		-
2179		- if (!data)
2180		- continue;
2181		-
2182		- rx_buf->data = NULL;
2183		-
2184		- if (BNXT_RX_PAGE_MODE(bp)) {
2185		- mapping -= bp->rx_dma_offset;
2186		- dma_unmap_page_attrs(&pdev->dev, mapping,
2187		- PAGE_SIZE, bp->rx_dir,
2188		- DMA_ATTR_WEAK_ORDERING);
2189		- __free_page(data);
2190		- } else {
2191		- dma_unmap_single_attrs(&pdev->dev, mapping,
2192		- bp->rx_buf_use_size,
2193		- bp->rx_dir,
2194		- DMA_ATTR_WEAK_ORDERING);
2195		- kfree(data);
2196		- }
2197		- }
2198		-
2199		- for (j = 0; j < max_agg_idx; j++) {
2200		- struct bnxt_sw_rx_agg_bd *rx_agg_buf =
2201		- &rxr->rx_agg_ring[j];
2202		- struct page *page = rx_agg_buf->page;
2203		-
2204		- if (!page)
2205		- continue;
2206		-
2207		- dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping,
2208		- BNXT_RX_PAGE_SIZE,
2209		- PCI_DMA_FROMDEVICE,
2210		- DMA_ATTR_WEAK_ORDERING);
2211		-
2212		- rx_agg_buf->page = NULL;
2213		- __clear_bit(j, rxr->rx_agg_bmap);
2214		-
2215		- __free_page(page);
2216		- }
2217		- if (rxr->rx_page) {
2218		- __free_page(rxr->rx_page);
2219		- rxr->rx_page = NULL;
2220		- }
2221		- }
	2763	+ for (i = 0; i < bp->rx_nr_rings; i++)
	2764	+ bnxt_free_one_rx_ring_skbs(bp, i);
2222	2765	}
2223	2766
2224	2767	static void bnxt_free_skbs(struct bnxt *bp)
..	..	@@ -2227,60 +2770,138 @@
2227	2770	bnxt_free_rx_skbs(bp);
2228	2771	}
2229	2772
2230		-static void bnxt_free_ring(struct bnxt bp, struct bnxt_ring_struct ring)
	2773	+static void bnxt_free_ring(struct bnxt bp, struct bnxt_ring_mem_info rmem)
2231	2774	{
2232	2775	struct pci_dev *pdev = bp->pdev;
2233	2776	int i;
2234	2777
2235		- for (i = 0; i < ring->nr_pages; i++) {
2236		- if (!ring->pg_arr[i])
	2778	+ for (i = 0; i < rmem->nr_pages; i++) {
	2779	+ if (!rmem->pg_arr[i])
2237	2780	continue;
2238	2781
2239		- dma_free_coherent(&pdev->dev, ring->page_size,
2240		- ring->pg_arr[i], ring->dma_arr[i]);
	2782	+ dma_free_coherent(&pdev->dev, rmem->page_size,
	2783	+ rmem->pg_arr[i], rmem->dma_arr[i]);
2241	2784
2242		- ring->pg_arr[i] = NULL;
	2785	+ rmem->pg_arr[i] = NULL;
2243	2786	}
2244		- if (ring->pg_tbl) {
2245		- dma_free_coherent(&pdev->dev, ring->nr_pages * 8,
2246		- ring->pg_tbl, ring->pg_tbl_map);
2247		- ring->pg_tbl = NULL;
	2787	+ if (rmem->pg_tbl) {
	2788	+ size_t pg_tbl_size = rmem->nr_pages * 8;
	2789	+
	2790	+ if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG)
	2791	+ pg_tbl_size = rmem->page_size;
	2792	+ dma_free_coherent(&pdev->dev, pg_tbl_size,
	2793	+ rmem->pg_tbl, rmem->pg_tbl_map);
	2794	+ rmem->pg_tbl = NULL;
2248	2795	}
2249		- if (ring->vmem_size && *ring->vmem) {
2250		- vfree(*ring->vmem);
2251		- *ring->vmem = NULL;
	2796	+ if (rmem->vmem_size && *rmem->vmem) {
	2797	+ vfree(*rmem->vmem);
	2798	+ *rmem->vmem = NULL;
2252	2799	}
2253	2800	}
2254	2801
2255		-static int bnxt_alloc_ring(struct bnxt bp, struct bnxt_ring_struct ring)
	2802	+static int bnxt_alloc_ring(struct bnxt bp, struct bnxt_ring_mem_info rmem)
	2803	+{
	2804	+ struct pci_dev *pdev = bp->pdev;
	2805	+ u64 valid_bit = 0;
	2806	+ int i;
	2807	+
	2808	+ if (rmem->flags & (BNXT_RMEM_VALID_PTE_FLAG \| BNXT_RMEM_RING_PTE_FLAG))
	2809	+ valid_bit = PTU_PTE_VALID;
	2810	+ if ((rmem->nr_pages > 1 \|\| rmem->depth > 0) && !rmem->pg_tbl) {
	2811	+ size_t pg_tbl_size = rmem->nr_pages * 8;
	2812	+
	2813	+ if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG)
	2814	+ pg_tbl_size = rmem->page_size;
	2815	+ rmem->pg_tbl = dma_alloc_coherent(&pdev->dev, pg_tbl_size,
	2816	+ &rmem->pg_tbl_map,
	2817	+ GFP_KERNEL);
	2818	+ if (!rmem->pg_tbl)
	2819	+ return -ENOMEM;
	2820	+ }
	2821	+
	2822	+ for (i = 0; i < rmem->nr_pages; i++) {
	2823	+ u64 extra_bits = valid_bit;
	2824	+
	2825	+ rmem->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
	2826	+ rmem->page_size,
	2827	+ &rmem->dma_arr[i],
	2828	+ GFP_KERNEL);
	2829	+ if (!rmem->pg_arr[i])
	2830	+ return -ENOMEM;
	2831	+
	2832	+ if (rmem->init_val)
	2833	+ memset(rmem->pg_arr[i], rmem->init_val,
	2834	+ rmem->page_size);
	2835	+ if (rmem->nr_pages > 1 \|\| rmem->depth > 0) {
	2836	+ if (i == rmem->nr_pages - 2 &&
	2837	+ (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
	2838	+ extra_bits \|= PTU_PTE_NEXT_TO_LAST;
	2839	+ else if (i == rmem->nr_pages - 1 &&
	2840	+ (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
	2841	+ extra_bits \|= PTU_PTE_LAST;
	2842	+ rmem->pg_tbl[i] =
	2843	+ cpu_to_le64(rmem->dma_arr[i] \| extra_bits);
	2844	+ }
	2845	+ }
	2846	+
	2847	+ if (rmem->vmem_size) {
	2848	+ *rmem->vmem = vzalloc(rmem->vmem_size);
	2849	+ if (!(*rmem->vmem))
	2850	+ return -ENOMEM;
	2851	+ }
	2852	+ return 0;
	2853	+}
	2854	+
	2855	+static void bnxt_free_tpa_info(struct bnxt *bp)
2256	2856	{
2257	2857	int i;
2258		- struct pci_dev *pdev = bp->pdev;
2259	2858
2260		- if (ring->nr_pages > 1) {
2261		- ring->pg_tbl = dma_alloc_coherent(&pdev->dev,
2262		- ring->nr_pages * 8,
2263		- &ring->pg_tbl_map,
2264		- GFP_KERNEL);
2265		- if (!ring->pg_tbl)
2266		- return -ENOMEM;
	2859	+ for (i = 0; i < bp->rx_nr_rings; i++) {
	2860	+ struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
	2861	+
	2862	+ kfree(rxr->rx_tpa_idx_map);
	2863	+ rxr->rx_tpa_idx_map = NULL;
	2864	+ if (rxr->rx_tpa) {
	2865	+ kfree(rxr->rx_tpa[0].agg_arr);
	2866	+ rxr->rx_tpa[0].agg_arr = NULL;
	2867	+ }
	2868	+ kfree(rxr->rx_tpa);
	2869	+ rxr->rx_tpa = NULL;
	2870	+ }
	2871	+}
	2872	+
	2873	+static int bnxt_alloc_tpa_info(struct bnxt *bp)
	2874	+{
	2875	+ int i, j, total_aggs = 0;
	2876	+
	2877	+ bp->max_tpa = MAX_TPA;
	2878	+ if (bp->flags & BNXT_FLAG_CHIP_P5) {
	2879	+ if (!bp->max_tpa_v2)
	2880	+ return 0;
	2881	+ bp->max_tpa = max_t(u16, bp->max_tpa_v2, MAX_TPA_P5);
	2882	+ total_aggs = bp->max_tpa * MAX_SKB_FRAGS;
2267	2883	}
2268	2884
2269		- for (i = 0; i < ring->nr_pages; i++) {
2270		- ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
2271		- ring->page_size,
2272		- &ring->dma_arr[i],
2273		- GFP_KERNEL);
2274		- if (!ring->pg_arr[i])
	2885	+ for (i = 0; i < bp->rx_nr_rings; i++) {
	2886	+ struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
	2887	+ struct rx_agg_cmp *agg;
	2888	+
	2889	+ rxr->rx_tpa = kcalloc(bp->max_tpa, sizeof(struct bnxt_tpa_info),
	2890	+ GFP_KERNEL);
	2891	+ if (!rxr->rx_tpa)
2275	2892	return -ENOMEM;
2276	2893
2277		- if (ring->nr_pages > 1)
2278		- ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]);
2279		- }
2280		-
2281		- if (ring->vmem_size) {
2282		- *ring->vmem = vzalloc(ring->vmem_size);
2283		- if (!(*ring->vmem))
	2894	+ if (!(bp->flags & BNXT_FLAG_CHIP_P5))
	2895	+ continue;
	2896	+ agg = kcalloc(total_aggs, sizeof(*agg), GFP_KERNEL);
	2897	+ rxr->rx_tpa[0].agg_arr = agg;
	2898	+ if (!agg)
	2899	+ return -ENOMEM;
	2900	+ for (j = 1; j < bp->max_tpa; j++)
	2901	+ rxr->rx_tpa[j].agg_arr = agg + j * MAX_SKB_FRAGS;
	2902	+ rxr->rx_tpa_idx_map = kzalloc(sizeof(*rxr->rx_tpa_idx_map),
	2903	+ GFP_KERNEL);
	2904	+ if (!rxr->rx_tpa_idx_map)
2284	2905	return -ENOMEM;
2285	2906	}
2286	2907	return 0;
..	..	@@ -2293,6 +2914,7 @@
2293	2914	if (!bp->rx_ring)
2294	2915	return;
2295	2916
	2917	+ bnxt_free_tpa_info(bp);
2296	2918	for (i = 0; i < bp->rx_nr_rings; i++) {
2297	2919	struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2298	2920	struct bnxt_ring_struct *ring;
..	..	@@ -2303,23 +2925,43 @@
2303	2925	if (xdp_rxq_info_is_reg(&rxr->xdp_rxq))
2304	2926	xdp_rxq_info_unreg(&rxr->xdp_rxq);
2305	2927
2306		- kfree(rxr->rx_tpa);
2307		- rxr->rx_tpa = NULL;
	2928	+ page_pool_destroy(rxr->page_pool);
	2929	+ rxr->page_pool = NULL;
2308	2930
2309	2931	kfree(rxr->rx_agg_bmap);
2310	2932	rxr->rx_agg_bmap = NULL;
2311	2933
2312	2934	ring = &rxr->rx_ring_struct;
2313		- bnxt_free_ring(bp, ring);
	2935	+ bnxt_free_ring(bp, &ring->ring_mem);
2314	2936
2315	2937	ring = &rxr->rx_agg_ring_struct;
2316		- bnxt_free_ring(bp, ring);
	2938	+ bnxt_free_ring(bp, &ring->ring_mem);
2317	2939	}
	2940	+}
	2941	+
	2942	+static int bnxt_alloc_rx_page_pool(struct bnxt *bp,
	2943	+ struct bnxt_rx_ring_info *rxr)
	2944	+{
	2945	+ struct page_pool_params pp = { 0 };
	2946	+
	2947	+ pp.pool_size = bp->rx_ring_size;
	2948	+ pp.nid = dev_to_node(&bp->pdev->dev);
	2949	+ pp.dev = &bp->pdev->dev;
	2950	+ pp.dma_dir = DMA_BIDIRECTIONAL;
	2951	+
	2952	+ rxr->page_pool = page_pool_create(&pp);
	2953	+ if (IS_ERR(rxr->page_pool)) {
	2954	+ int err = PTR_ERR(rxr->page_pool);
	2955	+
	2956	+ rxr->page_pool = NULL;
	2957	+ return err;
	2958	+ }
	2959	+ return 0;
2318	2960	}
2319	2961
2320	2962	static int bnxt_alloc_rx_rings(struct bnxt *bp)
2321	2963	{
2322		- int i, rc, agg_rings = 0, tpa_rings = 0;
	2964	+ int i, rc = 0, agg_rings = 0;
2323	2965
2324	2966	if (!bp->rx_ring)
2325	2967	return -ENOMEM;
..	..	@@ -2327,28 +2969,38 @@
2327	2969	if (bp->flags & BNXT_FLAG_AGG_RINGS)
2328	2970	agg_rings = 1;
2329	2971
2330		- if (bp->flags & BNXT_FLAG_TPA)
2331		- tpa_rings = 1;
2332		-
2333	2972	for (i = 0; i < bp->rx_nr_rings; i++) {
2334	2973	struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2335	2974	struct bnxt_ring_struct *ring;
2336	2975
2337	2976	ring = &rxr->rx_ring_struct;
2338	2977
	2978	+ rc = bnxt_alloc_rx_page_pool(bp, rxr);
	2979	+ if (rc)
	2980	+ return rc;
	2981	+
2339	2982	rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i);
2340	2983	if (rc < 0)
2341	2984	return rc;
2342	2985
2343		- rc = bnxt_alloc_ring(bp, ring);
	2986	+ rc = xdp_rxq_info_reg_mem_model(&rxr->xdp_rxq,
	2987	+ MEM_TYPE_PAGE_POOL,
	2988	+ rxr->page_pool);
	2989	+ if (rc) {
	2990	+ xdp_rxq_info_unreg(&rxr->xdp_rxq);
	2991	+ return rc;
	2992	+ }
	2993	+
	2994	+ rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2344	2995	if (rc)
2345	2996	return rc;
2346	2997
	2998	+ ring->grp_idx = i;
2347	2999	if (agg_rings) {
2348	3000	u16 mem_size;
2349	3001
2350	3002	ring = &rxr->rx_agg_ring_struct;
2351		- rc = bnxt_alloc_ring(bp, ring);
	3003	+ rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2352	3004	if (rc)
2353	3005	return rc;
2354	3006
..	..	@@ -2358,17 +3010,11 @@
2358	3010	rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
2359	3011	if (!rxr->rx_agg_bmap)
2360	3012	return -ENOMEM;
2361		-
2362		- if (tpa_rings) {
2363		- rxr->rx_tpa = kcalloc(MAX_TPA,
2364		- sizeof(struct bnxt_tpa_info),
2365		- GFP_KERNEL);
2366		- if (!rxr->rx_tpa)
2367		- return -ENOMEM;
2368		- }
2369	3013	}
2370	3014	}
2371		- return 0;
	3015	+ if (bp->flags & BNXT_FLAG_TPA)
	3016	+ rc = bnxt_alloc_tpa_info(bp);
	3017	+ return rc;
2372	3018	}
2373	3019
2374	3020	static void bnxt_free_tx_rings(struct bnxt *bp)
..	..	@@ -2391,7 +3037,7 @@
2391	3037
2392	3038	ring = &txr->tx_ring_struct;
2393	3039
2394		- bnxt_free_ring(bp, ring);
	3040	+ bnxt_free_ring(bp, &ring->ring_mem);
2395	3041	}
2396	3042	}
2397	3043
..	..	@@ -2422,7 +3068,7 @@
2422	3068
2423	3069	ring = &txr->tx_ring_struct;
2424	3070
2425		- rc = bnxt_alloc_ring(bp, ring);
	3071	+ rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2426	3072	if (rc)
2427	3073	return rc;
2428	3074
..	..	@@ -2444,8 +3090,6 @@
2444	3090	mapping = txr->tx_push_mapping +
2445	3091	sizeof(struct tx_push_bd);
2446	3092	txr->data_mapping = cpu_to_le64(mapping);
2447		-
2448		- memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
2449	3093	}
2450	3094	qidx = bp->tc_to_qidx[j];
2451	3095	ring->queue_id = bp->q_info[qidx].queue_id;
..	..	@@ -2468,6 +3112,7 @@
2468	3112	struct bnxt_napi *bnapi = bp->bnapi[i];
2469	3113	struct bnxt_cp_ring_info *cpr;
2470	3114	struct bnxt_ring_struct *ring;
	3115	+ int j;
2471	3116
2472	3117	if (!bnapi)
2473	3118	continue;
..	..	@@ -2475,12 +3120,51 @@
2475	3120	cpr = &bnapi->cp_ring;
2476	3121	ring = &cpr->cp_ring_struct;
2477	3122
2478		- bnxt_free_ring(bp, ring);
	3123	+ bnxt_free_ring(bp, &ring->ring_mem);
	3124	+
	3125	+ for (j = 0; j < 2; j++) {
	3126	+ struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
	3127	+
	3128	+ if (cpr2) {
	3129	+ ring = &cpr2->cp_ring_struct;
	3130	+ bnxt_free_ring(bp, &ring->ring_mem);
	3131	+ kfree(cpr2);
	3132	+ cpr->cp_ring_arr[j] = NULL;
	3133	+ }
	3134	+ }
2479	3135	}
	3136	+}
	3137	+
	3138	+static struct bnxt_cp_ring_info bnxt_alloc_cp_sub_ring(struct bnxt bp)
	3139	+{
	3140	+ struct bnxt_ring_mem_info *rmem;
	3141	+ struct bnxt_ring_struct *ring;
	3142	+ struct bnxt_cp_ring_info *cpr;
	3143	+ int rc;
	3144	+
	3145	+ cpr = kzalloc(sizeof(*cpr), GFP_KERNEL);
	3146	+ if (!cpr)
	3147	+ return NULL;
	3148	+
	3149	+ ring = &cpr->cp_ring_struct;
	3150	+ rmem = &ring->ring_mem;
	3151	+ rmem->nr_pages = bp->cp_nr_pages;
	3152	+ rmem->page_size = HW_CMPD_RING_SIZE;
	3153	+ rmem->pg_arr = (void **)cpr->cp_desc_ring;
	3154	+ rmem->dma_arr = cpr->cp_desc_mapping;
	3155	+ rmem->flags = BNXT_RMEM_RING_PTE_FLAG;
	3156	+ rc = bnxt_alloc_ring(bp, rmem);
	3157	+ if (rc) {
	3158	+ bnxt_free_ring(bp, rmem);
	3159	+ kfree(cpr);
	3160	+ cpr = NULL;
	3161	+ }
	3162	+ return cpr;
2480	3163	}
2481	3164
2482	3165	static int bnxt_alloc_cp_rings(struct bnxt *bp)
2483	3166	{
	3167	+ bool sh = !!(bp->flags & BNXT_FLAG_SHARED_RINGS);
2484	3168	int i, rc, ulp_base_vec, ulp_msix;
2485	3169
2486	3170	ulp_msix = bnxt_get_ulp_msix_num(bp);
..	..	@@ -2494,9 +3178,10 @@
2494	3178	continue;
2495	3179
2496	3180	cpr = &bnapi->cp_ring;
	3181	+ cpr->bnapi = bnapi;
2497	3182	ring = &cpr->cp_ring_struct;
2498	3183
2499		- rc = bnxt_alloc_ring(bp, ring);
	3184	+ rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2500	3185	if (rc)
2501	3186	return rc;
2502	3187
..	..	@@ -2504,6 +3189,29 @@
2504	3189	ring->map_idx = i + ulp_msix;
2505	3190	else
2506	3191	ring->map_idx = i;
	3192	+
	3193	+ if (!(bp->flags & BNXT_FLAG_CHIP_P5))
	3194	+ continue;
	3195	+
	3196	+ if (i < bp->rx_nr_rings) {
	3197	+ struct bnxt_cp_ring_info *cpr2 =
	3198	+ bnxt_alloc_cp_sub_ring(bp);
	3199	+
	3200	+ cpr->cp_ring_arr[BNXT_RX_HDL] = cpr2;
	3201	+ if (!cpr2)
	3202	+ return -ENOMEM;
	3203	+ cpr2->bnapi = bnapi;
	3204	+ }
	3205	+ if ((sh && i < bp->tx_nr_rings) \|\|
	3206	+ (!sh && i >= bp->rx_nr_rings)) {
	3207	+ struct bnxt_cp_ring_info *cpr2 =
	3208	+ bnxt_alloc_cp_sub_ring(bp);
	3209	+
	3210	+ cpr->cp_ring_arr[BNXT_TX_HDL] = cpr2;
	3211	+ if (!cpr2)
	3212	+ return -ENOMEM;
	3213	+ cpr2->bnapi = bnapi;
	3214	+ }
2507	3215	}
2508	3216	return 0;
2509	3217	}
..	..	@@ -2514,6 +3222,7 @@
2514	3222
2515	3223	for (i = 0; i < bp->cp_nr_rings; i++) {
2516	3224	struct bnxt_napi *bnapi = bp->bnapi[i];
	3225	+ struct bnxt_ring_mem_info *rmem;
2517	3226	struct bnxt_cp_ring_info *cpr;
2518	3227	struct bnxt_rx_ring_info *rxr;
2519	3228	struct bnxt_tx_ring_info *txr;
..	..	@@ -2524,31 +3233,34 @@
2524	3233
2525	3234	cpr = &bnapi->cp_ring;
2526	3235	ring = &cpr->cp_ring_struct;
2527		- ring->nr_pages = bp->cp_nr_pages;
2528		- ring->page_size = HW_CMPD_RING_SIZE;
2529		- ring->pg_arr = (void **)cpr->cp_desc_ring;
2530		- ring->dma_arr = cpr->cp_desc_mapping;
2531		- ring->vmem_size = 0;
	3236	+ rmem = &ring->ring_mem;
	3237	+ rmem->nr_pages = bp->cp_nr_pages;
	3238	+ rmem->page_size = HW_CMPD_RING_SIZE;
	3239	+ rmem->pg_arr = (void **)cpr->cp_desc_ring;
	3240	+ rmem->dma_arr = cpr->cp_desc_mapping;
	3241	+ rmem->vmem_size = 0;
2532	3242
2533	3243	rxr = bnapi->rx_ring;
2534	3244	if (!rxr)
2535	3245	goto skip_rx;
2536	3246
2537	3247	ring = &rxr->rx_ring_struct;
2538		- ring->nr_pages = bp->rx_nr_pages;
2539		- ring->page_size = HW_RXBD_RING_SIZE;
2540		- ring->pg_arr = (void **)rxr->rx_desc_ring;
2541		- ring->dma_arr = rxr->rx_desc_mapping;
2542		- ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
2543		- ring->vmem = (void **)&rxr->rx_buf_ring;
	3248	+ rmem = &ring->ring_mem;
	3249	+ rmem->nr_pages = bp->rx_nr_pages;
	3250	+ rmem->page_size = HW_RXBD_RING_SIZE;
	3251	+ rmem->pg_arr = (void **)rxr->rx_desc_ring;
	3252	+ rmem->dma_arr = rxr->rx_desc_mapping;
	3253	+ rmem->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
	3254	+ rmem->vmem = (void **)&rxr->rx_buf_ring;
2544	3255
2545	3256	ring = &rxr->rx_agg_ring_struct;
2546		- ring->nr_pages = bp->rx_agg_nr_pages;
2547		- ring->page_size = HW_RXBD_RING_SIZE;
2548		- ring->pg_arr = (void **)rxr->rx_agg_desc_ring;
2549		- ring->dma_arr = rxr->rx_agg_desc_mapping;
2550		- ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
2551		- ring->vmem = (void **)&rxr->rx_agg_ring;
	3257	+ rmem = &ring->ring_mem;
	3258	+ rmem->nr_pages = bp->rx_agg_nr_pages;
	3259	+ rmem->page_size = HW_RXBD_RING_SIZE;
	3260	+ rmem->pg_arr = (void **)rxr->rx_agg_desc_ring;
	3261	+ rmem->dma_arr = rxr->rx_agg_desc_mapping;
	3262	+ rmem->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
	3263	+ rmem->vmem = (void **)&rxr->rx_agg_ring;
2552	3264
2553	3265	skip_rx:
2554	3266	txr = bnapi->tx_ring;
..	..	@@ -2556,12 +3268,13 @@
2556	3268	continue;
2557	3269
2558	3270	ring = &txr->tx_ring_struct;
2559		- ring->nr_pages = bp->tx_nr_pages;
2560		- ring->page_size = HW_RXBD_RING_SIZE;
2561		- ring->pg_arr = (void **)txr->tx_desc_ring;
2562		- ring->dma_arr = txr->tx_desc_mapping;
2563		- ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
2564		- ring->vmem = (void **)&txr->tx_buf_ring;
	3271	+ rmem = &ring->ring_mem;
	3272	+ rmem->nr_pages = bp->tx_nr_pages;
	3273	+ rmem->page_size = HW_RXBD_RING_SIZE;
	3274	+ rmem->pg_arr = (void **)txr->tx_desc_ring;
	3275	+ rmem->dma_arr = txr->tx_desc_mapping;
	3276	+ rmem->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
	3277	+ rmem->vmem = (void **)&txr->tx_buf_ring;
2565	3278	}
2566	3279	}
2567	3280
..	..	@@ -2571,8 +3284,8 @@
2571	3284	u32 prod;
2572	3285	struct rx_bd **rx_buf_ring;
2573	3286
2574		- rx_buf_ring = (struct rx_bd **)ring->pg_arr;
2575		- for (i = 0, prod = 0; i < ring->nr_pages; i++) {
	3287	+ rx_buf_ring = (struct rx_bd **)ring->ring_mem.pg_arr;
	3288	+ for (i = 0, prod = 0; i < ring->ring_mem.nr_pages; i++) {
2576	3289	int j;
2577	3290	struct rx_bd *rxbd;
2578	3291
..	..	@@ -2587,13 +3300,60 @@
2587	3300	}
2588	3301	}
2589	3302
	3303	+static int bnxt_alloc_one_rx_ring(struct bnxt *bp, int ring_nr)
	3304	+{
	3305	+ struct bnxt_rx_ring_info *rxr = &bp->rx_ring[ring_nr];
	3306	+ struct net_device *dev = bp->dev;
	3307	+ u32 prod;
	3308	+ int i;
	3309	+
	3310	+ prod = rxr->rx_prod;
	3311	+ for (i = 0; i < bp->rx_ring_size; i++) {
	3312	+ if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL)) {
	3313	+ netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
	3314	+ ring_nr, i, bp->rx_ring_size);
	3315	+ break;
	3316	+ }
	3317	+ prod = NEXT_RX(prod);
	3318	+ }
	3319	+ rxr->rx_prod = prod;
	3320	+
	3321	+ if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
	3322	+ return 0;
	3323	+
	3324	+ prod = rxr->rx_agg_prod;
	3325	+ for (i = 0; i < bp->rx_agg_ring_size; i++) {
	3326	+ if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL)) {
	3327	+ netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
	3328	+ ring_nr, i, bp->rx_ring_size);
	3329	+ break;
	3330	+ }
	3331	+ prod = NEXT_RX_AGG(prod);
	3332	+ }
	3333	+ rxr->rx_agg_prod = prod;
	3334	+
	3335	+ if (rxr->rx_tpa) {
	3336	+ dma_addr_t mapping;
	3337	+ u8 *data;
	3338	+
	3339	+ for (i = 0; i < bp->max_tpa; i++) {
	3340	+ data = __bnxt_alloc_rx_data(bp, &mapping, GFP_KERNEL);
	3341	+ if (!data)
	3342	+ return -ENOMEM;
	3343	+
	3344	+ rxr->rx_tpa[i].data = data;
	3345	+ rxr->rx_tpa[i].data_ptr = data + bp->rx_offset;
	3346	+ rxr->rx_tpa[i].mapping = mapping;
	3347	+ }
	3348	+ }
	3349	+ return 0;
	3350	+}
	3351	+
2590	3352	static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
2591	3353	{
2592		- struct net_device *dev = bp->dev;
2593	3354	struct bnxt_rx_ring_info *rxr;
2594	3355	struct bnxt_ring_struct *ring;
2595		- u32 prod, type;
2596		- int i;
	3356	+ u32 type;
2597	3357
2598	3358	type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) \|
2599	3359	RX_BD_TYPE_RX_PACKET_BD \| RX_BD_FLAGS_EOP;
..	..	@@ -2606,75 +3366,27 @@
2606	3366	bnxt_init_rxbd_pages(ring, type);
2607	3367
2608	3368	if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) {
2609		- rxr->xdp_prog = bpf_prog_add(bp->xdp_prog, 1);
2610		- if (IS_ERR(rxr->xdp_prog)) {
2611		- int rc = PTR_ERR(rxr->xdp_prog);
2612		-
2613		- rxr->xdp_prog = NULL;
2614		- return rc;
2615		- }
	3369	+ bpf_prog_add(bp->xdp_prog, 1);
	3370	+ rxr->xdp_prog = bp->xdp_prog;
2616	3371	}
2617		- prod = rxr->rx_prod;
2618		- for (i = 0; i < bp->rx_ring_size; i++) {
2619		- if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
2620		- netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
2621		- ring_nr, i, bp->rx_ring_size);
2622		- break;
2623		- }
2624		- prod = NEXT_RX(prod);
2625		- }
2626		- rxr->rx_prod = prod;
2627	3372	ring->fw_ring_id = INVALID_HW_RING_ID;
2628	3373
2629	3374	ring = &rxr->rx_agg_ring_struct;
2630	3375	ring->fw_ring_id = INVALID_HW_RING_ID;
2631	3376
2632		- if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2633		- return 0;
	3377	+ if ((bp->flags & BNXT_FLAG_AGG_RINGS)) {
	3378	+ type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) \|
	3379	+ RX_BD_TYPE_RX_AGG_BD \| RX_BD_FLAGS_SOP;
2634	3380
2635		- type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) \|
2636		- RX_BD_TYPE_RX_AGG_BD \| RX_BD_FLAGS_SOP;
2637		-
2638		- bnxt_init_rxbd_pages(ring, type);
2639		-
2640		- prod = rxr->rx_agg_prod;
2641		- for (i = 0; i < bp->rx_agg_ring_size; i++) {
2642		- if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2643		- netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2644		- ring_nr, i, bp->rx_ring_size);
2645		- break;
2646		- }
2647		- prod = NEXT_RX_AGG(prod);
2648		- }
2649		- rxr->rx_agg_prod = prod;
2650		-
2651		- if (bp->flags & BNXT_FLAG_TPA) {
2652		- if (rxr->rx_tpa) {
2653		- u8 *data;
2654		- dma_addr_t mapping;
2655		-
2656		- for (i = 0; i < MAX_TPA; i++) {
2657		- data = __bnxt_alloc_rx_data(bp, &mapping,
2658		- GFP_KERNEL);
2659		- if (!data)
2660		- return -ENOMEM;
2661		-
2662		- rxr->rx_tpa[i].data = data;
2663		- rxr->rx_tpa[i].data_ptr = data + bp->rx_offset;
2664		- rxr->rx_tpa[i].mapping = mapping;
2665		- }
2666		- } else {
2667		- netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2668		- return -ENOMEM;
2669		- }
	3381	+ bnxt_init_rxbd_pages(ring, type);
2670	3382	}
2671	3383
2672		- return 0;
	3384	+ return bnxt_alloc_one_rx_ring(bp, ring_nr);
2673	3385	}
2674	3386
2675	3387	static void bnxt_init_cp_rings(struct bnxt *bp)
2676	3388	{
2677		- int i;
	3389	+ int i, j;
2678	3390
2679	3391	for (i = 0; i < bp->cp_nr_rings; i++) {
2680	3392	struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
..	..	@@ -2683,6 +3395,17 @@
2683	3395	ring->fw_ring_id = INVALID_HW_RING_ID;
2684	3396	cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
2685	3397	cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
	3398	+ for (j = 0; j < 2; j++) {
	3399	+ struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
	3400	+
	3401	+ if (!cpr2)
	3402	+ continue;
	3403	+
	3404	+ ring = &cpr2->cp_ring_struct;
	3405	+ ring->fw_ring_id = INVALID_HW_RING_ID;
	3406	+ cpr2->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
	3407	+ cpr2->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
	3408	+ }
2686	3409	}
2687	3410	}
2688	3411
..	..	@@ -2764,7 +3487,7 @@
2764	3487	int num_vnics = 1;
2765	3488
2766	3489	#ifdef CONFIG_RFS_ACCEL
2767		- if (bp->flags & BNXT_FLAG_RFS)
	3490	+ if ((bp->flags & (BNXT_FLAG_RFS \| BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS)
2768	3491	num_vnics += bp->rx_nr_rings;
2769	3492	#endif
2770	3493
..	..	@@ -2786,10 +3509,12 @@
2786	3509
2787	3510	for (i = 0; i < bp->nr_vnics; i++) {
2788	3511	struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
	3512	+ int j;
2789	3513
2790	3514	vnic->fw_vnic_id = INVALID_HW_RING_ID;
2791		- vnic->fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
2792		- vnic->fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
	3515	+ for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++)
	3516	+ vnic->fw_rss_cos_lb_ctx[j] = INVALID_HW_RING_ID;
	3517	+
2793	3518	vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2794	3519
2795	3520	if (bp->vnic_info[i].rss_hash_key) {
..	..	@@ -2837,7 +3562,7 @@
2837	3562	*/
2838	3563	void bnxt_set_ring_params(struct bnxt *bp)
2839	3564	{
2840		- u32 ring_size, rx_size, rx_space;
	3565	+ u32 ring_size, rx_size, rx_space, max_rx_cmpl;
2841	3566	u32 agg_factor = 0, agg_ring_size = 0;
2842	3567
2843	3568	/* 8 for CRC and VLAN */
..	..	@@ -2893,7 +3618,15 @@
2893	3618	bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2894	3619	bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2895	3620
2896		- ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
	3621	+ max_rx_cmpl = bp->rx_ring_size;
	3622	+ /* MAX TPA needs to be added because TPA_START completions are
	3623	+ * immediately recycled, so the TPA completions are not bound by
	3624	+ * the RX ring size.
	3625	+ */
	3626	+ if (bp->flags & BNXT_FLAG_TPA)
	3627	+ max_rx_cmpl += bp->max_tpa;
	3628	+ /* RX and TPA completions are 32-byte, all others are 16-byte */
	3629	+ ring_size = max_rx_cmpl * 2 + agg_ring_size + bp->tx_ring_size;
2897	3630	bp->cp_ring_size = ring_size;
2898	3631
2899	3632	bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
..	..	@@ -2957,7 +3690,7 @@
2957	3690	}
2958	3691
2959	3692	if (vnic->rss_table) {
2960		- dma_free_coherent(&pdev->dev, PAGE_SIZE,
	3693	+ dma_free_coherent(&pdev->dev, vnic->rss_table_size,
2961	3694	vnic->rss_table,
2962	3695	vnic->rss_table_dma_addr);
2963	3696	vnic->rss_table = NULL;
..	..	@@ -3003,6 +3736,9 @@
3003	3736	}
3004	3737	}
3005	3738
	3739	+ if (bp->flags & BNXT_FLAG_CHIP_P5)
	3740	+ goto vnic_skip_grps;
	3741	+
3006	3742	if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3007	3743	max_rings = bp->rx_nr_rings;
3008	3744	else
..	..	@@ -3013,21 +3749,25 @@
3013	3749	rc = -ENOMEM;
3014	3750	goto out;
3015	3751	}
3016		-
	3752	+vnic_skip_grps:
3017	3753	if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
3018	3754	!(vnic->flags & BNXT_VNIC_RSS_FLAG))
3019	3755	continue;
3020	3756
3021	3757	/* Allocate rss table and hash key */
3022		- vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
	3758	+ size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
	3759	+ if (bp->flags & BNXT_FLAG_CHIP_P5)
	3760	+ size = L1_CACHE_ALIGN(BNXT_MAX_RSS_TABLE_SIZE_P5);
	3761	+
	3762	+ vnic->rss_table_size = size + HW_HASH_KEY_SIZE;
	3763	+ vnic->rss_table = dma_alloc_coherent(&pdev->dev,
	3764	+ vnic->rss_table_size,
3023	3765	&vnic->rss_table_dma_addr,
3024	3766	GFP_KERNEL);
3025	3767	if (!vnic->rss_table) {
3026	3768	rc = -ENOMEM;
3027	3769	goto out;
3028	3770	}
3029		-
3030		- size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
3031	3771
3032	3772	vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
3033	3773	vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
..	..	@@ -3047,6 +3787,30 @@
3047	3787	bp->hwrm_cmd_resp_dma_addr);
3048	3788	bp->hwrm_cmd_resp_addr = NULL;
3049	3789	}
	3790	+
	3791	+ if (bp->hwrm_cmd_kong_resp_addr) {
	3792	+ dma_free_coherent(&pdev->dev, PAGE_SIZE,
	3793	+ bp->hwrm_cmd_kong_resp_addr,
	3794	+ bp->hwrm_cmd_kong_resp_dma_addr);
	3795	+ bp->hwrm_cmd_kong_resp_addr = NULL;
	3796	+ }
	3797	+}
	3798	+
	3799	+static int bnxt_alloc_kong_hwrm_resources(struct bnxt *bp)
	3800	+{
	3801	+ struct pci_dev *pdev = bp->pdev;
	3802	+
	3803	+ if (bp->hwrm_cmd_kong_resp_addr)
	3804	+ return 0;
	3805	+
	3806	+ bp->hwrm_cmd_kong_resp_addr =
	3807	+ dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
	3808	+ &bp->hwrm_cmd_kong_resp_dma_addr,
	3809	+ GFP_KERNEL);
	3810	+ if (!bp->hwrm_cmd_kong_resp_addr)
	3811	+ return -ENOMEM;
	3812	+
	3813	+ return 0;
3050	3814	}
3051	3815
3052	3816	static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
..	..	@@ -3067,7 +3831,7 @@
3067	3831	if (bp->hwrm_short_cmd_req_addr) {
3068	3832	struct pci_dev *pdev = bp->pdev;
3069	3833
3070		- dma_free_coherent(&pdev->dev, BNXT_HWRM_MAX_REQ_LEN,
	3834	+ dma_free_coherent(&pdev->dev, bp->hwrm_max_ext_req_len,
3071	3835	bp->hwrm_short_cmd_req_addr,
3072	3836	bp->hwrm_short_cmd_req_dma_addr);
3073	3837	bp->hwrm_short_cmd_req_addr = NULL;
..	..	@@ -3078,8 +3842,11 @@
3078	3842	{
3079	3843	struct pci_dev *pdev = bp->pdev;
3080	3844
	3845	+ if (bp->hwrm_short_cmd_req_addr)
	3846	+ return 0;
	3847	+
3081	3848	bp->hwrm_short_cmd_req_addr =
3082		- dma_alloc_coherent(&pdev->dev, BNXT_HWRM_MAX_REQ_LEN,
	3849	+ dma_alloc_coherent(&pdev->dev, bp->hwrm_max_ext_req_len,
3083	3850	&bp->hwrm_short_cmd_req_dma_addr,
3084	3851	GFP_KERNEL);
3085	3852	if (!bp->hwrm_short_cmd_req_addr)
..	..	@@ -3088,97 +3855,246 @@
3088	3855	return 0;
3089	3856	}
3090	3857
3091		-static void bnxt_free_stats(struct bnxt *bp)
	3858	+static void bnxt_free_stats_mem(struct bnxt bp, struct bnxt_stats_mem stats)
3092	3859	{
3093		- u32 size, i;
3094		- struct pci_dev *pdev = bp->pdev;
	3860	+ kfree(stats->hw_masks);
	3861	+ stats->hw_masks = NULL;
	3862	+ kfree(stats->sw_stats);
	3863	+ stats->sw_stats = NULL;
	3864	+ if (stats->hw_stats) {
	3865	+ dma_free_coherent(&bp->pdev->dev, stats->len, stats->hw_stats,
	3866	+ stats->hw_stats_map);
	3867	+ stats->hw_stats = NULL;
	3868	+ }
	3869	+}
3095	3870
	3871	+static int bnxt_alloc_stats_mem(struct bnxt bp, struct bnxt_stats_mem stats,
	3872	+ bool alloc_masks)
	3873	+{
	3874	+ stats->hw_stats = dma_alloc_coherent(&bp->pdev->dev, stats->len,
	3875	+ &stats->hw_stats_map, GFP_KERNEL);
	3876	+ if (!stats->hw_stats)
	3877	+ return -ENOMEM;
	3878	+
	3879	+ stats->sw_stats = kzalloc(stats->len, GFP_KERNEL);
	3880	+ if (!stats->sw_stats)
	3881	+ goto stats_mem_err;
	3882	+
	3883	+ if (alloc_masks) {
	3884	+ stats->hw_masks = kzalloc(stats->len, GFP_KERNEL);
	3885	+ if (!stats->hw_masks)
	3886	+ goto stats_mem_err;
	3887	+ }
	3888	+ return 0;
	3889	+
	3890	+stats_mem_err:
	3891	+ bnxt_free_stats_mem(bp, stats);
	3892	+ return -ENOMEM;
	3893	+}
	3894	+
	3895	+static void bnxt_fill_masks(u64 *mask_arr, u64 mask, int count)
	3896	+{
	3897	+ int i;
	3898	+
	3899	+ for (i = 0; i < count; i++)
	3900	+ mask_arr[i] = mask;
	3901	+}
	3902	+
	3903	+static void bnxt_copy_hw_masks(u64 mask_arr, __le64 hw_mask_arr, int count)
	3904	+{
	3905	+ int i;
	3906	+
	3907	+ for (i = 0; i < count; i++)
	3908	+ mask_arr[i] = le64_to_cpu(hw_mask_arr[i]);
	3909	+}
	3910	+
	3911	+static int bnxt_hwrm_func_qstat_ext(struct bnxt *bp,
	3912	+ struct bnxt_stats_mem *stats)
	3913	+{
	3914	+ struct hwrm_func_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
	3915	+ struct hwrm_func_qstats_ext_input req = {0};
	3916	+ __le64 *hw_masks;
	3917	+ int rc;
	3918	+
	3919	+ if (!(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED) \|\|
	3920	+ !(bp->flags & BNXT_FLAG_CHIP_P5))
	3921	+ return -EOPNOTSUPP;
	3922	+
	3923	+ bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QSTATS_EXT, -1, -1);
	3924	+ req.fid = cpu_to_le16(0xffff);
	3925	+ req.flags = FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK;
	3926	+ mutex_lock(&bp->hwrm_cmd_lock);
	3927	+ rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
	3928	+ if (rc)
	3929	+ goto qstat_exit;
	3930	+
	3931	+ hw_masks = &resp->rx_ucast_pkts;
	3932	+ bnxt_copy_hw_masks(stats->hw_masks, hw_masks, stats->len / 8);
	3933	+
	3934	+qstat_exit:
	3935	+ mutex_unlock(&bp->hwrm_cmd_lock);
	3936	+ return rc;
	3937	+}
	3938	+
	3939	+static int bnxt_hwrm_port_qstats(struct bnxt *bp, u8 flags);
	3940	+static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp, u8 flags);
	3941	+
	3942	+static void bnxt_init_stats(struct bnxt *bp)
	3943	+{
	3944	+ struct bnxt_napi *bnapi = bp->bnapi[0];
	3945	+ struct bnxt_cp_ring_info *cpr;
	3946	+ struct bnxt_stats_mem *stats;
	3947	+ __le64 rx_stats, tx_stats;
	3948	+ int rc, rx_count, tx_count;
	3949	+ u64 rx_masks, tx_masks;
	3950	+ u64 mask;
	3951	+ u8 flags;
	3952	+
	3953	+ cpr = &bnapi->cp_ring;
	3954	+ stats = &cpr->stats;
	3955	+ rc = bnxt_hwrm_func_qstat_ext(bp, stats);
	3956	+ if (rc) {
	3957	+ if (bp->flags & BNXT_FLAG_CHIP_P5)
	3958	+ mask = (1ULL << 48) - 1;
	3959	+ else
	3960	+ mask = -1ULL;
	3961	+ bnxt_fill_masks(stats->hw_masks, mask, stats->len / 8);
	3962	+ }
	3963	+ if (bp->flags & BNXT_FLAG_PORT_STATS) {
	3964	+ stats = &bp->port_stats;
	3965	+ rx_stats = stats->hw_stats;
	3966	+ rx_masks = stats->hw_masks;
	3967	+ rx_count = sizeof(struct rx_port_stats) / 8;
	3968	+ tx_stats = rx_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
	3969	+ tx_masks = rx_masks + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
	3970	+ tx_count = sizeof(struct tx_port_stats) / 8;
	3971	+
	3972	+ flags = PORT_QSTATS_REQ_FLAGS_COUNTER_MASK;
	3973	+ rc = bnxt_hwrm_port_qstats(bp, flags);
	3974	+ if (rc) {
	3975	+ mask = (1ULL << 40) - 1;
	3976	+
	3977	+ bnxt_fill_masks(rx_masks, mask, rx_count);
	3978	+ bnxt_fill_masks(tx_masks, mask, tx_count);
	3979	+ } else {
	3980	+ bnxt_copy_hw_masks(rx_masks, rx_stats, rx_count);
	3981	+ bnxt_copy_hw_masks(tx_masks, tx_stats, tx_count);
	3982	+ bnxt_hwrm_port_qstats(bp, 0);
	3983	+ }
	3984	+ }
	3985	+ if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
	3986	+ stats = &bp->rx_port_stats_ext;
	3987	+ rx_stats = stats->hw_stats;
	3988	+ rx_masks = stats->hw_masks;
	3989	+ rx_count = sizeof(struct rx_port_stats_ext) / 8;
	3990	+ stats = &bp->tx_port_stats_ext;
	3991	+ tx_stats = stats->hw_stats;
	3992	+ tx_masks = stats->hw_masks;
	3993	+ tx_count = sizeof(struct tx_port_stats_ext) / 8;
	3994	+
	3995	+ flags = PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK;
	3996	+ rc = bnxt_hwrm_port_qstats_ext(bp, flags);
	3997	+ if (rc) {
	3998	+ mask = (1ULL << 40) - 1;
	3999	+
	4000	+ bnxt_fill_masks(rx_masks, mask, rx_count);
	4001	+ if (tx_stats)
	4002	+ bnxt_fill_masks(tx_masks, mask, tx_count);
	4003	+ } else {
	4004	+ bnxt_copy_hw_masks(rx_masks, rx_stats, rx_count);
	4005	+ if (tx_stats)
	4006	+ bnxt_copy_hw_masks(tx_masks, tx_stats,
	4007	+ tx_count);
	4008	+ bnxt_hwrm_port_qstats_ext(bp, 0);
	4009	+ }
	4010	+ }
	4011	+}
	4012	+
	4013	+static void bnxt_free_port_stats(struct bnxt *bp)
	4014	+{
3096	4015	bp->flags &= ~BNXT_FLAG_PORT_STATS;
3097	4016	bp->flags &= ~BNXT_FLAG_PORT_STATS_EXT;
3098	4017
3099		- if (bp->hw_rx_port_stats) {
3100		- dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
3101		- bp->hw_rx_port_stats,
3102		- bp->hw_rx_port_stats_map);
3103		- bp->hw_rx_port_stats = NULL;
3104		- }
	4018	+ bnxt_free_stats_mem(bp, &bp->port_stats);
	4019	+ bnxt_free_stats_mem(bp, &bp->rx_port_stats_ext);
	4020	+ bnxt_free_stats_mem(bp, &bp->tx_port_stats_ext);
	4021	+}
3105	4022
3106		- if (bp->hw_rx_port_stats_ext) {
3107		- dma_free_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext),
3108		- bp->hw_rx_port_stats_ext,
3109		- bp->hw_rx_port_stats_ext_map);
3110		- bp->hw_rx_port_stats_ext = NULL;
3111		- }
	4023	+static void bnxt_free_ring_stats(struct bnxt *bp)
	4024	+{
	4025	+ int i;
3112	4026
3113	4027	if (!bp->bnapi)
3114	4028	return;
3115		-
3116		- size = sizeof(struct ctx_hw_stats);
3117	4029
3118	4030	for (i = 0; i < bp->cp_nr_rings; i++) {
3119	4031	struct bnxt_napi *bnapi = bp->bnapi[i];
3120	4032	struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3121	4033
3122		- if (cpr->hw_stats) {
3123		- dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
3124		- cpr->hw_stats_map);
3125		- cpr->hw_stats = NULL;
3126		- }
	4034	+ bnxt_free_stats_mem(bp, &cpr->stats);
3127	4035	}
3128	4036	}
3129	4037
3130	4038	static int bnxt_alloc_stats(struct bnxt *bp)
3131	4039	{
3132	4040	u32 size, i;
3133		- struct pci_dev *pdev = bp->pdev;
	4041	+ int rc;
3134	4042
3135		- size = sizeof(struct ctx_hw_stats);
	4043	+ size = bp->hw_ring_stats_size;
3136	4044
3137	4045	for (i = 0; i < bp->cp_nr_rings; i++) {
3138	4046	struct bnxt_napi *bnapi = bp->bnapi[i];
3139	4047	struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3140	4048
3141		- cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
3142		- &cpr->hw_stats_map,
3143		- GFP_KERNEL);
3144		- if (!cpr->hw_stats)
3145		- return -ENOMEM;
	4049	+ cpr->stats.len = size;
	4050	+ rc = bnxt_alloc_stats_mem(bp, &cpr->stats, !i);
	4051	+ if (rc)
	4052	+ return rc;
3146	4053
3147	4054	cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3148	4055	}
3149	4056
3150		- if (BNXT_PF(bp) && bp->chip_num != CHIP_NUM_58700) {
3151		- bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
3152		- sizeof(struct tx_port_stats) + 1024;
	4057	+ if (BNXT_VF(bp) \|\| bp->chip_num == CHIP_NUM_58700)
	4058	+ return 0;
3153	4059
3154		- bp->hw_rx_port_stats =
3155		- dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
3156		- &bp->hw_rx_port_stats_map,
3157		- GFP_KERNEL);
3158		- if (!bp->hw_rx_port_stats)
3159		- return -ENOMEM;
	4060	+ if (bp->port_stats.hw_stats)
	4061	+ goto alloc_ext_stats;
3160	4062
3161		- bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) +
3162		- 512;
3163		- bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
3164		- sizeof(struct rx_port_stats) + 512;
3165		- bp->flags \|= BNXT_FLAG_PORT_STATS;
	4063	+ bp->port_stats.len = BNXT_PORT_STATS_SIZE;
	4064	+ rc = bnxt_alloc_stats_mem(bp, &bp->port_stats, true);
	4065	+ if (rc)
	4066	+ return rc;
3166	4067
3167		- /* Display extended statistics only if FW supports it */
3168		- if (bp->hwrm_spec_code < 0x10804 \|\|
3169		- bp->hwrm_spec_code == 0x10900)
	4068	+ bp->flags \|= BNXT_FLAG_PORT_STATS;
	4069	+
	4070	+alloc_ext_stats:
	4071	+ /* Display extended statistics only if FW supports it */
	4072	+ if (bp->hwrm_spec_code < 0x10804 \|\| bp->hwrm_spec_code == 0x10900)
	4073	+ if (!(bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED))
3170	4074	return 0;
3171	4075
3172		- bp->hw_rx_port_stats_ext =
3173		- dma_zalloc_coherent(&pdev->dev,
3174		- sizeof(struct rx_port_stats_ext),
3175		- &bp->hw_rx_port_stats_ext_map,
3176		- GFP_KERNEL);
3177		- if (!bp->hw_rx_port_stats_ext)
3178		- return 0;
	4076	+ if (bp->rx_port_stats_ext.hw_stats)
	4077	+ goto alloc_tx_ext_stats;
3179	4078
3180		- bp->flags \|= BNXT_FLAG_PORT_STATS_EXT;
	4079	+ bp->rx_port_stats_ext.len = sizeof(struct rx_port_stats_ext);
	4080	+ rc = bnxt_alloc_stats_mem(bp, &bp->rx_port_stats_ext, true);
	4081	+ /* Extended stats are optional */
	4082	+ if (rc)
	4083	+ return 0;
	4084	+
	4085	+alloc_tx_ext_stats:
	4086	+ if (bp->tx_port_stats_ext.hw_stats)
	4087	+ return 0;
	4088	+
	4089	+ if (bp->hwrm_spec_code >= 0x10902 \|\|
	4090	+ (bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) {
	4091	+ bp->tx_port_stats_ext.len = sizeof(struct tx_port_stats_ext);
	4092	+ rc = bnxt_alloc_stats_mem(bp, &bp->tx_port_stats_ext, true);
	4093	+ /* Extended stats are optional */
	4094	+ if (rc)
	4095	+ return 0;
3181	4096	}
	4097	+ bp->flags \|= BNXT_FLAG_PORT_STATS_EXT;
3182	4098	return 0;
3183	4099	}
3184	4100
..	..	@@ -3277,7 +4193,10 @@
3277	4193	bnxt_free_cp_rings(bp);
3278	4194	bnxt_free_ntp_fltrs(bp, irq_re_init);
3279	4195	if (irq_re_init) {
3280		- bnxt_free_stats(bp);
	4196	+ bnxt_free_ring_stats(bp);
	4197	+ if (!(bp->fw_cap & BNXT_FW_CAP_PORT_STATS_NO_RESET) \|\|
	4198	+ test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
	4199	+ bnxt_free_port_stats(bp);
3281	4200	bnxt_free_ring_grps(bp);
3282	4201	bnxt_free_vnics(bp);
3283	4202	kfree(bp->tx_ring_map);
..	..	@@ -3315,6 +4234,13 @@
3315	4234	bp->bnapi[i] = bnapi;
3316	4235	bp->bnapi[i]->index = i;
3317	4236	bp->bnapi[i]->bp = bp;
	4237	+ if (bp->flags & BNXT_FLAG_CHIP_P5) {
	4238	+ struct bnxt_cp_ring_info *cpr =
	4239	+ &bp->bnapi[i]->cp_ring;
	4240	+
	4241	+ cpr->cp_ring_struct.ring_mem.flags =
	4242	+ BNXT_RMEM_RING_PTE_FLAG;
	4243	+ }
3318	4244	}
3319	4245
3320	4246	bp->rx_ring = kcalloc(bp->rx_nr_rings,
..	..	@@ -3324,7 +4250,15 @@
3324	4250	return -ENOMEM;
3325	4251
3326	4252	for (i = 0; i < bp->rx_nr_rings; i++) {
3327		- bp->rx_ring[i].bnapi = bp->bnapi[i];
	4253	+ struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
	4254	+
	4255	+ if (bp->flags & BNXT_FLAG_CHIP_P5) {
	4256	+ rxr->rx_ring_struct.ring_mem.flags =
	4257	+ BNXT_RMEM_RING_PTE_FLAG;
	4258	+ rxr->rx_agg_ring_struct.ring_mem.flags =
	4259	+ BNXT_RMEM_RING_PTE_FLAG;
	4260	+ }
	4261	+ rxr->bnapi = bp->bnapi[i];
3328	4262	bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
3329	4263	}
3330	4264
..	..	@@ -3346,12 +4280,16 @@
3346	4280	j = bp->rx_nr_rings;
3347	4281
3348	4282	for (i = 0; i < bp->tx_nr_rings; i++, j++) {
3349		- bp->tx_ring[i].bnapi = bp->bnapi[j];
3350		- bp->bnapi[j]->tx_ring = &bp->tx_ring[i];
	4283	+ struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
	4284	+
	4285	+ if (bp->flags & BNXT_FLAG_CHIP_P5)
	4286	+ txr->tx_ring_struct.ring_mem.flags =
	4287	+ BNXT_RMEM_RING_PTE_FLAG;
	4288	+ txr->bnapi = bp->bnapi[j];
	4289	+ bp->bnapi[j]->tx_ring = txr;
3351	4290	bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
3352	4291	if (i >= bp->tx_nr_rings_xdp) {
3353		- bp->tx_ring[i].txq_index = i -
3354		- bp->tx_nr_rings_xdp;
	4292	+ txr->txq_index = i - bp->tx_nr_rings_xdp;
3355	4293	bp->bnapi[j]->tx_int = bnxt_tx_int;
3356	4294	} else {
3357	4295	bp->bnapi[j]->flags \|= BNXT_NAPI_FLAG_XDP;
..	..	@@ -3362,6 +4300,7 @@
3362	4300	rc = bnxt_alloc_stats(bp);
3363	4301	if (rc)
3364	4302	goto alloc_mem_err;
	4303	+ bnxt_init_stats(bp);
3365	4304
3366	4305	rc = bnxt_alloc_ntp_fltrs(bp);
3367	4306	if (rc)
..	..	@@ -3411,7 +4350,7 @@
3411	4350	struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3412	4351
3413	4352	if (ring->fw_ring_id != INVALID_HW_RING_ID)
3414		- BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
	4353	+ bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
3415	4354	}
3416	4355	}
3417	4356
..	..	@@ -3447,7 +4386,7 @@
3447	4386	struct bnxt_napi *bnapi = bp->bnapi[i];
3448	4387	struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3449	4388
3450		- BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
	4389	+ bnxt_db_nq_arm(bp, &cpr->cp_db, cpr->cp_raw_cons);
3451	4390	}
3452	4391	}
3453	4392
..	..	@@ -3459,7 +4398,39 @@
3459	4398	req->req_type = cpu_to_le16(req_type);
3460	4399	req->cmpl_ring = cpu_to_le16(cmpl_ring);
3461	4400	req->target_id = cpu_to_le16(target_id);
3462		- req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
	4401	+ if (bnxt_kong_hwrm_message(bp, req))
	4402	+ req->resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr);
	4403	+ else
	4404	+ req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
	4405	+}
	4406	+
	4407	+static int bnxt_hwrm_to_stderr(u32 hwrm_err)
	4408	+{
	4409	+ switch (hwrm_err) {
	4410	+ case HWRM_ERR_CODE_SUCCESS:
	4411	+ return 0;
	4412	+ case HWRM_ERR_CODE_RESOURCE_LOCKED:
	4413	+ return -EROFS;
	4414	+ case HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED:
	4415	+ return -EACCES;
	4416	+ case HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR:
	4417	+ return -ENOSPC;
	4418	+ case HWRM_ERR_CODE_INVALID_PARAMS:
	4419	+ case HWRM_ERR_CODE_INVALID_FLAGS:
	4420	+ case HWRM_ERR_CODE_INVALID_ENABLES:
	4421	+ case HWRM_ERR_CODE_UNSUPPORTED_TLV:
	4422	+ case HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR:
	4423	+ return -EINVAL;
	4424	+ case HWRM_ERR_CODE_NO_BUFFER:
	4425	+ return -ENOMEM;
	4426	+ case HWRM_ERR_CODE_HOT_RESET_PROGRESS:
	4427	+ case HWRM_ERR_CODE_BUSY:
	4428	+ return -EAGAIN;
	4429	+ case HWRM_ERR_CODE_CMD_NOT_SUPPORTED:
	4430	+ return -EOPNOTSUPP;
	4431	+ default:
	4432	+ return -EIO;
	4433	+ }
3463	4434	}
3464	4435
3465	4436	static int bnxt_hwrm_do_send_msg(struct bnxt bp, void msg, u32 msg_len,
..	..	@@ -3468,24 +4439,56 @@
3468	4439	int i, intr_process, rc, tmo_count;
3469	4440	struct input *req = msg;
3470	4441	u32 *data = msg;
3471		- __le32 *resp_len;
3472	4442	u8 *valid;
3473	4443	u16 cp_ring_id, len = 0;
3474	4444	struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
3475	4445	u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN;
3476	4446	struct hwrm_short_input short_input = {0};
	4447	+ u32 doorbell_offset = BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER;
	4448	+ u32 bar_offset = BNXT_GRCPF_REG_CHIMP_COMM;
	4449	+ u16 dst = BNXT_HWRM_CHNL_CHIMP;
3477	4450
3478		- req->seq_id = cpu_to_le16(bp->hwrm_cmd_seq++);
	4451	+ if (BNXT_NO_FW_ACCESS(bp) &&
	4452	+ le16_to_cpu(req->req_type) != HWRM_FUNC_RESET)
	4453	+ return -EBUSY;
	4454	+
	4455	+ if (msg_len > BNXT_HWRM_MAX_REQ_LEN) {
	4456	+ if (msg_len > bp->hwrm_max_ext_req_len \|\|
	4457	+ !bp->hwrm_short_cmd_req_addr)
	4458	+ return -EINVAL;
	4459	+ }
	4460	+
	4461	+ if (bnxt_hwrm_kong_chnl(bp, req)) {
	4462	+ dst = BNXT_HWRM_CHNL_KONG;
	4463	+ bar_offset = BNXT_GRCPF_REG_KONG_COMM;
	4464	+ doorbell_offset = BNXT_GRCPF_REG_KONG_COMM_TRIGGER;
	4465	+ resp = bp->hwrm_cmd_kong_resp_addr;
	4466	+ }
	4467	+
3479	4468	memset(resp, 0, PAGE_SIZE);
3480	4469	cp_ring_id = le16_to_cpu(req->cmpl_ring);
3481	4470	intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
3482	4471
3483		- if (bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) {
	4472	+ req->seq_id = cpu_to_le16(bnxt_get_hwrm_seq_id(bp, dst));
	4473	+ /* currently supports only one outstanding message */
	4474	+ if (intr_process)
	4475	+ bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
	4476	+
	4477	+ if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) \|\|
	4478	+ msg_len > BNXT_HWRM_MAX_REQ_LEN) {
3484	4479	void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
	4480	+ u16 max_msg_len;
	4481	+
	4482	+ /* Set boundary for maximum extended request length for short
	4483	+ * cmd format. If passed up from device use the max supported
	4484	+ * internal req length.
	4485	+ */
	4486	+ max_msg_len = bp->hwrm_max_ext_req_len;
3485	4487
3486	4488	memcpy(short_cmd_req, req, msg_len);
3487		- memset(short_cmd_req + msg_len, 0, BNXT_HWRM_MAX_REQ_LEN -
3488		- msg_len);
	4489	+ if (msg_len < max_msg_len)
	4490	+ memset(short_cmd_req + msg_len, 0,
	4491	+ max_msg_len - msg_len);
3489	4492
3490	4493	short_input.req_type = req->req_type;
3491	4494	short_input.signature =
..	..	@@ -3504,17 +4507,16 @@
3504	4507	}
3505	4508
3506	4509	/* Write request msg to hwrm channel */
3507		- __iowrite32_copy(bp->bar0, data, msg_len / 4);
	4510	+ __iowrite32_copy(bp->bar0 + bar_offset, data, msg_len / 4);
3508	4511
3509	4512	for (i = msg_len; i < max_req_len; i += 4)
3510		- writel(0, bp->bar0 + i);
3511		-
3512		- /* currently supports only one outstanding message */
3513		- if (intr_process)
3514		- bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
	4513	+ writel(0, bp->bar0 + bar_offset + i);
3515	4514
3516	4515	/* Ring channel doorbell */
3517		- writel(1, bp->bar0 + 0x100);
	4516	+ writel(1, bp->bar0 + doorbell_offset);
	4517	+
	4518	+ if (!pci_is_enabled(bp->pdev))
	4519	+ return 0;
3518	4520
3519	4521	if (!timeout)
3520	4522	timeout = DFLT_HWRM_CMD_TIMEOUT;
..	..	@@ -3529,11 +4531,18 @@
3529	4531	tmo_count = HWRM_SHORT_TIMEOUT_COUNTER;
3530	4532	timeout = timeout - HWRM_SHORT_MIN_TIMEOUT * HWRM_SHORT_TIMEOUT_COUNTER;
3531	4533	tmo_count += DIV_ROUND_UP(timeout, HWRM_MIN_TIMEOUT);
3532		- resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
	4534	+
3533	4535	if (intr_process) {
	4536	+ u16 seq_id = bp->hwrm_intr_seq_id;
	4537	+
3534	4538	/* Wait until hwrm response cmpl interrupt is processed */
3535		- while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
	4539	+ while (bp->hwrm_intr_seq_id != (u16)~seq_id &&
3536	4540	i++ < tmo_count) {
	4541	+ /* Abort the wait for completion if the FW health
	4542	+ * check has failed.
	4543	+ */
	4544	+ if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))
	4545	+ return -EBUSY;
3537	4546	/* on first few passes, just barely sleep */
3538	4547	if (i < HWRM_SHORT_TIMEOUT_COUNTER)
3539	4548	usleep_range(HWRM_SHORT_MIN_TIMEOUT,
..	..	@@ -3543,21 +4552,25 @@
3543	4552	HWRM_MAX_TIMEOUT);
3544	4553	}
3545	4554
3546		- if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
3547		- netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
3548		- le16_to_cpu(req->req_type));
3549		- return -1;
	4555	+ if (bp->hwrm_intr_seq_id != (u16)~seq_id) {
	4556	+ if (!silent)
	4557	+ netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
	4558	+ le16_to_cpu(req->req_type));
	4559	+ return -EBUSY;
3550	4560	}
3551		- len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3552		- HWRM_RESP_LEN_SFT;
3553		- valid = bp->hwrm_cmd_resp_addr + len - 1;
	4561	+ len = le16_to_cpu(resp->resp_len);
	4562	+ valid = ((u8 *)resp) + len - 1;
3554	4563	} else {
3555	4564	int j;
3556	4565
3557	4566	/* Check if response len is updated */
3558	4567	for (i = 0; i < tmo_count; i++) {
3559		- len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3560		- HWRM_RESP_LEN_SFT;
	4568	+ /* Abort the wait for completion if the FW health
	4569	+ * check has failed.
	4570	+ */
	4571	+ if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))
	4572	+ return -EBUSY;
	4573	+ len = le16_to_cpu(resp->resp_len);
3561	4574	if (len)
3562	4575	break;
3563	4576	/* on first few passes, just barely sleep */
..	..	@@ -3570,15 +4583,16 @@
3570	4583	}
3571	4584
3572	4585	if (i >= tmo_count) {
3573		- netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
3574		- HWRM_TOTAL_TIMEOUT(i),
3575		- le16_to_cpu(req->req_type),
3576		- le16_to_cpu(req->seq_id), len);
3577		- return -1;
	4586	+ if (!silent)
	4587	+ netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
	4588	+ HWRM_TOTAL_TIMEOUT(i),
	4589	+ le16_to_cpu(req->req_type),
	4590	+ le16_to_cpu(req->seq_id), len);
	4591	+ return -EBUSY;
3578	4592	}
3579	4593
3580	4594	/* Last byte of resp contains valid bit */
3581		- valid = bp->hwrm_cmd_resp_addr + len - 1;
	4595	+ valid = ((u8 *)resp) + len - 1;
3582	4596	for (j = 0; j < HWRM_VALID_BIT_DELAY_USEC; j++) {
3583	4597	/* make sure we read from updated DMA memory */
3584	4598	dma_rmb();
..	..	@@ -3588,11 +4602,13 @@
3588	4602	}
3589	4603
3590	4604	if (j >= HWRM_VALID_BIT_DELAY_USEC) {
3591		- netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
3592		- HWRM_TOTAL_TIMEOUT(i),
3593		- le16_to_cpu(req->req_type),
3594		- le16_to_cpu(req->seq_id), len, *valid);
3595		- return -1;
	4605	+ if (!silent)
	4606	+ netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
	4607	+ HWRM_TOTAL_TIMEOUT(i),
	4608	+ le16_to_cpu(req->req_type),
	4609	+ le16_to_cpu(req->seq_id), len,
	4610	+ *valid);
	4611	+ return -EBUSY;
3596	4612	}
3597	4613	}
3598	4614
..	..	@@ -3606,7 +4622,7 @@
3606	4622	netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
3607	4623	le16_to_cpu(resp->req_type),
3608	4624	le16_to_cpu(resp->seq_id), rc);
3609		- return rc;
	4625	+ return bnxt_hwrm_to_stderr(rc);
3610	4626	}
3611	4627
3612	4628	int _hwrm_send_message(struct bnxt bp, void msg, u32 msg_len, int timeout)
..	..	@@ -3641,50 +4657,31 @@
3641	4657	return rc;
3642	4658	}
3643	4659
3644		-int bnxt_hwrm_func_rgtr_async_events(struct bnxt bp, unsigned long bmap,
3645		- int bmap_size)
3646		-{
3647		- struct hwrm_func_drv_rgtr_input req = {0};
3648		- DECLARE_BITMAP(async_events_bmap, 256);
3649		- u32 events = (u32 )async_events_bmap;
3650		- int i;
3651		-
3652		- bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3653		-
3654		- req.enables =
3655		- cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
3656		-
3657		- memset(async_events_bmap, 0, sizeof(async_events_bmap));
3658		- for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++)
3659		- __set_bit(bnxt_async_events_arr[i], async_events_bmap);
3660		-
3661		- if (bmap && bmap_size) {
3662		- for (i = 0; i < bmap_size; i++) {
3663		- if (test_bit(i, bmap))
3664		- __set_bit(i, async_events_bmap);
3665		- }
3666		- }
3667		-
3668		- for (i = 0; i < 8; i++)
3669		- req.async_event_fwd[i] \|= cpu_to_le32(events[i]);
3670		-
3671		- return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3672		-}
3673		-
3674		-static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
	4660	+int bnxt_hwrm_func_drv_rgtr(struct bnxt bp, unsigned long bmap, int bmap_size,
	4661	+ bool async_only)
3675	4662	{
3676	4663	struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3677	4664	struct hwrm_func_drv_rgtr_input req = {0};
3678		- int rc;
	4665	+ DECLARE_BITMAP(async_events_bmap, 256);
	4666	+ u32 events = (u32 )async_events_bmap;
	4667	+ u32 flags;
	4668	+ int rc, i;
3679	4669
3680	4670	bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3681	4671
3682	4672	req.enables =
3683	4673	cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE \|
3684		- FUNC_DRV_RGTR_REQ_ENABLES_VER);
	4674	+ FUNC_DRV_RGTR_REQ_ENABLES_VER \|
	4675	+ FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
3685	4676
3686	4677	req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
3687		- req.flags = cpu_to_le32(FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE);
	4678	+ flags = FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE;
	4679	+ if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
	4680	+ flags \|= FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT;
	4681	+ if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
	4682	+ flags \|= FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT \|
	4683	+ FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT;
	4684	+ req.flags = cpu_to_le32(flags);
3688	4685	req.ver_maj_8b = DRV_VER_MAJ;
3689	4686	req.ver_min_8b = DRV_VER_MIN;
3690	4687	req.ver_upd_8b = DRV_VER_UPD;
..	..	@@ -3713,13 +4710,40 @@
3713	4710	cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
3714	4711	}
3715	4712
	4713	+ if (bp->fw_cap & BNXT_FW_CAP_OVS_64BIT_HANDLE)
	4714	+ req.flags \|= cpu_to_le32(
	4715	+ FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE);
	4716	+
	4717	+ memset(async_events_bmap, 0, sizeof(async_events_bmap));
	4718	+ for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++) {
	4719	+ u16 event_id = bnxt_async_events_arr[i];
	4720	+
	4721	+ if (event_id == ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY &&
	4722	+ !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
	4723	+ continue;
	4724	+ __set_bit(bnxt_async_events_arr[i], async_events_bmap);
	4725	+ }
	4726	+ if (bmap && bmap_size) {
	4727	+ for (i = 0; i < bmap_size; i++) {
	4728	+ if (test_bit(i, bmap))
	4729	+ __set_bit(i, async_events_bmap);
	4730	+ }
	4731	+ }
	4732	+ for (i = 0; i < 8; i++)
	4733	+ req.async_event_fwd[i] \|= cpu_to_le32(events[i]);
	4734	+
	4735	+ if (async_only)
	4736	+ req.enables =
	4737	+ cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
	4738	+
3716	4739	mutex_lock(&bp->hwrm_cmd_lock);
3717	4740	rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3718		- if (rc)
3719		- rc = -EIO;
3720		- else if (resp->flags &
3721		- cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED))
3722		- bp->fw_cap \|= BNXT_FW_CAP_IF_CHANGE;
	4741	+ if (!rc) {
	4742	+ set_bit(BNXT_STATE_DRV_REGISTERED, &bp->state);
	4743	+ if (resp->flags &
	4744	+ cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED))
	4745	+ bp->fw_cap \|= BNXT_FW_CAP_IF_CHANGE;
	4746	+ }
3723	4747	mutex_unlock(&bp->hwrm_cmd_lock);
3724	4748	return rc;
3725	4749	}
..	..	@@ -3727,6 +4751,9 @@
3727	4751	static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
3728	4752	{
3729	4753	struct hwrm_func_drv_unrgtr_input req = {0};
	4754	+
	4755	+ if (!test_and_clear_bit(BNXT_STATE_DRV_REGISTERED, &bp->state))
	4756	+ return 0;
3730	4757
3731	4758	bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
3732	4759	return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
..	..	@@ -3742,10 +4769,12 @@
3742	4769
3743	4770	switch (tunnel_type) {
3744	4771	case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
3745		- req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
	4772	+ req.tunnel_dst_port_id = cpu_to_le16(bp->vxlan_fw_dst_port_id);
	4773	+ bp->vxlan_fw_dst_port_id = INVALID_HW_RING_ID;
3746	4774	break;
3747	4775	case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
3748		- req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
	4776	+ req.tunnel_dst_port_id = cpu_to_le16(bp->nge_fw_dst_port_id);
	4777	+ bp->nge_fw_dst_port_id = INVALID_HW_RING_ID;
3749	4778	break;
3750	4779	default:
3751	4780	break;
..	..	@@ -3780,10 +4809,11 @@
3780	4809
3781	4810	switch (tunnel_type) {
3782	4811	case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
3783		- bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
	4812	+ bp->vxlan_fw_dst_port_id =
	4813	+ le16_to_cpu(resp->tunnel_dst_port_id);
3784	4814	break;
3785	4815	case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
3786		- bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
	4816	+ bp->nge_fw_dst_port_id = le16_to_cpu(resp->tunnel_dst_port_id);
3787	4817	break;
3788	4818	default:
3789	4819	break;
..	..	@@ -3841,16 +4871,24 @@
3841	4871	static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
3842	4872	struct bnxt_ntuple_filter *fltr)
3843	4873	{
3844		- int rc = 0;
3845	4874	struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
3846		- struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3847		- bp->hwrm_cmd_resp_addr;
	4875	+ struct hwrm_cfa_ntuple_filter_alloc_output *resp;
3848	4876	struct flow_keys *keys = &fltr->fkeys;
3849		- struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
	4877	+ struct bnxt_vnic_info *vnic;
	4878	+ u32 flags = 0;
	4879	+ int rc = 0;
3850	4880
3851	4881	bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
3852	4882	req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
3853	4883
	4884	+ if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2) {
	4885	+ flags = CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX;
	4886	+ req.dst_id = cpu_to_le16(fltr->rxq);
	4887	+ } else {
	4888	+ vnic = &bp->vnic_info[fltr->rxq + 1];
	4889	+ req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
	4890	+ }
	4891	+ req.flags = cpu_to_le32(flags);
3854	4892	req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
3855	4893
3856	4894	req.ethertype = htons(ETH_P_IP);
..	..	@@ -3889,11 +4927,12 @@
3889	4927	req.dst_port = keys->ports.dst;
3890	4928	req.dst_port_mask = cpu_to_be16(0xffff);
3891	4929
3892		- req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
3893	4930	mutex_lock(&bp->hwrm_cmd_lock);
3894	4931	rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3895		- if (!rc)
	4932	+ if (!rc) {
	4933	+ resp = bnxt_get_hwrm_resp_addr(bp, &req);
3896	4934	fltr->filter_id = resp->ntuple_filter_id;
	4935	+ }
3897	4936	mutex_unlock(&bp->hwrm_cmd_lock);
3898	4937	return rc;
3899	4938	}
..	..	@@ -3964,6 +5003,7 @@
3964	5003	static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
3965	5004	{
3966	5005	struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
	5006	+ u16 max_aggs = VNIC_TPA_CFG_REQ_MAX_AGGS_MAX;
3967	5007	struct hwrm_vnic_tpa_cfg_input req = {0};
3968	5008
3969	5009	if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
..	..	@@ -4003,9 +5043,14 @@
4003	5043	nsegs = (MAX_SKB_FRAGS - n) / n;
4004	5044	}
4005	5045
4006		- segs = ilog2(nsegs);
	5046	+ if (bp->flags & BNXT_FLAG_CHIP_P5) {
	5047	+ segs = MAX_TPA_SEGS_P5;
	5048	+ max_aggs = bp->max_tpa;
	5049	+ } else {
	5050	+ segs = ilog2(nsegs);
	5051	+ }
4007	5052	req.max_agg_segs = cpu_to_le16(segs);
4008		- req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
	5053	+ req.max_aggs = cpu_to_le16(max_aggs);
4009	5054
4010	5055	req.min_agg_len = cpu_to_le32(512);
4011	5056	}
..	..	@@ -4014,41 +5059,196 @@
4014	5059	return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4015	5060	}
4016	5061
	5062	+static u16 bnxt_cp_ring_from_grp(struct bnxt bp, struct bnxt_ring_struct ring)
	5063	+{
	5064	+ struct bnxt_ring_grp_info *grp_info;
	5065	+
	5066	+ grp_info = &bp->grp_info[ring->grp_idx];
	5067	+ return grp_info->cp_fw_ring_id;
	5068	+}
	5069	+
	5070	+static u16 bnxt_cp_ring_for_rx(struct bnxt bp, struct bnxt_rx_ring_info rxr)
	5071	+{
	5072	+ if (bp->flags & BNXT_FLAG_CHIP_P5) {
	5073	+ struct bnxt_napi *bnapi = rxr->bnapi;
	5074	+ struct bnxt_cp_ring_info *cpr;
	5075	+
	5076	+ cpr = bnapi->cp_ring.cp_ring_arr[BNXT_RX_HDL];
	5077	+ return cpr->cp_ring_struct.fw_ring_id;
	5078	+ } else {
	5079	+ return bnxt_cp_ring_from_grp(bp, &rxr->rx_ring_struct);
	5080	+ }
	5081	+}
	5082	+
	5083	+static u16 bnxt_cp_ring_for_tx(struct bnxt bp, struct bnxt_tx_ring_info txr)
	5084	+{
	5085	+ if (bp->flags & BNXT_FLAG_CHIP_P5) {
	5086	+ struct bnxt_napi *bnapi = txr->bnapi;
	5087	+ struct bnxt_cp_ring_info *cpr;
	5088	+
	5089	+ cpr = bnapi->cp_ring.cp_ring_arr[BNXT_TX_HDL];
	5090	+ return cpr->cp_ring_struct.fw_ring_id;
	5091	+ } else {
	5092	+ return bnxt_cp_ring_from_grp(bp, &txr->tx_ring_struct);
	5093	+ }
	5094	+}
	5095	+
	5096	+static int bnxt_alloc_rss_indir_tbl(struct bnxt *bp)
	5097	+{
	5098	+ int entries;
	5099	+
	5100	+ if (bp->flags & BNXT_FLAG_CHIP_P5)
	5101	+ entries = BNXT_MAX_RSS_TABLE_ENTRIES_P5;
	5102	+ else
	5103	+ entries = HW_HASH_INDEX_SIZE;
	5104	+
	5105	+ bp->rss_indir_tbl_entries = entries;
	5106	+ bp->rss_indir_tbl = kmalloc_array(entries, sizeof(*bp->rss_indir_tbl),
	5107	+ GFP_KERNEL);
	5108	+ if (!bp->rss_indir_tbl)
	5109	+ return -ENOMEM;
	5110	+ return 0;
	5111	+}
	5112	+
	5113	+static void bnxt_set_dflt_rss_indir_tbl(struct bnxt *bp)
	5114	+{
	5115	+ u16 max_rings, max_entries, pad, i;
	5116	+
	5117	+ if (!bp->rx_nr_rings)
	5118	+ return;
	5119	+
	5120	+ if (BNXT_CHIP_TYPE_NITRO_A0(bp))
	5121	+ max_rings = bp->rx_nr_rings - 1;
	5122	+ else
	5123	+ max_rings = bp->rx_nr_rings;
	5124	+
	5125	+ max_entries = bnxt_get_rxfh_indir_size(bp->dev);
	5126	+
	5127	+ for (i = 0; i < max_entries; i++)
	5128	+ bp->rss_indir_tbl[i] = ethtool_rxfh_indir_default(i, max_rings);
	5129	+
	5130	+ pad = bp->rss_indir_tbl_entries - max_entries;
	5131	+ if (pad)
	5132	+ memset(&bp->rss_indir_tbl[i], 0, pad * sizeof(u16));
	5133	+}
	5134	+
	5135	+static u16 bnxt_get_max_rss_ring(struct bnxt *bp)
	5136	+{
	5137	+ u16 i, tbl_size, max_ring = 0;
	5138	+
	5139	+ if (!bp->rss_indir_tbl)
	5140	+ return 0;
	5141	+
	5142	+ tbl_size = bnxt_get_rxfh_indir_size(bp->dev);
	5143	+ for (i = 0; i < tbl_size; i++)
	5144	+ max_ring = max(max_ring, bp->rss_indir_tbl[i]);
	5145	+ return max_ring;
	5146	+}
	5147	+
	5148	+int bnxt_get_nr_rss_ctxs(struct bnxt *bp, int rx_rings)
	5149	+{
	5150	+ if (bp->flags & BNXT_FLAG_CHIP_P5)
	5151	+ return DIV_ROUND_UP(rx_rings, BNXT_RSS_TABLE_ENTRIES_P5);
	5152	+ if (BNXT_CHIP_TYPE_NITRO_A0(bp))
	5153	+ return 2;
	5154	+ return 1;
	5155	+}
	5156	+
	5157	+static void __bnxt_fill_hw_rss_tbl(struct bnxt bp, struct bnxt_vnic_info vnic)
	5158	+{
	5159	+ bool no_rss = !(vnic->flags & BNXT_VNIC_RSS_FLAG);
	5160	+ u16 i, j;
	5161	+
	5162	+ /* Fill the RSS indirection table with ring group ids */
	5163	+ for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++) {
	5164	+ if (!no_rss)
	5165	+ j = bp->rss_indir_tbl[i];
	5166	+ vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
	5167	+ }
	5168	+}
	5169	+
	5170	+static void __bnxt_fill_hw_rss_tbl_p5(struct bnxt *bp,
	5171	+ struct bnxt_vnic_info *vnic)
	5172	+{
	5173	+ __le16 *ring_tbl = vnic->rss_table;
	5174	+ struct bnxt_rx_ring_info *rxr;
	5175	+ u16 tbl_size, i;
	5176	+
	5177	+ tbl_size = bnxt_get_rxfh_indir_size(bp->dev);
	5178	+
	5179	+ for (i = 0; i < tbl_size; i++) {
	5180	+ u16 ring_id, j;
	5181	+
	5182	+ j = bp->rss_indir_tbl[i];
	5183	+ rxr = &bp->rx_ring[j];
	5184	+
	5185	+ ring_id = rxr->rx_ring_struct.fw_ring_id;
	5186	+ *ring_tbl++ = cpu_to_le16(ring_id);
	5187	+ ring_id = bnxt_cp_ring_for_rx(bp, rxr);
	5188	+ *ring_tbl++ = cpu_to_le16(ring_id);
	5189	+ }
	5190	+}
	5191	+
	5192	+static void bnxt_fill_hw_rss_tbl(struct bnxt bp, struct bnxt_vnic_info vnic)
	5193	+{
	5194	+ if (bp->flags & BNXT_FLAG_CHIP_P5)
	5195	+ __bnxt_fill_hw_rss_tbl_p5(bp, vnic);
	5196	+ else
	5197	+ __bnxt_fill_hw_rss_tbl(bp, vnic);
	5198	+}
	5199	+
4017	5200	static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
4018	5201	{
4019		- u32 i, j, max_rings;
4020	5202	struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4021	5203	struct hwrm_vnic_rss_cfg_input req = {0};
4022	5204
4023		- if (vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
	5205	+ if ((bp->flags & BNXT_FLAG_CHIP_P5) \|\|
	5206	+ vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
4024	5207	return 0;
4025	5208
4026	5209	bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
4027	5210	if (set_rss) {
	5211	+ bnxt_fill_hw_rss_tbl(bp, vnic);
4028	5212	req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
4029	5213	req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
4030		- if (vnic->flags & BNXT_VNIC_RSS_FLAG) {
4031		- if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4032		- max_rings = bp->rx_nr_rings - 1;
4033		- else
4034		- max_rings = bp->rx_nr_rings;
4035		- } else {
4036		- max_rings = 1;
4037		- }
4038		-
4039		- /* Fill the RSS indirection table with ring group ids */
4040		- for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
4041		- if (j == max_rings)
4042		- j = 0;
4043		- vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
4044		- }
4045		-
4046	5214	req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
4047	5215	req.hash_key_tbl_addr =
4048	5216	cpu_to_le64(vnic->rss_hash_key_dma_addr);
4049	5217	}
4050	5218	req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
4051	5219	return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
	5220	+}
	5221	+
	5222	+static int bnxt_hwrm_vnic_set_rss_p5(struct bnxt *bp, u16 vnic_id, bool set_rss)
	5223	+{
	5224	+ struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
	5225	+ struct hwrm_vnic_rss_cfg_input req = {0};
	5226	+ dma_addr_t ring_tbl_map;
	5227	+ u32 i, nr_ctxs;
	5228	+
	5229	+ bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
	5230	+ req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
	5231	+ if (!set_rss) {
	5232	+ hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
	5233	+ return 0;
	5234	+ }
	5235	+ bnxt_fill_hw_rss_tbl(bp, vnic);
	5236	+ req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
	5237	+ req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
	5238	+ req.hash_key_tbl_addr = cpu_to_le64(vnic->rss_hash_key_dma_addr);
	5239	+ ring_tbl_map = vnic->rss_table_dma_addr;
	5240	+ nr_ctxs = bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings);
	5241	+ for (i = 0; i < nr_ctxs; ring_tbl_map += BNXT_RSS_TABLE_SIZE_P5, i++) {
	5242	+ int rc;
	5243	+
	5244	+ req.ring_grp_tbl_addr = cpu_to_le64(ring_tbl_map);
	5245	+ req.ring_table_pair_index = i;
	5246	+ req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[i]);
	5247	+ rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
	5248	+ if (rc)
	5249	+ return rc;
	5250	+ }
	5251	+ return 0;
4052	5252	}
4053	5253
4054	5254	static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
..	..	@@ -4134,6 +5334,18 @@
4134	5334
4135	5335	bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
4136	5336
	5337	+ if (bp->flags & BNXT_FLAG_CHIP_P5) {
	5338	+ struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
	5339	+
	5340	+ req.default_rx_ring_id =
	5341	+ cpu_to_le16(rxr->rx_ring_struct.fw_ring_id);
	5342	+ req.default_cmpl_ring_id =
	5343	+ cpu_to_le16(bnxt_cp_ring_for_rx(bp, rxr));
	5344	+ req.enables =
	5345	+ cpu_to_le32(VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID \|
	5346	+ VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID);
	5347	+ goto vnic_mru;
	5348	+ }
4137	5349	req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
4138	5350	/* Only RSS support for now TBD: COS & LB */
4139	5351	if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
..	..	@@ -4166,13 +5378,12 @@
4166	5378	ring = bp->rx_nr_rings - 1;
4167	5379
4168	5380	grp_idx = bp->rx_ring[ring].bnapi->index;
4169		- req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4170	5381	req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
4171		-
4172	5382	req.lb_rule = cpu_to_le16(0xffff);
4173		- req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
4174		- VLAN_HLEN);
	5383	+vnic_mru:
	5384	+ req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + VLAN_HLEN);
4175	5385
	5386	+ req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4176	5387	#ifdef CONFIG_BNXT_SRIOV
4177	5388	if (BNXT_VF(bp))
4178	5389	def_vlan = bp->vf.vlan;
..	..	@@ -4185,10 +5396,8 @@
4185	5396	return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4186	5397	}
4187	5398
4188		-static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
	5399	+static void bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
4189	5400	{
4190		- u32 rc = 0;
4191		-
4192	5401	if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
4193	5402	struct hwrm_vnic_free_input req = {0};
4194	5403
..	..	@@ -4196,12 +5405,9 @@
4196	5405	req.vnic_id =
4197	5406	cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
4198	5407
4199		- rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4200		- if (rc)
4201		- return rc;
	5408	+ hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4202	5409	bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
4203	5410	}
4204		- return rc;
4205	5411	}
4206	5412
4207	5413	static void bnxt_hwrm_vnic_free(struct bnxt *bp)
..	..	@@ -4220,6 +5426,10 @@
4220	5426	unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
4221	5427	struct hwrm_vnic_alloc_input req = {0};
4222	5428	struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
	5429	+ struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
	5430	+
	5431	+ if (bp->flags & BNXT_FLAG_CHIP_P5)
	5432	+ goto vnic_no_ring_grps;
4223	5433
4224	5434	/* map ring groups to this vnic */
4225	5435	for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
..	..	@@ -4229,12 +5439,12 @@
4229	5439	j, nr_rings);
4230	5440	break;
4231	5441	}
4232		- bp->vnic_info[vnic_id].fw_grp_ids[j] =
4233		- bp->grp_info[grp_idx].fw_grp_id;
	5442	+ vnic->fw_grp_ids[j] = bp->grp_info[grp_idx].fw_grp_id;
4234	5443	}
4235	5444
4236		- bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
4237		- bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
	5445	+vnic_no_ring_grps:
	5446	+ for (i = 0; i < BNXT_MAX_CTX_PER_VNIC; i++)
	5447	+ vnic->fw_rss_cos_lb_ctx[i] = INVALID_HW_RING_ID;
4238	5448	if (vnic_id == 0)
4239	5449	req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
4240	5450
..	..	@@ -4243,7 +5453,7 @@
4243	5453	mutex_lock(&bp->hwrm_cmd_lock);
4244	5454	rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4245	5455	if (!rc)
4246		- bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
	5456	+ vnic->fw_vnic_id = le32_to_cpu(resp->vnic_id);
4247	5457	mutex_unlock(&bp->hwrm_cmd_lock);
4248	5458	return rc;
4249	5459	}
..	..	@@ -4254,6 +5464,8 @@
4254	5464	struct hwrm_vnic_qcaps_input req = {0};
4255	5465	int rc;
4256	5466
	5467	+ bp->hw_ring_stats_size = sizeof(struct ctx_hw_stats);
	5468	+ bp->flags &= ~(BNXT_FLAG_NEW_RSS_CAP \| BNXT_FLAG_ROCE_MIRROR_CAP);
4257	5469	if (bp->hwrm_spec_code < 0x10600)
4258	5470	return 0;
4259	5471
..	..	@@ -4263,11 +5475,27 @@
4263	5475	if (!rc) {
4264	5476	u32 flags = le32_to_cpu(resp->flags);
4265	5477
4266		- if (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP)
	5478	+ if (!(bp->flags & BNXT_FLAG_CHIP_P5) &&
	5479	+ (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP))
4267	5480	bp->flags \|= BNXT_FLAG_NEW_RSS_CAP;
4268	5481	if (flags &
4269	5482	VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP)
4270	5483	bp->flags \|= BNXT_FLAG_ROCE_MIRROR_CAP;
	5484	+
	5485	+ /* Older P5 fw before EXT_HW_STATS support did not set
	5486	+ * VLAN_STRIP_CAP properly.
	5487	+ */
	5488	+ if ((flags & VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP) \|\|
	5489	+ (BNXT_CHIP_P5_THOR(bp) &&
	5490	+ !(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED)))
	5491	+ bp->fw_cap \|= BNXT_FW_CAP_VLAN_RX_STRIP;
	5492	+ bp->max_tpa_v2 = le16_to_cpu(resp->max_aggs_supported);
	5493	+ if (bp->max_tpa_v2) {
	5494	+ if (BNXT_CHIP_P5_THOR(bp))
	5495	+ bp->hw_ring_stats_size = BNXT_RING_STATS_SIZE_P5;
	5496	+ else
	5497	+ bp->hw_ring_stats_size = BNXT_RING_STATS_SIZE_P5_SR2;
	5498	+ }
4271	5499	}
4272	5500	mutex_unlock(&bp->hwrm_cmd_lock);
4273	5501	return rc;
..	..	@@ -4277,6 +5505,9 @@
4277	5505	{
4278	5506	u16 i;
4279	5507	u32 rc = 0;
	5508	+
	5509	+ if (bp->flags & BNXT_FLAG_CHIP_P5)
	5510	+ return 0;
4280	5511
4281	5512	mutex_lock(&bp->hwrm_cmd_lock);
4282	5513	for (i = 0; i < bp->rx_nr_rings; i++) {
..	..	@@ -4304,14 +5535,13 @@
4304	5535	return rc;
4305	5536	}
4306	5537
4307		-static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
	5538	+static void bnxt_hwrm_ring_grp_free(struct bnxt *bp)
4308	5539	{
4309	5540	u16 i;
4310		- u32 rc = 0;
4311	5541	struct hwrm_ring_grp_free_input req = {0};
4312	5542
4313		- if (!bp->grp_info)
4314		- return 0;
	5543	+ if (!bp->grp_info \|\| (bp->flags & BNXT_FLAG_CHIP_P5))
	5544	+ return;
4315	5545
4316	5546	bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
4317	5547
..	..	@@ -4322,14 +5552,10 @@
4322	5552	req.ring_group_id =
4323	5553	cpu_to_le32(bp->grp_info[i].fw_grp_id);
4324	5554
4325		- rc = _hwrm_send_message(bp, &req, sizeof(req),
4326		- HWRM_CMD_TIMEOUT);
4327		- if (rc)
4328		- break;
	5555	+ _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4329	5556	bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
4330	5557	}
4331	5558	mutex_unlock(&bp->hwrm_cmd_lock);
4332		- return rc;
4333	5559	}
4334	5560
4335	5561	static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
..	..	@@ -4339,44 +5565,89 @@
4339	5565	int rc = 0, err = 0;
4340	5566	struct hwrm_ring_alloc_input req = {0};
4341	5567	struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
	5568	+ struct bnxt_ring_mem_info *rmem = &ring->ring_mem;
4342	5569	struct bnxt_ring_grp_info *grp_info;
4343	5570	u16 ring_id;
4344	5571
4345	5572	bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
4346	5573
4347	5574	req.enables = 0;
4348		- if (ring->nr_pages > 1) {
4349		- req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map);
	5575	+ if (rmem->nr_pages > 1) {
	5576	+ req.page_tbl_addr = cpu_to_le64(rmem->pg_tbl_map);
4350	5577	/* Page size is in log2 units */
4351	5578	req.page_size = BNXT_PAGE_SHIFT;
4352	5579	req.page_tbl_depth = 1;
4353	5580	} else {
4354		- req.page_tbl_addr = cpu_to_le64(ring->dma_arr[0]);
	5581	+ req.page_tbl_addr = cpu_to_le64(rmem->dma_arr[0]);
4355	5582	}
4356	5583	req.fbo = 0;
4357	5584	/* Association of ring index with doorbell index and MSIX number */
4358	5585	req.logical_id = cpu_to_le16(map_index);
4359	5586
4360	5587	switch (ring_type) {
4361		- case HWRM_RING_ALLOC_TX:
	5588	+ case HWRM_RING_ALLOC_TX: {
	5589	+ struct bnxt_tx_ring_info *txr;
	5590	+
	5591	+ txr = container_of(ring, struct bnxt_tx_ring_info,
	5592	+ tx_ring_struct);
4362	5593	req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
4363	5594	/* Association of transmit ring with completion ring */
4364	5595	grp_info = &bp->grp_info[ring->grp_idx];
4365		- req.cmpl_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id);
	5596	+ req.cmpl_ring_id = cpu_to_le16(bnxt_cp_ring_for_tx(bp, txr));
4366	5597	req.length = cpu_to_le32(bp->tx_ring_mask + 1);
4367	5598	req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
4368	5599	req.queue_id = cpu_to_le16(ring->queue_id);
4369	5600	break;
	5601	+ }
4370	5602	case HWRM_RING_ALLOC_RX:
4371	5603	req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4372	5604	req.length = cpu_to_le32(bp->rx_ring_mask + 1);
	5605	+ if (bp->flags & BNXT_FLAG_CHIP_P5) {
	5606	+ u16 flags = 0;
	5607	+
	5608	+ /* Association of rx ring with stats context */
	5609	+ grp_info = &bp->grp_info[ring->grp_idx];
	5610	+ req.rx_buf_size = cpu_to_le16(bp->rx_buf_use_size);
	5611	+ req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
	5612	+ req.enables \|= cpu_to_le32(
	5613	+ RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
	5614	+ if (NET_IP_ALIGN == 2)
	5615	+ flags = RING_ALLOC_REQ_FLAGS_RX_SOP_PAD;
	5616	+ req.flags = cpu_to_le16(flags);
	5617	+ }
4373	5618	break;
4374	5619	case HWRM_RING_ALLOC_AGG:
4375		- req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
	5620	+ if (bp->flags & BNXT_FLAG_CHIP_P5) {
	5621	+ req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX_AGG;
	5622	+ /* Association of agg ring with rx ring */
	5623	+ grp_info = &bp->grp_info[ring->grp_idx];
	5624	+ req.rx_ring_id = cpu_to_le16(grp_info->rx_fw_ring_id);
	5625	+ req.rx_buf_size = cpu_to_le16(BNXT_RX_PAGE_SIZE);
	5626	+ req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
	5627	+ req.enables \|= cpu_to_le32(
	5628	+ RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID \|
	5629	+ RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
	5630	+ } else {
	5631	+ req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
	5632	+ }
4376	5633	req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
4377	5634	break;
4378	5635	case HWRM_RING_ALLOC_CMPL:
4379	5636	req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;
	5637	+ req.length = cpu_to_le32(bp->cp_ring_mask + 1);
	5638	+ if (bp->flags & BNXT_FLAG_CHIP_P5) {
	5639	+ /* Association of cp ring with nq */
	5640	+ grp_info = &bp->grp_info[map_index];
	5641	+ req.nq_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id);
	5642	+ req.cq_handle = cpu_to_le64(ring->handle);
	5643	+ req.enables \|= cpu_to_le32(
	5644	+ RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID);
	5645	+ } else if (bp->flags & BNXT_FLAG_USING_MSIX) {
	5646	+ req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
	5647	+ }
	5648	+ break;
	5649	+ case HWRM_RING_ALLOC_NQ:
	5650	+ req.ring_type = RING_ALLOC_REQ_RING_TYPE_NQ;
4380	5651	req.length = cpu_to_le32(bp->cp_ring_mask + 1);
4381	5652	if (bp->flags & BNXT_FLAG_USING_MSIX)
4382	5653	req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
..	..	@@ -4426,22 +5697,74 @@
4426	5697	return rc;
4427	5698	}
4428	5699
	5700	+static void bnxt_set_db(struct bnxt bp, struct bnxt_db_info db, u32 ring_type,
	5701	+ u32 map_idx, u32 xid)
	5702	+{
	5703	+ if (bp->flags & BNXT_FLAG_CHIP_P5) {
	5704	+ if (BNXT_PF(bp))
	5705	+ db->doorbell = bp->bar1 + DB_PF_OFFSET_P5;
	5706	+ else
	5707	+ db->doorbell = bp->bar1 + DB_VF_OFFSET_P5;
	5708	+ switch (ring_type) {
	5709	+ case HWRM_RING_ALLOC_TX:
	5710	+ db->db_key64 = DBR_PATH_L2 \| DBR_TYPE_SQ;
	5711	+ break;
	5712	+ case HWRM_RING_ALLOC_RX:
	5713	+ case HWRM_RING_ALLOC_AGG:
	5714	+ db->db_key64 = DBR_PATH_L2 \| DBR_TYPE_SRQ;
	5715	+ break;
	5716	+ case HWRM_RING_ALLOC_CMPL:
	5717	+ db->db_key64 = DBR_PATH_L2;
	5718	+ break;
	5719	+ case HWRM_RING_ALLOC_NQ:
	5720	+ db->db_key64 = DBR_PATH_L2;
	5721	+ break;
	5722	+ }
	5723	+ db->db_key64 \|= (u64)xid << DBR_XID_SFT;
	5724	+ } else {
	5725	+ db->doorbell = bp->bar1 + map_idx * 0x80;
	5726	+ switch (ring_type) {
	5727	+ case HWRM_RING_ALLOC_TX:
	5728	+ db->db_key32 = DB_KEY_TX;
	5729	+ break;
	5730	+ case HWRM_RING_ALLOC_RX:
	5731	+ case HWRM_RING_ALLOC_AGG:
	5732	+ db->db_key32 = DB_KEY_RX;
	5733	+ break;
	5734	+ case HWRM_RING_ALLOC_CMPL:
	5735	+ db->db_key32 = DB_KEY_CP;
	5736	+ break;
	5737	+ }
	5738	+ }
	5739	+}
	5740	+
4429	5741	static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
4430	5742	{
	5743	+ bool agg_rings = !!(bp->flags & BNXT_FLAG_AGG_RINGS);
4431	5744	int i, rc = 0;
	5745	+ u32 type;
4432	5746
	5747	+ if (bp->flags & BNXT_FLAG_CHIP_P5)
	5748	+ type = HWRM_RING_ALLOC_NQ;
	5749	+ else
	5750	+ type = HWRM_RING_ALLOC_CMPL;
4433	5751	for (i = 0; i < bp->cp_nr_rings; i++) {
4434	5752	struct bnxt_napi *bnapi = bp->bnapi[i];
4435	5753	struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4436	5754	struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4437	5755	u32 map_idx = ring->map_idx;
	5756	+ unsigned int vector;
4438	5757
4439		- cpr->cp_doorbell = bp->bar1 + map_idx * 0x80;
4440		- rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL,
4441		- map_idx);
4442		- if (rc)
	5758	+ vector = bp->irq_tbl[map_idx].vector;
	5759	+ disable_irq_nosync(vector);
	5760	+ rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
	5761	+ if (rc) {
	5762	+ enable_irq(vector);
4443	5763	goto err_out;
4444		- BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
	5764	+ }
	5765	+ bnxt_set_db(bp, &cpr->cp_db, type, map_idx, ring->fw_ring_id);
	5766	+ bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
	5767	+ enable_irq(vector);
4445	5768	bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
4446	5769
4447	5770	if (!i) {
..	..	@@ -4451,33 +5774,71 @@
4451	5774	}
4452	5775	}
4453	5776
	5777	+ type = HWRM_RING_ALLOC_TX;
4454	5778	for (i = 0; i < bp->tx_nr_rings; i++) {
4455	5779	struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4456		- struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
4457		- u32 map_idx = i;
	5780	+ struct bnxt_ring_struct *ring;
	5781	+ u32 map_idx;
4458	5782
4459		- rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX,
4460		- map_idx);
	5783	+ if (bp->flags & BNXT_FLAG_CHIP_P5) {
	5784	+ struct bnxt_napi *bnapi = txr->bnapi;
	5785	+ struct bnxt_cp_ring_info cpr, cpr2;
	5786	+ u32 type2 = HWRM_RING_ALLOC_CMPL;
	5787	+
	5788	+ cpr = &bnapi->cp_ring;
	5789	+ cpr2 = cpr->cp_ring_arr[BNXT_TX_HDL];
	5790	+ ring = &cpr2->cp_ring_struct;
	5791	+ ring->handle = BNXT_TX_HDL;
	5792	+ map_idx = bnapi->index;
	5793	+ rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
	5794	+ if (rc)
	5795	+ goto err_out;
	5796	+ bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
	5797	+ ring->fw_ring_id);
	5798	+ bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
	5799	+ }
	5800	+ ring = &txr->tx_ring_struct;
	5801	+ map_idx = i;
	5802	+ rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
4461	5803	if (rc)
4462	5804	goto err_out;
4463		- txr->tx_doorbell = bp->bar1 + map_idx * 0x80;
	5805	+ bnxt_set_db(bp, &txr->tx_db, type, map_idx, ring->fw_ring_id);
4464	5806	}
4465	5807
	5808	+ type = HWRM_RING_ALLOC_RX;
4466	5809	for (i = 0; i < bp->rx_nr_rings; i++) {
4467	5810	struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4468	5811	struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
4469		- u32 map_idx = rxr->bnapi->index;
	5812	+ struct bnxt_napi *bnapi = rxr->bnapi;
	5813	+ u32 map_idx = bnapi->index;
4470	5814
4471		- rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX,
4472		- map_idx);
	5815	+ rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
4473	5816	if (rc)
4474	5817	goto err_out;
4475		- rxr->rx_doorbell = bp->bar1 + map_idx * 0x80;
4476		- writel(DB_KEY_RX \| rxr->rx_prod, rxr->rx_doorbell);
	5818	+ bnxt_set_db(bp, &rxr->rx_db, type, map_idx, ring->fw_ring_id);
	5819	+ /* If we have agg rings, post agg buffers first. */
	5820	+ if (!agg_rings)
	5821	+ bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
4477	5822	bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
	5823	+ if (bp->flags & BNXT_FLAG_CHIP_P5) {
	5824	+ struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
	5825	+ u32 type2 = HWRM_RING_ALLOC_CMPL;
	5826	+ struct bnxt_cp_ring_info *cpr2;
	5827	+
	5828	+ cpr2 = cpr->cp_ring_arr[BNXT_RX_HDL];
	5829	+ ring = &cpr2->cp_ring_struct;
	5830	+ ring->handle = BNXT_RX_HDL;
	5831	+ rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
	5832	+ if (rc)
	5833	+ goto err_out;
	5834	+ bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
	5835	+ ring->fw_ring_id);
	5836	+ bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
	5837	+ }
4478	5838	}
4479	5839
4480		- if (bp->flags & BNXT_FLAG_AGG_RINGS) {
	5840	+ if (agg_rings) {
	5841	+ type = HWRM_RING_ALLOC_AGG;
4481	5842	for (i = 0; i < bp->rx_nr_rings; i++) {
4482	5843	struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4483	5844	struct bnxt_ring_struct *ring =
..	..	@@ -4485,15 +5846,14 @@
4485	5846	u32 grp_idx = ring->grp_idx;
4486	5847	u32 map_idx = grp_idx + bp->rx_nr_rings;
4487	5848
4488		- rc = hwrm_ring_alloc_send_msg(bp, ring,
4489		- HWRM_RING_ALLOC_AGG,
4490		- map_idx);
	5849	+ rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
4491	5850	if (rc)
4492	5851	goto err_out;
4493	5852
4494		- rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80;
4495		- writel(DB_KEY_RX \| rxr->rx_agg_prod,
4496		- rxr->rx_agg_doorbell);
	5853	+ bnxt_set_db(bp, &rxr->rx_agg_db, type, map_idx,
	5854	+ ring->fw_ring_id);
	5855	+ bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
	5856	+ bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
4497	5857	bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
4498	5858	}
4499	5859	}
..	..	@@ -4509,6 +5869,9 @@
4509	5869	struct hwrm_ring_free_input req = {0};
4510	5870	struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
4511	5871	u16 error_code;
	5872	+
	5873	+ if (BNXT_NO_FW_ACCESS(bp))
	5874	+ return 0;
4512	5875
4513	5876	bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
4514	5877	req.ring_type = ring_type;
..	..	@@ -4529,6 +5892,7 @@
4529	5892
4530	5893	static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
4531	5894	{
	5895	+ u32 type;
4532	5896	int i;
4533	5897
4534	5898	if (!bp->bnapi)
..	..	@@ -4537,10 +5901,10 @@
4537	5901	for (i = 0; i < bp->tx_nr_rings; i++) {
4538	5902	struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4539	5903	struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
4540		- u32 grp_idx = txr->bnapi->index;
4541		- u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4542	5904
4543	5905	if (ring->fw_ring_id != INVALID_HW_RING_ID) {
	5906	+ u32 cmpl_ring_id = bnxt_cp_ring_for_tx(bp, txr);
	5907	+
4544	5908	hwrm_ring_free_send_msg(bp, ring,
4545	5909	RING_FREE_REQ_RING_TYPE_TX,
4546	5910	close_path ? cmpl_ring_id :
..	..	@@ -4553,9 +5917,10 @@
4553	5917	struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4554	5918	struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
4555	5919	u32 grp_idx = rxr->bnapi->index;
4556		- u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4557	5920
4558	5921	if (ring->fw_ring_id != INVALID_HW_RING_ID) {
	5922	+ u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr);
	5923	+
4559	5924	hwrm_ring_free_send_msg(bp, ring,
4560	5925	RING_FREE_REQ_RING_TYPE_RX,
4561	5926	close_path ? cmpl_ring_id :
..	..	@@ -4566,15 +5931,19 @@
4566	5931	}
4567	5932	}
4568	5933
	5934	+ if (bp->flags & BNXT_FLAG_CHIP_P5)
	5935	+ type = RING_FREE_REQ_RING_TYPE_RX_AGG;
	5936	+ else
	5937	+ type = RING_FREE_REQ_RING_TYPE_RX;
4569	5938	for (i = 0; i < bp->rx_nr_rings; i++) {
4570	5939	struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4571	5940	struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
4572	5941	u32 grp_idx = rxr->bnapi->index;
4573		- u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4574	5942
4575	5943	if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4576		- hwrm_ring_free_send_msg(bp, ring,
4577		- RING_FREE_REQ_RING_TYPE_RX,
	5944	+ u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr);
	5945	+
	5946	+ hwrm_ring_free_send_msg(bp, ring, type,
4578	5947	close_path ? cmpl_ring_id :
4579	5948	INVALID_HW_RING_ID);
4580	5949	ring->fw_ring_id = INVALID_HW_RING_ID;
..	..	@@ -4589,20 +5958,41 @@
4589	5958	*/
4590	5959	bnxt_disable_int_sync(bp);
4591	5960
	5961	+ if (bp->flags & BNXT_FLAG_CHIP_P5)
	5962	+ type = RING_FREE_REQ_RING_TYPE_NQ;
	5963	+ else
	5964	+ type = RING_FREE_REQ_RING_TYPE_L2_CMPL;
4592	5965	for (i = 0; i < bp->cp_nr_rings; i++) {
4593	5966	struct bnxt_napi *bnapi = bp->bnapi[i];
4594	5967	struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4595		- struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
	5968	+ struct bnxt_ring_struct *ring;
	5969	+ int j;
4596	5970
	5971	+ for (j = 0; j < 2; j++) {
	5972	+ struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
	5973	+
	5974	+ if (cpr2) {
	5975	+ ring = &cpr2->cp_ring_struct;
	5976	+ if (ring->fw_ring_id == INVALID_HW_RING_ID)
	5977	+ continue;
	5978	+ hwrm_ring_free_send_msg(bp, ring,
	5979	+ RING_FREE_REQ_RING_TYPE_L2_CMPL,
	5980	+ INVALID_HW_RING_ID);
	5981	+ ring->fw_ring_id = INVALID_HW_RING_ID;
	5982	+ }
	5983	+ }
	5984	+ ring = &cpr->cp_ring_struct;
4597	5985	if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4598		- hwrm_ring_free_send_msg(bp, ring,
4599		- RING_FREE_REQ_RING_TYPE_L2_CMPL,
	5986	+ hwrm_ring_free_send_msg(bp, ring, type,
4600	5987	INVALID_HW_RING_ID);
4601	5988	ring->fw_ring_id = INVALID_HW_RING_ID;
4602	5989	bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
4603	5990	}
4604	5991	}
4605	5992	}
	5993	+
	5994	+static int bnxt_trim_rings(struct bnxt bp, int rx, int *tx, int max,
	5995	+ bool shared);
4606	5996
4607	5997	static int bnxt_hwrm_get_rings(struct bnxt *bp)
4608	5998	{
..	..	@@ -4620,7 +6010,7 @@
4620	6010	rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4621	6011	if (rc) {
4622	6012	mutex_unlock(&bp->hwrm_cmd_lock);
4623		- return -EIO;
	6013	+ return rc;
4624	6014	}
4625	6015
4626	6016	hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings);
..	..	@@ -4633,8 +6023,25 @@
4633	6023	hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics);
4634	6024	cp = le16_to_cpu(resp->alloc_cmpl_rings);
4635	6025	stats = le16_to_cpu(resp->alloc_stat_ctx);
4636		- cp = min_t(u16, cp, stats);
	6026	+ hw_resc->resv_irqs = cp;
	6027	+ if (bp->flags & BNXT_FLAG_CHIP_P5) {
	6028	+ int rx = hw_resc->resv_rx_rings;
	6029	+ int tx = hw_resc->resv_tx_rings;
	6030	+
	6031	+ if (bp->flags & BNXT_FLAG_AGG_RINGS)
	6032	+ rx >>= 1;
	6033	+ if (cp < (rx + tx)) {
	6034	+ bnxt_trim_rings(bp, &rx, &tx, cp, false);
	6035	+ if (bp->flags & BNXT_FLAG_AGG_RINGS)
	6036	+ rx <<= 1;
	6037	+ hw_resc->resv_rx_rings = rx;
	6038	+ hw_resc->resv_tx_rings = tx;
	6039	+ }
	6040	+ hw_resc->resv_irqs = le16_to_cpu(resp->alloc_msix);
	6041	+ hw_resc->resv_hw_ring_grps = rx;
	6042	+ }
4637	6043	hw_resc->resv_cp_rings = cp;
	6044	+ hw_resc->resv_stat_ctxs = stats;
4638	6045	}
4639	6046	mutex_unlock(&bp->hwrm_cmd_lock);
4640	6047	return 0;
..	..	@@ -4659,10 +6066,12 @@
4659	6066	return rc;
4660	6067	}
4661	6068
	6069	+static bool bnxt_rfs_supported(struct bnxt *bp);
	6070	+
4662	6071	static void
4663	6072	__bnxt_hwrm_reserve_pf_rings(struct bnxt bp, struct hwrm_func_cfg_input req,
4664	6073	int tx_rings, int rx_rings, int ring_grps,
4665		- int cp_rings, int vnics)
	6074	+ int cp_rings, int stats, int vnics)
4666	6075	{
4667	6076	u32 enables = 0;
4668	6077
..	..	@@ -4672,16 +6081,38 @@
4672	6081	req->num_tx_rings = cpu_to_le16(tx_rings);
4673	6082	if (BNXT_NEW_RM(bp)) {
4674	6083	enables \|= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
4675		- enables \|= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS \|
4676		- FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
4677		- enables \|= ring_grps ?
4678		- FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
	6084	+ enables \|= stats ? FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
	6085	+ if (bp->flags & BNXT_FLAG_CHIP_P5) {
	6086	+ enables \|= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_MSIX : 0;
	6087	+ enables \|= tx_rings + ring_grps ?
	6088	+ FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
	6089	+ enables \|= rx_rings ?
	6090	+ FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
	6091	+ } else {
	6092	+ enables \|= cp_rings ?
	6093	+ FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
	6094	+ enables \|= ring_grps ?
	6095	+ FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS \|
	6096	+ FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
	6097	+ }
4679	6098	enables \|= vnics ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0;
4680	6099
4681	6100	req->num_rx_rings = cpu_to_le16(rx_rings);
4682		- req->num_hw_ring_grps = cpu_to_le16(ring_grps);
4683		- req->num_cmpl_rings = cpu_to_le16(cp_rings);
4684		- req->num_stat_ctxs = req->num_cmpl_rings;
	6101	+ if (bp->flags & BNXT_FLAG_CHIP_P5) {
	6102	+ req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
	6103	+ req->num_msix = cpu_to_le16(cp_rings);
	6104	+ req->num_rsscos_ctxs =
	6105	+ cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
	6106	+ } else {
	6107	+ req->num_cmpl_rings = cpu_to_le16(cp_rings);
	6108	+ req->num_hw_ring_grps = cpu_to_le16(ring_grps);
	6109	+ req->num_rsscos_ctxs = cpu_to_le16(1);
	6110	+ if (!(bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
	6111	+ bnxt_rfs_supported(bp))
	6112	+ req->num_rsscos_ctxs =
	6113	+ cpu_to_le16(ring_grps + 1);
	6114	+ }
	6115	+ req->num_stat_ctxs = cpu_to_le16(stats);
4685	6116	req->num_vnics = cpu_to_le16(vnics);
4686	6117	}
4687	6118	req->enables = cpu_to_le32(enables);
..	..	@@ -4691,23 +6122,39 @@
4691	6122	__bnxt_hwrm_reserve_vf_rings(struct bnxt *bp,
4692	6123	struct hwrm_func_vf_cfg_input *req, int tx_rings,
4693	6124	int rx_rings, int ring_grps, int cp_rings,
4694		- int vnics)
	6125	+ int stats, int vnics)
4695	6126	{
4696	6127	u32 enables = 0;
4697	6128
4698	6129	bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_VF_CFG, -1, -1);
4699	6130	enables \|= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
4700		- enables \|= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
4701		- enables \|= cp_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS \|
4702		- FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
4703		- enables \|= ring_grps ? FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
	6131	+ enables \|= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS \|
	6132	+ FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
	6133	+ enables \|= stats ? FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
	6134	+ if (bp->flags & BNXT_FLAG_CHIP_P5) {
	6135	+ enables \|= tx_rings + ring_grps ?
	6136	+ FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
	6137	+ } else {
	6138	+ enables \|= cp_rings ?
	6139	+ FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
	6140	+ enables \|= ring_grps ?
	6141	+ FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
	6142	+ }
4704	6143	enables \|= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0;
	6144	+ enables \|= FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS;
4705	6145
	6146	+ req->num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX);
4706	6147	req->num_tx_rings = cpu_to_le16(tx_rings);
4707	6148	req->num_rx_rings = cpu_to_le16(rx_rings);
4708		- req->num_hw_ring_grps = cpu_to_le16(ring_grps);
4709		- req->num_cmpl_rings = cpu_to_le16(cp_rings);
4710		- req->num_stat_ctxs = req->num_cmpl_rings;
	6149	+ if (bp->flags & BNXT_FLAG_CHIP_P5) {
	6150	+ req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
	6151	+ req->num_rsscos_ctxs = cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
	6152	+ } else {
	6153	+ req->num_cmpl_rings = cpu_to_le16(cp_rings);
	6154	+ req->num_hw_ring_grps = cpu_to_le16(ring_grps);
	6155	+ req->num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX);
	6156	+ }
	6157	+ req->num_stat_ctxs = cpu_to_le16(stats);
4711	6158	req->num_vnics = cpu_to_le16(vnics);
4712	6159
4713	6160	req->enables = cpu_to_le32(enables);
..	..	@@ -4715,30 +6162,29 @@
4715	6162
4716	6163	static int
4717	6164	bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4718		- int ring_grps, int cp_rings, int vnics)
	6165	+ int ring_grps, int cp_rings, int stats, int vnics)
4719	6166	{
4720	6167	struct hwrm_func_cfg_input req = {0};
4721	6168	int rc;
4722	6169
4723	6170	__bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
4724		- cp_rings, vnics);
	6171	+ cp_rings, stats, vnics);
4725	6172	if (!req.enables)
4726	6173	return 0;
4727	6174
4728	6175	rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4729	6176	if (rc)
4730		- return -ENOMEM;
	6177	+ return rc;
4731	6178
4732	6179	if (bp->hwrm_spec_code < 0x10601)
4733	6180	bp->hw_resc.resv_tx_rings = tx_rings;
4734	6181
4735		- rc = bnxt_hwrm_get_rings(bp);
4736		- return rc;
	6182	+ return bnxt_hwrm_get_rings(bp);
4737	6183	}
4738	6184
4739	6185	static int
4740	6186	bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4741		- int ring_grps, int cp_rings, int vnics)
	6187	+ int ring_grps, int cp_rings, int stats, int vnics)
4742	6188	{
4743	6189	struct hwrm_func_vf_cfg_input req = {0};
4744	6190	int rc;
..	..	@@ -4749,29 +6195,26 @@
4749	6195	}
4750	6196
4751	6197	__bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
4752		- cp_rings, vnics);
4753		- req.enables \|= cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS \|
4754		- FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS);
4755		- req.num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX);
4756		- req.num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX);
	6198	+ cp_rings, stats, vnics);
4757	6199	rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4758	6200	if (rc)
4759		- return -ENOMEM;
	6201	+ return rc;
4760	6202
4761		- rc = bnxt_hwrm_get_rings(bp);
4762		- return rc;
	6203	+ return bnxt_hwrm_get_rings(bp);
4763	6204	}
4764	6205
4765	6206	static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp,
4766		- int cp, int vnic)
	6207	+ int cp, int stat, int vnic)
4767	6208	{
4768	6209	if (BNXT_PF(bp))
4769		- return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, vnic);
	6210	+ return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, stat,
	6211	+ vnic);
4770	6212	else
4771		- return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, vnic);
	6213	+ return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, stat,
	6214	+ vnic);
4772	6215	}
4773	6216
4774		-static int bnxt_cp_rings_in_use(struct bnxt *bp)
	6217	+int bnxt_nq_rings_in_use(struct bnxt *bp)
4775	6218	{
4776	6219	int cp = bp->cp_nr_rings;
4777	6220	int ulp_msix, ulp_base;
..	..	@@ -4786,64 +6229,116 @@
4786	6229	return cp;
4787	6230	}
4788	6231
	6232	+static int bnxt_cp_rings_in_use(struct bnxt *bp)
	6233	+{
	6234	+ int cp;
	6235	+
	6236	+ if (!(bp->flags & BNXT_FLAG_CHIP_P5))
	6237	+ return bnxt_nq_rings_in_use(bp);
	6238	+
	6239	+ cp = bp->tx_nr_rings + bp->rx_nr_rings;
	6240	+ return cp;
	6241	+}
	6242	+
	6243	+static int bnxt_get_func_stat_ctxs(struct bnxt *bp)
	6244	+{
	6245	+ int ulp_stat = bnxt_get_ulp_stat_ctxs(bp);
	6246	+ int cp = bp->cp_nr_rings;
	6247	+
	6248	+ if (!ulp_stat)
	6249	+ return cp;
	6250	+
	6251	+ if (bnxt_nq_rings_in_use(bp) > cp + bnxt_get_ulp_msix_num(bp))
	6252	+ return bnxt_get_ulp_msix_base(bp) + ulp_stat;
	6253	+
	6254	+ return cp + ulp_stat;
	6255	+}
	6256	+
	6257	+/* Check if a default RSS map needs to be setup. This function is only
	6258	+ * used on older firmware that does not require reserving RX rings.
	6259	+ */
	6260	+static void bnxt_check_rss_tbl_no_rmgr(struct bnxt *bp)
	6261	+{
	6262	+ struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
	6263	+
	6264	+ /* The RSS map is valid for RX rings set to resv_rx_rings */
	6265	+ if (hw_resc->resv_rx_rings != bp->rx_nr_rings) {
	6266	+ hw_resc->resv_rx_rings = bp->rx_nr_rings;
	6267	+ if (!netif_is_rxfh_configured(bp->dev))
	6268	+ bnxt_set_dflt_rss_indir_tbl(bp);
	6269	+ }
	6270	+}
	6271	+
4789	6272	static bool bnxt_need_reserve_rings(struct bnxt *bp)
4790	6273	{
4791	6274	struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
4792	6275	int cp = bnxt_cp_rings_in_use(bp);
4793		- int rx = bp->rx_nr_rings;
	6276	+ int nq = bnxt_nq_rings_in_use(bp);
	6277	+ int rx = bp->rx_nr_rings, stat;
4794	6278	int vnic = 1, grp = rx;
4795	6279
4796		- if (bp->hwrm_spec_code < 0x10601)
4797		- return false;
4798		-
4799		- if (hw_resc->resv_tx_rings != bp->tx_nr_rings)
	6280	+ if (hw_resc->resv_tx_rings != bp->tx_nr_rings &&
	6281	+ bp->hwrm_spec_code >= 0x10601)
4800	6282	return true;
4801	6283
4802		- if (bp->flags & BNXT_FLAG_RFS)
	6284	+ /* Old firmware does not need RX ring reservations but we still
	6285	+ * need to setup a default RSS map when needed. With new firmware
	6286	+ * we go through RX ring reservations first and then set up the
	6287	+ * RSS map for the successfully reserved RX rings when needed.
	6288	+ */
	6289	+ if (!BNXT_NEW_RM(bp)) {
	6290	+ bnxt_check_rss_tbl_no_rmgr(bp);
	6291	+ return false;
	6292	+ }
	6293	+ if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
4803	6294	vnic = rx + 1;
4804	6295	if (bp->flags & BNXT_FLAG_AGG_RINGS)
4805	6296	rx <<= 1;
4806		- if (BNXT_NEW_RM(bp) &&
4807		- (hw_resc->resv_rx_rings != rx \|\| hw_resc->resv_cp_rings != cp \|\|
4808		- hw_resc->resv_hw_ring_grps != grp \|\| hw_resc->resv_vnics != vnic))
	6297	+ stat = bnxt_get_func_stat_ctxs(bp);
	6298	+ if (hw_resc->resv_rx_rings != rx \|\| hw_resc->resv_cp_rings != cp \|\|
	6299	+ hw_resc->resv_vnics != vnic \|\| hw_resc->resv_stat_ctxs != stat \|\|
	6300	+ (hw_resc->resv_hw_ring_grps != grp &&
	6301	+ !(bp->flags & BNXT_FLAG_CHIP_P5)))
	6302	+ return true;
	6303	+ if ((bp->flags & BNXT_FLAG_CHIP_P5) && BNXT_PF(bp) &&
	6304	+ hw_resc->resv_irqs != nq)
4809	6305	return true;
4810	6306	return false;
4811	6307	}
4812	6308
4813		-static int bnxt_trim_rings(struct bnxt bp, int rx, int *tx, int max,
4814		- bool shared);
4815		-
4816	6309	static int __bnxt_reserve_rings(struct bnxt *bp)
4817	6310	{
4818	6311	struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
4819		- int cp = bnxt_cp_rings_in_use(bp);
	6312	+ int cp = bnxt_nq_rings_in_use(bp);
4820	6313	int tx = bp->tx_nr_rings;
4821	6314	int rx = bp->rx_nr_rings;
4822	6315	int grp, rx_rings, rc;
	6316	+ int vnic = 1, stat;
4823	6317	bool sh = false;
4824		- int vnic = 1;
4825	6318
4826	6319	if (!bnxt_need_reserve_rings(bp))
4827	6320	return 0;
4828	6321
4829	6322	if (bp->flags & BNXT_FLAG_SHARED_RINGS)
4830	6323	sh = true;
4831		- if (bp->flags & BNXT_FLAG_RFS)
	6324	+ if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
4832	6325	vnic = rx + 1;
4833	6326	if (bp->flags & BNXT_FLAG_AGG_RINGS)
4834	6327	rx <<= 1;
4835	6328	grp = bp->rx_nr_rings;
	6329	+ stat = bnxt_get_func_stat_ctxs(bp);
4836	6330
4837		- rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, vnic);
	6331	+ rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, stat, vnic);
4838	6332	if (rc)
4839	6333	return rc;
4840	6334
4841	6335	tx = hw_resc->resv_tx_rings;
4842	6336	if (BNXT_NEW_RM(bp)) {
4843	6337	rx = hw_resc->resv_rx_rings;
4844		- cp = hw_resc->resv_cp_rings;
	6338	+ cp = hw_resc->resv_irqs;
4845	6339	grp = hw_resc->resv_hw_ring_grps;
4846	6340	vnic = hw_resc->resv_vnics;
	6341	+ stat = hw_resc->resv_stat_ctxs;
4847	6342	}
4848	6343
4849	6344	rx_rings = rx;
..	..	@@ -4862,124 +6357,245 @@
4862	6357	}
4863	6358	}
4864	6359	rx_rings = min_t(int, rx_rings, grp);
	6360	+ cp = min_t(int, cp, bp->cp_nr_rings);
	6361	+ if (stat > bnxt_get_ulp_stat_ctxs(bp))
	6362	+ stat -= bnxt_get_ulp_stat_ctxs(bp);
	6363	+ cp = min_t(int, cp, stat);
4865	6364	rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh);
4866	6365	if (bp->flags & BNXT_FLAG_AGG_RINGS)
4867	6366	rx = rx_rings << 1;
4868	6367	cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings;
4869	6368	bp->tx_nr_rings = tx;
	6369	+
	6370	+ /* If we cannot reserve all the RX rings, reset the RSS map only
	6371	+ * if absolutely necessary
	6372	+ */
	6373	+ if (rx_rings != bp->rx_nr_rings) {
	6374	+ netdev_warn(bp->dev, "Able to reserve only %d out of %d requested RX rings\n",
	6375	+ rx_rings, bp->rx_nr_rings);
	6376	+ if ((bp->dev->priv_flags & IFF_RXFH_CONFIGURED) &&
	6377	+ (bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) !=
	6378	+ bnxt_get_nr_rss_ctxs(bp, rx_rings) \|\|
	6379	+ bnxt_get_max_rss_ring(bp) >= rx_rings)) {
	6380	+ netdev_warn(bp->dev, "RSS table entries reverting to default\n");
	6381	+ bp->dev->priv_flags &= ~IFF_RXFH_CONFIGURED;
	6382	+ }
	6383	+ }
4870	6384	bp->rx_nr_rings = rx_rings;
4871	6385	bp->cp_nr_rings = cp;
4872	6386
4873		- if (!tx \|\| !rx \|\| !cp \|\| !grp \|\| !vnic)
	6387	+ if (!tx \|\| !rx \|\| !cp \|\| !grp \|\| !vnic \|\| !stat)
4874	6388	return -ENOMEM;
	6389	+
	6390	+ if (!netif_is_rxfh_configured(bp->dev))
	6391	+ bnxt_set_dflt_rss_indir_tbl(bp);
4875	6392
4876	6393	return rc;
4877	6394	}
4878	6395
4879	6396	static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4880		- int ring_grps, int cp_rings, int vnics)
	6397	+ int ring_grps, int cp_rings, int stats,
	6398	+ int vnics)
4881	6399	{
4882	6400	struct hwrm_func_vf_cfg_input req = {0};
4883	6401	u32 flags;
4884		- int rc;
4885	6402
4886	6403	if (!BNXT_NEW_RM(bp))
4887	6404	return 0;
4888	6405
4889	6406	__bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
4890		- cp_rings, vnics);
	6407	+ cp_rings, stats, vnics);
4891	6408	flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST \|
4892	6409	FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST \|
4893	6410	FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST \|
4894		- FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST \|
4895	6411	FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST \|
4896		- FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST;
	6412	+ FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST \|
	6413	+ FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST;
	6414	+ if (!(bp->flags & BNXT_FLAG_CHIP_P5))
	6415	+ flags \|= FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
4897	6416
4898	6417	req.flags = cpu_to_le32(flags);
4899		- rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4900		- if (rc)
4901		- return -ENOMEM;
4902		- return 0;
	6418	+ return hwrm_send_message_silent(bp, &req, sizeof(req),
	6419	+ HWRM_CMD_TIMEOUT);
4903	6420	}
4904	6421
4905	6422	static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4906		- int ring_grps, int cp_rings, int vnics)
	6423	+ int ring_grps, int cp_rings, int stats,
	6424	+ int vnics)
4907	6425	{
4908	6426	struct hwrm_func_cfg_input req = {0};
4909	6427	u32 flags;
4910		- int rc;
4911	6428
4912	6429	__bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
4913		- cp_rings, vnics);
	6430	+ cp_rings, stats, vnics);
4914	6431	flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST;
4915		- if (BNXT_NEW_RM(bp))
	6432	+ if (BNXT_NEW_RM(bp)) {
4916	6433	flags \|= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST \|
4917	6434	FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST \|
4918		- FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST \|
4919	6435	FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST \|
4920	6436	FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST;
	6437	+ if (bp->flags & BNXT_FLAG_CHIP_P5)
	6438	+ flags \|= FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST \|
	6439	+ FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST;
	6440	+ else
	6441	+ flags \|= FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
	6442	+ }
4921	6443
4922	6444	req.flags = cpu_to_le32(flags);
4923		- rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4924		- if (rc)
4925		- return -ENOMEM;
4926		- return 0;
	6445	+ return hwrm_send_message_silent(bp, &req, sizeof(req),
	6446	+ HWRM_CMD_TIMEOUT);
4927	6447	}
4928	6448
4929	6449	static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4930		- int ring_grps, int cp_rings, int vnics)
	6450	+ int ring_grps, int cp_rings, int stats,
	6451	+ int vnics)
4931	6452	{
4932	6453	if (bp->hwrm_spec_code < 0x10801)
4933	6454	return 0;
4934	6455
4935	6456	if (BNXT_PF(bp))
4936	6457	return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings,
4937		- ring_grps, cp_rings, vnics);
	6458	+ ring_grps, cp_rings, stats,
	6459	+ vnics);
4938	6460
4939	6461	return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps,
4940		- cp_rings, vnics);
	6462	+ cp_rings, stats, vnics);
4941	6463	}
4942	6464
4943		-static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
	6465	+static void bnxt_hwrm_coal_params_qcaps(struct bnxt *bp)
	6466	+{
	6467	+ struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
	6468	+ struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
	6469	+ struct hwrm_ring_aggint_qcaps_input req = {0};
	6470	+ int rc;
	6471	+
	6472	+ coal_cap->cmpl_params = BNXT_LEGACY_COAL_CMPL_PARAMS;
	6473	+ coal_cap->num_cmpl_dma_aggr_max = 63;
	6474	+ coal_cap->num_cmpl_dma_aggr_during_int_max = 63;
	6475	+ coal_cap->cmpl_aggr_dma_tmr_max = 65535;
	6476	+ coal_cap->cmpl_aggr_dma_tmr_during_int_max = 65535;
	6477	+ coal_cap->int_lat_tmr_min_max = 65535;
	6478	+ coal_cap->int_lat_tmr_max_max = 65535;
	6479	+ coal_cap->num_cmpl_aggr_int_max = 65535;
	6480	+ coal_cap->timer_units = 80;
	6481	+
	6482	+ if (bp->hwrm_spec_code < 0x10902)
	6483	+ return;
	6484	+
	6485	+ bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_AGGINT_QCAPS, -1, -1);
	6486	+ mutex_lock(&bp->hwrm_cmd_lock);
	6487	+ rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
	6488	+ if (!rc) {
	6489	+ coal_cap->cmpl_params = le32_to_cpu(resp->cmpl_params);
	6490	+ coal_cap->nq_params = le32_to_cpu(resp->nq_params);
	6491	+ coal_cap->num_cmpl_dma_aggr_max =
	6492	+ le16_to_cpu(resp->num_cmpl_dma_aggr_max);
	6493	+ coal_cap->num_cmpl_dma_aggr_during_int_max =
	6494	+ le16_to_cpu(resp->num_cmpl_dma_aggr_during_int_max);
	6495	+ coal_cap->cmpl_aggr_dma_tmr_max =
	6496	+ le16_to_cpu(resp->cmpl_aggr_dma_tmr_max);
	6497	+ coal_cap->cmpl_aggr_dma_tmr_during_int_max =
	6498	+ le16_to_cpu(resp->cmpl_aggr_dma_tmr_during_int_max);
	6499	+ coal_cap->int_lat_tmr_min_max =
	6500	+ le16_to_cpu(resp->int_lat_tmr_min_max);
	6501	+ coal_cap->int_lat_tmr_max_max =
	6502	+ le16_to_cpu(resp->int_lat_tmr_max_max);
	6503	+ coal_cap->num_cmpl_aggr_int_max =
	6504	+ le16_to_cpu(resp->num_cmpl_aggr_int_max);
	6505	+ coal_cap->timer_units = le16_to_cpu(resp->timer_units);
	6506	+ }
	6507	+ mutex_unlock(&bp->hwrm_cmd_lock);
	6508	+}
	6509	+
	6510	+static u16 bnxt_usec_to_coal_tmr(struct bnxt *bp, u16 usec)
	6511	+{
	6512	+ struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
	6513	+
	6514	+ return usec * 1000 / coal_cap->timer_units;
	6515	+}
	6516	+
	6517	+static void bnxt_hwrm_set_coal_params(struct bnxt *bp,
	6518	+ struct bnxt_coal *hw_coal,
4944	6519	struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4945	6520	{
4946		- u16 val, tmr, max, flags;
	6521	+ struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
	6522	+ u32 cmpl_params = coal_cap->cmpl_params;
	6523	+ u16 val, tmr, max, flags = 0;
4947	6524
4948	6525	max = hw_coal->bufs_per_record * 128;
4949	6526	if (hw_coal->budget)
4950	6527	max = hw_coal->bufs_per_record * hw_coal->budget;
	6528	+ max = min_t(u16, max, coal_cap->num_cmpl_aggr_int_max);
4951	6529
4952	6530	val = clamp_t(u16, hw_coal->coal_bufs, 1, max);
4953	6531	req->num_cmpl_aggr_int = cpu_to_le16(val);
4954	6532
4955		- /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4956		- val = min_t(u16, val, 63);
	6533	+ val = min_t(u16, val, coal_cap->num_cmpl_dma_aggr_max);
4957	6534	req->num_cmpl_dma_aggr = cpu_to_le16(val);
4958	6535
4959		- /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4960		- val = clamp_t(u16, hw_coal->coal_bufs_irq, 1, 63);
	6536	+ val = clamp_t(u16, hw_coal->coal_bufs_irq, 1,
	6537	+ coal_cap->num_cmpl_dma_aggr_during_int_max);
4961	6538	req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val);
4962	6539
4963		- tmr = BNXT_USEC_TO_COAL_TIMER(hw_coal->coal_ticks);
4964		- tmr = max_t(u16, tmr, 1);
	6540	+ tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks);
	6541	+ tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_max_max);
4965	6542	req->int_lat_tmr_max = cpu_to_le16(tmr);
4966	6543
4967	6544	/* min timer set to 1/2 of interrupt timer */
4968		- val = tmr / 2;
4969		- req->int_lat_tmr_min = cpu_to_le16(val);
	6545	+ if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN) {
	6546	+ val = tmr / 2;
	6547	+ val = clamp_t(u16, val, 1, coal_cap->int_lat_tmr_min_max);
	6548	+ req->int_lat_tmr_min = cpu_to_le16(val);
	6549	+ req->enables \|= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
	6550	+ }
4970	6551
4971	6552	/* buf timer set to 1/4 of interrupt timer */
4972		- val = max_t(u16, tmr / 4, 1);
	6553	+ val = clamp_t(u16, tmr / 4, 1, coal_cap->cmpl_aggr_dma_tmr_max);
4973	6554	req->cmpl_aggr_dma_tmr = cpu_to_le16(val);
4974	6555
4975		- tmr = BNXT_USEC_TO_COAL_TIMER(hw_coal->coal_ticks_irq);
4976		- tmr = max_t(u16, tmr, 1);
4977		- req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(tmr);
	6556	+ if (cmpl_params &
	6557	+ RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT) {
	6558	+ tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks_irq);
	6559	+ val = clamp_t(u16, tmr, 1,
	6560	+ coal_cap->cmpl_aggr_dma_tmr_during_int_max);
	6561	+ req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(val);
	6562	+ req->enables \|=
	6563	+ cpu_to_le16(BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE);
	6564	+ }
4978	6565
4979		- flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
4980		- if (hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh)
	6566	+ if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET)
	6567	+ flags \|= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
	6568	+ if ((cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE) &&
	6569	+ hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh)
4981	6570	flags \|= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
4982	6571	req->flags = cpu_to_le16(flags);
	6572	+ req->enables \|= cpu_to_le16(BNXT_COAL_CMPL_ENABLES);
	6573	+}
	6574	+
	6575	+/* Caller holds bp->hwrm_cmd_lock */
	6576	+static int __bnxt_hwrm_set_coal_nq(struct bnxt bp, struct bnxt_napi bnapi,
	6577	+ struct bnxt_coal *hw_coal)
	6578	+{
	6579	+ struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
	6580	+ struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
	6581	+ struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
	6582	+ u32 nq_params = coal_cap->nq_params;
	6583	+ u16 tmr;
	6584	+
	6585	+ if (!(nq_params & RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN))
	6586	+ return 0;
	6587	+
	6588	+ bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
	6589	+ -1, -1);
	6590	+ req.ring_id = cpu_to_le16(cpr->cp_ring_struct.fw_ring_id);
	6591	+ req.flags =
	6592	+ cpu_to_le16(RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ);
	6593	+
	6594	+ tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks) / 2;
	6595	+ tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_min_max);
	6596	+ req.int_lat_tmr_min = cpu_to_le16(tmr);
	6597	+ req.enables \|= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
	6598	+ return _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4983	6599	}
4984	6600
4985	6601	int bnxt_hwrm_set_ring_coal(struct bnxt bp, struct bnxt_napi bnapi)
..	..	@@ -4987,7 +6603,6 @@
4987	6603	struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0};
4988	6604	struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4989	6605	struct bnxt_coal coal;
4990		- unsigned int grp_idx;
4991	6606
4992	6607	/* Tick values in micro seconds.
4993	6608	* 1 coal_buf x bufs_per_record = 1 completion record.
..	..	@@ -5003,10 +6618,9 @@
5003	6618	bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
5004	6619	HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5005	6620
5006		- bnxt_hwrm_set_coal_params(&coal, &req_rx);
	6621	+ bnxt_hwrm_set_coal_params(bp, &coal, &req_rx);
5007	6622
5008		- grp_idx = bnapi->index;
5009		- req_rx.ring_id = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
	6623	+ req_rx.ring_id = cpu_to_le16(bnxt_cp_ring_for_rx(bp, bnapi->rx_ring));
5010	6624
5011	6625	return hwrm_send_message(bp, &req_rx, sizeof(req_rx),
5012	6626	HWRM_CMD_TIMEOUT);
..	..	@@ -5023,38 +6637,64 @@
5023	6637	bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
5024	6638	HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5025	6639
5026		- bnxt_hwrm_set_coal_params(&bp->rx_coal, &req_rx);
5027		- bnxt_hwrm_set_coal_params(&bp->tx_coal, &req_tx);
	6640	+ bnxt_hwrm_set_coal_params(bp, &bp->rx_coal, &req_rx);
	6641	+ bnxt_hwrm_set_coal_params(bp, &bp->tx_coal, &req_tx);
5028	6642
5029	6643	mutex_lock(&bp->hwrm_cmd_lock);
5030	6644	for (i = 0; i < bp->cp_nr_rings; i++) {
5031	6645	struct bnxt_napi *bnapi = bp->bnapi[i];
	6646	+ struct bnxt_coal *hw_coal;
	6647	+ u16 ring_id;
5032	6648
5033	6649	req = &req_rx;
5034		- if (!bnapi->rx_ring)
	6650	+ if (!bnapi->rx_ring) {
	6651	+ ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring);
5035	6652	req = &req_tx;
5036		- req->ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
	6653	+ } else {
	6654	+ ring_id = bnxt_cp_ring_for_rx(bp, bnapi->rx_ring);
	6655	+ }
	6656	+ req->ring_id = cpu_to_le16(ring_id);
5037	6657
5038	6658	rc = _hwrm_send_message(bp, req, sizeof(*req),
5039	6659	HWRM_CMD_TIMEOUT);
5040	6660	if (rc)
5041	6661	break;
	6662	+
	6663	+ if (!(bp->flags & BNXT_FLAG_CHIP_P5))
	6664	+ continue;
	6665	+
	6666	+ if (bnapi->rx_ring && bnapi->tx_ring) {
	6667	+ req = &req_tx;
	6668	+ ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring);
	6669	+ req->ring_id = cpu_to_le16(ring_id);
	6670	+ rc = _hwrm_send_message(bp, req, sizeof(*req),
	6671	+ HWRM_CMD_TIMEOUT);
	6672	+ if (rc)
	6673	+ break;
	6674	+ }
	6675	+ if (bnapi->rx_ring)
	6676	+ hw_coal = &bp->rx_coal;
	6677	+ else
	6678	+ hw_coal = &bp->tx_coal;
	6679	+ __bnxt_hwrm_set_coal_nq(bp, bnapi, hw_coal);
5042	6680	}
5043	6681	mutex_unlock(&bp->hwrm_cmd_lock);
5044	6682	return rc;
5045	6683	}
5046	6684
5047		-static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
	6685	+static void bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
5048	6686	{
5049		- int rc = 0, i;
	6687	+ struct hwrm_stat_ctx_clr_stats_input req0 = {0};
5050	6688	struct hwrm_stat_ctx_free_input req = {0};
	6689	+ int i;
5051	6690
5052	6691	if (!bp->bnapi)
5053		- return 0;
	6692	+ return;
5054	6693
5055	6694	if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5056		- return 0;
	6695	+ return;
5057	6696
	6697	+ bnxt_hwrm_cmd_hdr_init(bp, &req0, HWRM_STAT_CTX_CLR_STATS, -1, -1);
5058	6698	bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
5059	6699
5060	6700	mutex_lock(&bp->hwrm_cmd_lock);
..	..	@@ -5064,17 +6704,18 @@
5064	6704
5065	6705	if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
5066	6706	req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
5067		-
5068		- rc = _hwrm_send_message(bp, &req, sizeof(req),
5069		- HWRM_CMD_TIMEOUT);
5070		- if (rc)
5071		- break;
	6707	+ if (BNXT_FW_MAJ(bp) <= 20) {
	6708	+ req0.stat_ctx_id = req.stat_ctx_id;
	6709	+ _hwrm_send_message(bp, &req0, sizeof(req0),
	6710	+ HWRM_CMD_TIMEOUT);
	6711	+ }
	6712	+ _hwrm_send_message(bp, &req, sizeof(req),
	6713	+ HWRM_CMD_TIMEOUT);
5072	6714
5073	6715	cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
5074	6716	}
5075	6717	}
5076	6718	mutex_unlock(&bp->hwrm_cmd_lock);
5077		- return rc;
5078	6719	}
5079	6720
5080	6721	static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
..	..	@@ -5088,6 +6729,7 @@
5088	6729
5089	6730	bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
5090	6731
	6732	+ req.stats_dma_length = cpu_to_le16(bp->hw_ring_stats_size);
5091	6733	req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
5092	6734
5093	6735	mutex_lock(&bp->hwrm_cmd_lock);
..	..	@@ -5095,7 +6737,7 @@
5095	6737	struct bnxt_napi *bnapi = bp->bnapi[i];
5096	6738	struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5097	6739
5098		- req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
	6740	+ req.stats_dma_addr = cpu_to_le64(cpr->stats.hw_stats_map);
5099	6741
5100	6742	rc = _hwrm_send_message(bp, &req, sizeof(req),
5101	6743	HWRM_CMD_TIMEOUT);
..	..	@@ -5114,6 +6756,7 @@
5114	6756	{
5115	6757	struct hwrm_func_qcfg_input req = {0};
5116	6758	struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
	6759	+ u32 min_db_offset = 0;
5117	6760	u16 flags;
5118	6761	int rc;
5119	6762
..	..	@@ -5129,6 +6772,8 @@
5129	6772	struct bnxt_vf_info *vf = &bp->vf;
5130	6773
5131	6774	vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
	6775	+ } else {
	6776	+ bp->pf.registered_vfs = le16_to_cpu(resp->registered_vfs);
5132	6777	}
5133	6778	#endif
5134	6779	flags = le16_to_cpu(resp->flags);
..	..	@@ -5140,6 +6785,8 @@
5140	6785	}
5141	6786	if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST))
5142	6787	bp->flags \|= BNXT_FLAG_MULTI_HOST;
	6788	+ if (flags & FUNC_QCFG_RESP_FLAGS_RING_MONITOR_ENABLED)
	6789	+ bp->fw_cap \|= BNXT_FW_CAP_RING_MONITOR;
5143	6790
5144	6791	switch (resp->port_partition_type) {
5145	6792	case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
..	..	@@ -5160,9 +6807,479 @@
5160	6807	if (!bp->max_mtu)
5161	6808	bp->max_mtu = BNXT_MAX_MTU;
5162	6809
	6810	+ if (bp->db_size)
	6811	+ goto func_qcfg_exit;
	6812	+
	6813	+ if (bp->flags & BNXT_FLAG_CHIP_P5) {
	6814	+ if (BNXT_PF(bp))
	6815	+ min_db_offset = DB_PF_OFFSET_P5;
	6816	+ else
	6817	+ min_db_offset = DB_VF_OFFSET_P5;
	6818	+ }
	6819	+ bp->db_size = PAGE_ALIGN(le16_to_cpu(resp->l2_doorbell_bar_size_kb) *
	6820	+ 1024);
	6821	+ if (!bp->db_size \|\| bp->db_size > pci_resource_len(bp->pdev, 2) \|\|
	6822	+ bp->db_size <= min_db_offset)
	6823	+ bp->db_size = pci_resource_len(bp->pdev, 2);
	6824	+
5163	6825	func_qcfg_exit:
5164	6826	mutex_unlock(&bp->hwrm_cmd_lock);
5165	6827	return rc;
	6828	+}
	6829	+
	6830	+static int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
	6831	+{
	6832	+ struct hwrm_func_backing_store_qcaps_input req = {0};
	6833	+ struct hwrm_func_backing_store_qcaps_output *resp =
	6834	+ bp->hwrm_cmd_resp_addr;
	6835	+ int rc;
	6836	+
	6837	+ if (bp->hwrm_spec_code < 0x10902 \|\| BNXT_VF(bp) \|\| bp->ctx)
	6838	+ return 0;
	6839	+
	6840	+ bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_QCAPS, -1, -1);
	6841	+ mutex_lock(&bp->hwrm_cmd_lock);
	6842	+ rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
	6843	+ if (!rc) {
	6844	+ struct bnxt_ctx_pg_info *ctx_pg;
	6845	+ struct bnxt_ctx_mem_info *ctx;
	6846	+ int i, tqm_rings;
	6847	+
	6848	+ ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
	6849	+ if (!ctx) {
	6850	+ rc = -ENOMEM;
	6851	+ goto ctx_err;
	6852	+ }
	6853	+ ctx->qp_max_entries = le32_to_cpu(resp->qp_max_entries);
	6854	+ ctx->qp_min_qp1_entries = le16_to_cpu(resp->qp_min_qp1_entries);
	6855	+ ctx->qp_max_l2_entries = le16_to_cpu(resp->qp_max_l2_entries);
	6856	+ ctx->qp_entry_size = le16_to_cpu(resp->qp_entry_size);
	6857	+ ctx->srq_max_l2_entries = le16_to_cpu(resp->srq_max_l2_entries);
	6858	+ ctx->srq_max_entries = le32_to_cpu(resp->srq_max_entries);
	6859	+ ctx->srq_entry_size = le16_to_cpu(resp->srq_entry_size);
	6860	+ ctx->cq_max_l2_entries = le16_to_cpu(resp->cq_max_l2_entries);
	6861	+ ctx->cq_max_entries = le32_to_cpu(resp->cq_max_entries);
	6862	+ ctx->cq_entry_size = le16_to_cpu(resp->cq_entry_size);
	6863	+ ctx->vnic_max_vnic_entries =
	6864	+ le16_to_cpu(resp->vnic_max_vnic_entries);
	6865	+ ctx->vnic_max_ring_table_entries =
	6866	+ le16_to_cpu(resp->vnic_max_ring_table_entries);
	6867	+ ctx->vnic_entry_size = le16_to_cpu(resp->vnic_entry_size);
	6868	+ ctx->stat_max_entries = le32_to_cpu(resp->stat_max_entries);
	6869	+ ctx->stat_entry_size = le16_to_cpu(resp->stat_entry_size);
	6870	+ ctx->tqm_entry_size = le16_to_cpu(resp->tqm_entry_size);
	6871	+ ctx->tqm_min_entries_per_ring =
	6872	+ le32_to_cpu(resp->tqm_min_entries_per_ring);
	6873	+ ctx->tqm_max_entries_per_ring =
	6874	+ le32_to_cpu(resp->tqm_max_entries_per_ring);
	6875	+ ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
	6876	+ if (!ctx->tqm_entries_multiple)
	6877	+ ctx->tqm_entries_multiple = 1;
	6878	+ ctx->mrav_max_entries = le32_to_cpu(resp->mrav_max_entries);
	6879	+ ctx->mrav_entry_size = le16_to_cpu(resp->mrav_entry_size);
	6880	+ ctx->mrav_num_entries_units =
	6881	+ le16_to_cpu(resp->mrav_num_entries_units);
	6882	+ ctx->tim_entry_size = le16_to_cpu(resp->tim_entry_size);
	6883	+ ctx->tim_max_entries = le32_to_cpu(resp->tim_max_entries);
	6884	+ ctx->ctx_kind_initializer = resp->ctx_kind_initializer;
	6885	+ ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
	6886	+ if (!ctx->tqm_fp_rings_count)
	6887	+ ctx->tqm_fp_rings_count = bp->max_q;
	6888	+ else if (ctx->tqm_fp_rings_count > BNXT_MAX_TQM_FP_RINGS)
	6889	+ ctx->tqm_fp_rings_count = BNXT_MAX_TQM_FP_RINGS;
	6890	+
	6891	+ tqm_rings = ctx->tqm_fp_rings_count + BNXT_MAX_TQM_SP_RINGS;
	6892	+ ctx_pg = kcalloc(tqm_rings, sizeof(*ctx_pg), GFP_KERNEL);
	6893	+ if (!ctx_pg) {
	6894	+ kfree(ctx);
	6895	+ rc = -ENOMEM;
	6896	+ goto ctx_err;
	6897	+ }
	6898	+ for (i = 0; i < tqm_rings; i++, ctx_pg++)
	6899	+ ctx->tqm_mem[i] = ctx_pg;
	6900	+ bp->ctx = ctx;
	6901	+ } else {
	6902	+ rc = 0;
	6903	+ }
	6904	+ctx_err:
	6905	+ mutex_unlock(&bp->hwrm_cmd_lock);
	6906	+ return rc;
	6907	+}
	6908	+
	6909	+static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info rmem, u8 pg_attr,
	6910	+ __le64 *pg_dir)
	6911	+{
	6912	+ BNXT_SET_CTX_PAGE_ATTR(*pg_attr);
	6913	+ if (rmem->depth >= 1) {
	6914	+ if (rmem->depth == 2)
	6915	+ *pg_attr \|= 2;
	6916	+ else
	6917	+ *pg_attr \|= 1;
	6918	+ *pg_dir = cpu_to_le64(rmem->pg_tbl_map);
	6919	+ } else {
	6920	+ *pg_dir = cpu_to_le64(rmem->dma_arr[0]);
	6921	+ }
	6922	+}
	6923	+
	6924	+#define FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES \
	6925	+ (FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP \| \
	6926	+ FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ \| \
	6927	+ FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ \| \
	6928	+ FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC \| \
	6929	+ FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT)
	6930	+
	6931	+static int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, u32 enables)
	6932	+{
	6933	+ struct hwrm_func_backing_store_cfg_input req = {0};
	6934	+ struct bnxt_ctx_mem_info *ctx = bp->ctx;
	6935	+ struct bnxt_ctx_pg_info *ctx_pg;
	6936	+ __le32 *num_entries;
	6937	+ __le64 *pg_dir;
	6938	+ u32 flags = 0;
	6939	+ u8 *pg_attr;
	6940	+ u32 ena;
	6941	+ int i;
	6942	+
	6943	+ if (!ctx)
	6944	+ return 0;
	6945	+
	6946	+ bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_CFG, -1, -1);
	6947	+ req.enables = cpu_to_le32(enables);
	6948	+
	6949	+ if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP) {
	6950	+ ctx_pg = &ctx->qp_mem;
	6951	+ req.qp_num_entries = cpu_to_le32(ctx_pg->entries);
	6952	+ req.qp_num_qp1_entries = cpu_to_le16(ctx->qp_min_qp1_entries);
	6953	+ req.qp_num_l2_entries = cpu_to_le16(ctx->qp_max_l2_entries);
	6954	+ req.qp_entry_size = cpu_to_le16(ctx->qp_entry_size);
	6955	+ bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
	6956	+ &req.qpc_pg_size_qpc_lvl,
	6957	+ &req.qpc_page_dir);
	6958	+ }
	6959	+ if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ) {
	6960	+ ctx_pg = &ctx->srq_mem;
	6961	+ req.srq_num_entries = cpu_to_le32(ctx_pg->entries);
	6962	+ req.srq_num_l2_entries = cpu_to_le16(ctx->srq_max_l2_entries);
	6963	+ req.srq_entry_size = cpu_to_le16(ctx->srq_entry_size);
	6964	+ bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
	6965	+ &req.srq_pg_size_srq_lvl,
	6966	+ &req.srq_page_dir);
	6967	+ }
	6968	+ if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ) {
	6969	+ ctx_pg = &ctx->cq_mem;
	6970	+ req.cq_num_entries = cpu_to_le32(ctx_pg->entries);
	6971	+ req.cq_num_l2_entries = cpu_to_le16(ctx->cq_max_l2_entries);
	6972	+ req.cq_entry_size = cpu_to_le16(ctx->cq_entry_size);
	6973	+ bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, &req.cq_pg_size_cq_lvl,
	6974	+ &req.cq_page_dir);
	6975	+ }
	6976	+ if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC) {
	6977	+ ctx_pg = &ctx->vnic_mem;
	6978	+ req.vnic_num_vnic_entries =
	6979	+ cpu_to_le16(ctx->vnic_max_vnic_entries);
	6980	+ req.vnic_num_ring_table_entries =
	6981	+ cpu_to_le16(ctx->vnic_max_ring_table_entries);
	6982	+ req.vnic_entry_size = cpu_to_le16(ctx->vnic_entry_size);
	6983	+ bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
	6984	+ &req.vnic_pg_size_vnic_lvl,
	6985	+ &req.vnic_page_dir);
	6986	+ }
	6987	+ if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) {
	6988	+ ctx_pg = &ctx->stat_mem;
	6989	+ req.stat_num_entries = cpu_to_le32(ctx->stat_max_entries);
	6990	+ req.stat_entry_size = cpu_to_le16(ctx->stat_entry_size);
	6991	+ bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
	6992	+ &req.stat_pg_size_stat_lvl,
	6993	+ &req.stat_page_dir);
	6994	+ }
	6995	+ if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV) {
	6996	+ ctx_pg = &ctx->mrav_mem;
	6997	+ req.mrav_num_entries = cpu_to_le32(ctx_pg->entries);
	6998	+ if (ctx->mrav_num_entries_units)
	6999	+ flags \|=
	7000	+ FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT;
	7001	+ req.mrav_entry_size = cpu_to_le16(ctx->mrav_entry_size);
	7002	+ bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
	7003	+ &req.mrav_pg_size_mrav_lvl,
	7004	+ &req.mrav_page_dir);
	7005	+ }
	7006	+ if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM) {
	7007	+ ctx_pg = &ctx->tim_mem;
	7008	+ req.tim_num_entries = cpu_to_le32(ctx_pg->entries);
	7009	+ req.tim_entry_size = cpu_to_le16(ctx->tim_entry_size);
	7010	+ bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
	7011	+ &req.tim_pg_size_tim_lvl,
	7012	+ &req.tim_page_dir);
	7013	+ }
	7014	+ for (i = 0, num_entries = &req.tqm_sp_num_entries,
	7015	+ pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl,
	7016	+ pg_dir = &req.tqm_sp_page_dir,
	7017	+ ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP;
	7018	+ i < BNXT_MAX_TQM_RINGS;
	7019	+ i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
	7020	+ if (!(enables & ena))
	7021	+ continue;
	7022	+
	7023	+ req.tqm_entry_size = cpu_to_le16(ctx->tqm_entry_size);
	7024	+ ctx_pg = ctx->tqm_mem[i];
	7025	+ *num_entries = cpu_to_le32(ctx_pg->entries);
	7026	+ bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
	7027	+ }
	7028	+ req.flags = cpu_to_le32(flags);
	7029	+ return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
	7030	+}
	7031	+
	7032	+static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
	7033	+ struct bnxt_ctx_pg_info *ctx_pg)
	7034	+{
	7035	+ struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
	7036	+
	7037	+ rmem->page_size = BNXT_PAGE_SIZE;
	7038	+ rmem->pg_arr = ctx_pg->ctx_pg_arr;
	7039	+ rmem->dma_arr = ctx_pg->ctx_dma_arr;
	7040	+ rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
	7041	+ if (rmem->depth >= 1)
	7042	+ rmem->flags \|= BNXT_RMEM_USE_FULL_PAGE_FLAG;
	7043	+ return bnxt_alloc_ring(bp, rmem);
	7044	+}
	7045	+
	7046	+static int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp,
	7047	+ struct bnxt_ctx_pg_info *ctx_pg, u32 mem_size,
	7048	+ u8 depth, bool use_init_val)
	7049	+{
	7050	+ struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
	7051	+ int rc;
	7052	+
	7053	+ if (!mem_size)
	7054	+ return -EINVAL;
	7055	+
	7056	+ ctx_pg->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
	7057	+ if (ctx_pg->nr_pages > MAX_CTX_TOTAL_PAGES) {
	7058	+ ctx_pg->nr_pages = 0;
	7059	+ return -EINVAL;
	7060	+ }
	7061	+ if (ctx_pg->nr_pages > MAX_CTX_PAGES \|\| depth > 1) {
	7062	+ int nr_tbls, i;
	7063	+
	7064	+ rmem->depth = 2;
	7065	+ ctx_pg->ctx_pg_tbl = kcalloc(MAX_CTX_PAGES, sizeof(ctx_pg),
	7066	+ GFP_KERNEL);
	7067	+ if (!ctx_pg->ctx_pg_tbl)
	7068	+ return -ENOMEM;
	7069	+ nr_tbls = DIV_ROUND_UP(ctx_pg->nr_pages, MAX_CTX_PAGES);
	7070	+ rmem->nr_pages = nr_tbls;
	7071	+ rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg);
	7072	+ if (rc)
	7073	+ return rc;
	7074	+ for (i = 0; i < nr_tbls; i++) {
	7075	+ struct bnxt_ctx_pg_info *pg_tbl;
	7076	+
	7077	+ pg_tbl = kzalloc(sizeof(*pg_tbl), GFP_KERNEL);
	7078	+ if (!pg_tbl)
	7079	+ return -ENOMEM;
	7080	+ ctx_pg->ctx_pg_tbl[i] = pg_tbl;
	7081	+ rmem = &pg_tbl->ring_mem;
	7082	+ rmem->pg_tbl = ctx_pg->ctx_pg_arr[i];
	7083	+ rmem->pg_tbl_map = ctx_pg->ctx_dma_arr[i];
	7084	+ rmem->depth = 1;
	7085	+ rmem->nr_pages = MAX_CTX_PAGES;
	7086	+ if (use_init_val)
	7087	+ rmem->init_val = bp->ctx->ctx_kind_initializer;
	7088	+ if (i == (nr_tbls - 1)) {
	7089	+ int rem = ctx_pg->nr_pages % MAX_CTX_PAGES;
	7090	+
	7091	+ if (rem)
	7092	+ rmem->nr_pages = rem;
	7093	+ }
	7094	+ rc = bnxt_alloc_ctx_mem_blk(bp, pg_tbl);
	7095	+ if (rc)
	7096	+ break;
	7097	+ }
	7098	+ } else {
	7099	+ rmem->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
	7100	+ if (rmem->nr_pages > 1 \|\| depth)
	7101	+ rmem->depth = 1;
	7102	+ if (use_init_val)
	7103	+ rmem->init_val = bp->ctx->ctx_kind_initializer;
	7104	+ rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg);
	7105	+ }
	7106	+ return rc;
	7107	+}
	7108	+
	7109	+static void bnxt_free_ctx_pg_tbls(struct bnxt *bp,
	7110	+ struct bnxt_ctx_pg_info *ctx_pg)
	7111	+{
	7112	+ struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
	7113	+
	7114	+ if (rmem->depth > 1 \|\| ctx_pg->nr_pages > MAX_CTX_PAGES \|\|
	7115	+ ctx_pg->ctx_pg_tbl) {
	7116	+ int i, nr_tbls = rmem->nr_pages;
	7117	+
	7118	+ for (i = 0; i < nr_tbls; i++) {
	7119	+ struct bnxt_ctx_pg_info *pg_tbl;
	7120	+ struct bnxt_ring_mem_info *rmem2;
	7121	+
	7122	+ pg_tbl = ctx_pg->ctx_pg_tbl[i];
	7123	+ if (!pg_tbl)
	7124	+ continue;
	7125	+ rmem2 = &pg_tbl->ring_mem;
	7126	+ bnxt_free_ring(bp, rmem2);
	7127	+ ctx_pg->ctx_pg_arr[i] = NULL;
	7128	+ kfree(pg_tbl);
	7129	+ ctx_pg->ctx_pg_tbl[i] = NULL;
	7130	+ }
	7131	+ kfree(ctx_pg->ctx_pg_tbl);
	7132	+ ctx_pg->ctx_pg_tbl = NULL;
	7133	+ }
	7134	+ bnxt_free_ring(bp, rmem);
	7135	+ ctx_pg->nr_pages = 0;
	7136	+}
	7137	+
	7138	+static void bnxt_free_ctx_mem(struct bnxt *bp)
	7139	+{
	7140	+ struct bnxt_ctx_mem_info *ctx = bp->ctx;
	7141	+ int i;
	7142	+
	7143	+ if (!ctx)
	7144	+ return;
	7145	+
	7146	+ if (ctx->tqm_mem[0]) {
	7147	+ for (i = 0; i < ctx->tqm_fp_rings_count + 1; i++)
	7148	+ bnxt_free_ctx_pg_tbls(bp, ctx->tqm_mem[i]);
	7149	+ kfree(ctx->tqm_mem[0]);
	7150	+ ctx->tqm_mem[0] = NULL;
	7151	+ }
	7152	+
	7153	+ bnxt_free_ctx_pg_tbls(bp, &ctx->tim_mem);
	7154	+ bnxt_free_ctx_pg_tbls(bp, &ctx->mrav_mem);
	7155	+ bnxt_free_ctx_pg_tbls(bp, &ctx->stat_mem);
	7156	+ bnxt_free_ctx_pg_tbls(bp, &ctx->vnic_mem);
	7157	+ bnxt_free_ctx_pg_tbls(bp, &ctx->cq_mem);
	7158	+ bnxt_free_ctx_pg_tbls(bp, &ctx->srq_mem);
	7159	+ bnxt_free_ctx_pg_tbls(bp, &ctx->qp_mem);
	7160	+ ctx->flags &= ~BNXT_CTX_FLAG_INITED;
	7161	+}
	7162	+
	7163	+static int bnxt_alloc_ctx_mem(struct bnxt *bp)
	7164	+{
	7165	+ struct bnxt_ctx_pg_info *ctx_pg;
	7166	+ struct bnxt_ctx_mem_info *ctx;
	7167	+ u32 mem_size, ena, entries;
	7168	+ u32 entries_sp, min;
	7169	+ u32 num_mr, num_ah;
	7170	+ u32 extra_srqs = 0;
	7171	+ u32 extra_qps = 0;
	7172	+ u8 pg_lvl = 1;
	7173	+ int i, rc;
	7174	+
	7175	+ rc = bnxt_hwrm_func_backing_store_qcaps(bp);
	7176	+ if (rc) {
	7177	+ netdev_err(bp->dev, "Failed querying context mem capability, rc = %d.\n",
	7178	+ rc);
	7179	+ return rc;
	7180	+ }
	7181	+ ctx = bp->ctx;
	7182	+ if (!ctx \|\| (ctx->flags & BNXT_CTX_FLAG_INITED))
	7183	+ return 0;
	7184	+
	7185	+ if ((bp->flags & BNXT_FLAG_ROCE_CAP) && !is_kdump_kernel()) {
	7186	+ pg_lvl = 2;
	7187	+ extra_qps = 65536;
	7188	+ extra_srqs = 8192;
	7189	+ }
	7190	+
	7191	+ ctx_pg = &ctx->qp_mem;
	7192	+ ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries +
	7193	+ extra_qps;
	7194	+ mem_size = ctx->qp_entry_size * ctx_pg->entries;
	7195	+ rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, true);
	7196	+ if (rc)
	7197	+ return rc;
	7198	+
	7199	+ ctx_pg = &ctx->srq_mem;
	7200	+ ctx_pg->entries = ctx->srq_max_l2_entries + extra_srqs;
	7201	+ mem_size = ctx->srq_entry_size * ctx_pg->entries;
	7202	+ rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, true);
	7203	+ if (rc)
	7204	+ return rc;
	7205	+
	7206	+ ctx_pg = &ctx->cq_mem;
	7207	+ ctx_pg->entries = ctx->cq_max_l2_entries + extra_qps * 2;
	7208	+ mem_size = ctx->cq_entry_size * ctx_pg->entries;
	7209	+ rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, true);
	7210	+ if (rc)
	7211	+ return rc;
	7212	+
	7213	+ ctx_pg = &ctx->vnic_mem;
	7214	+ ctx_pg->entries = ctx->vnic_max_vnic_entries +
	7215	+ ctx->vnic_max_ring_table_entries;
	7216	+ mem_size = ctx->vnic_entry_size * ctx_pg->entries;
	7217	+ rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, true);
	7218	+ if (rc)
	7219	+ return rc;
	7220	+
	7221	+ ctx_pg = &ctx->stat_mem;
	7222	+ ctx_pg->entries = ctx->stat_max_entries;
	7223	+ mem_size = ctx->stat_entry_size * ctx_pg->entries;
	7224	+ rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, true);
	7225	+ if (rc)
	7226	+ return rc;
	7227	+
	7228	+ ena = 0;
	7229	+ if (!(bp->flags & BNXT_FLAG_ROCE_CAP))
	7230	+ goto skip_rdma;
	7231	+
	7232	+ ctx_pg = &ctx->mrav_mem;
	7233	+ /* 128K extra is needed to accommodate static AH context
	7234	+ * allocation by f/w.
	7235	+ */
	7236	+ num_mr = 1024 * 256;
	7237	+ num_ah = 1024 * 128;
	7238	+ ctx_pg->entries = num_mr + num_ah;
	7239	+ mem_size = ctx->mrav_entry_size * ctx_pg->entries;
	7240	+ rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 2, true);
	7241	+ if (rc)
	7242	+ return rc;
	7243	+ ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV;
	7244	+ if (ctx->mrav_num_entries_units)
	7245	+ ctx_pg->entries =
	7246	+ ((num_mr / ctx->mrav_num_entries_units) << 16) \|
	7247	+ (num_ah / ctx->mrav_num_entries_units);
	7248	+
	7249	+ ctx_pg = &ctx->tim_mem;
	7250	+ ctx_pg->entries = ctx->qp_mem.entries;
	7251	+ mem_size = ctx->tim_entry_size * ctx_pg->entries;
	7252	+ rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, false);
	7253	+ if (rc)
	7254	+ return rc;
	7255	+ ena \|= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM;
	7256	+
	7257	+skip_rdma:
	7258	+ min = ctx->tqm_min_entries_per_ring;
	7259	+ entries_sp = ctx->vnic_max_vnic_entries + ctx->qp_max_l2_entries +
	7260	+ 2 * (extra_qps + ctx->qp_min_qp1_entries) + min;
	7261	+ entries_sp = roundup(entries_sp, ctx->tqm_entries_multiple);
	7262	+ entries = ctx->qp_max_l2_entries + 2 * (extra_qps + ctx->qp_min_qp1_entries);
	7263	+ entries = roundup(entries, ctx->tqm_entries_multiple);
	7264	+ entries = clamp_t(u32, entries, min, ctx->tqm_max_entries_per_ring);
	7265	+ for (i = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
	7266	+ ctx_pg = ctx->tqm_mem[i];
	7267	+ ctx_pg->entries = i ? entries : entries_sp;
	7268	+ mem_size = ctx->tqm_entry_size * ctx_pg->entries;
	7269	+ rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, false);
	7270	+ if (rc)
	7271	+ return rc;
	7272	+ ena \|= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP << i;
	7273	+ }
	7274	+ ena \|= FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES;
	7275	+ rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
	7276	+ if (rc) {
	7277	+ netdev_err(bp->dev, "Failed configuring context mem, rc = %d.\n",
	7278	+ rc);
	7279	+ return rc;
	7280	+ }
	7281	+ ctx->flags \|= BNXT_CTX_FLAG_INITED;
	7282	+ return 0;
5166	7283	}
5167	7284
5168	7285	int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all)
..	..	@@ -5176,11 +7293,10 @@
5176	7293	req.fid = cpu_to_le16(0xffff);
5177	7294
5178	7295	mutex_lock(&bp->hwrm_cmd_lock);
5179		- rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5180		- if (rc) {
5181		- rc = -EIO;
	7296	+ rc = _hwrm_send_message_silent(bp, &req, sizeof(req),
	7297	+ HWRM_CMD_TIMEOUT);
	7298	+ if (rc)
5182	7299	goto hwrm_func_resc_qcaps_exit;
5183		- }
5184	7300
5185	7301	hw_resc->max_tx_sch_inputs = le16_to_cpu(resp->max_tx_scheduler_inputs);
5186	7302	if (!all)
..	..	@@ -5203,6 +7319,13 @@
5203	7319	hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx);
5204	7320	hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
5205	7321
	7322	+ if (bp->flags & BNXT_FLAG_CHIP_P5) {
	7323	+ u16 max_msix = le16_to_cpu(resp->max_msix);
	7324	+
	7325	+ hw_resc->max_nqs = max_msix;
	7326	+ hw_resc->max_hw_ring_grps = hw_resc->max_rx_rings;
	7327	+ }
	7328	+
5206	7329	if (BNXT_PF(bp)) {
5207	7330	struct bnxt_pf_info *pf = &bp->pf;
5208	7331
..	..	@@ -5222,7 +7345,7 @@
5222	7345	struct hwrm_func_qcaps_input req = {0};
5223	7346	struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5224	7347	struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5225		- u32 flags;
	7348	+ u32 flags, flags_ext;
5226	7349
5227	7350	bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
5228	7351	req.fid = cpu_to_le16(0xffff);
..	..	@@ -5237,9 +7360,26 @@
5237	7360	bp->flags \|= BNXT_FLAG_ROCEV1_CAP;
5238	7361	if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED)
5239	7362	bp->flags \|= BNXT_FLAG_ROCEV2_CAP;
	7363	+ if (flags & FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED)
	7364	+ bp->fw_cap \|= BNXT_FW_CAP_PCIE_STATS_SUPPORTED;
	7365	+ if (flags & FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE)
	7366	+ bp->fw_cap \|= BNXT_FW_CAP_HOT_RESET;
	7367	+ if (flags & FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED)
	7368	+ bp->fw_cap \|= BNXT_FW_CAP_EXT_STATS_SUPPORTED;
	7369	+ if (flags & FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE)
	7370	+ bp->fw_cap \|= BNXT_FW_CAP_ERROR_RECOVERY;
	7371	+ if (flags & FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD)
	7372	+ bp->fw_cap \|= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
	7373	+ if (!(flags & FUNC_QCAPS_RESP_FLAGS_VLAN_ACCELERATION_TX_DISABLED))
	7374	+ bp->fw_cap \|= BNXT_FW_CAP_VLAN_TX_INSERT;
	7375	+
	7376	+ flags_ext = le32_to_cpu(resp->flags_ext);
	7377	+ if (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_EXT_HW_STATS_SUPPORTED)
	7378	+ bp->fw_cap \|= BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED;
5240	7379
5241	7380	bp->tx_push_thresh = 0;
5242		- if (flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED)
	7381	+ if ((flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED) &&
	7382	+ BNXT_FW_MAJ(bp) > 217)
5243	7383	bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
5244	7384
5245	7385	hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
..	..	@@ -5267,6 +7407,7 @@
5267	7407	pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
5268	7408	pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
5269	7409	pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
	7410	+ bp->flags &= ~BNXT_FLAG_WOL_CAP;
5270	7411	if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED)
5271	7412	bp->flags \|= BNXT_FLAG_WOL_CAP;
5272	7413	} else {
..	..	@@ -5283,6 +7424,8 @@
5283	7424	return rc;
5284	7425	}
5285	7426
	7427	+static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp);
	7428	+
5286	7429	static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
5287	7430	{
5288	7431	int rc;
..	..	@@ -5290,12 +7433,206 @@
5290	7433	rc = __bnxt_hwrm_func_qcaps(bp);
5291	7434	if (rc)
5292	7435	return rc;
	7436	+ rc = bnxt_hwrm_queue_qportcfg(bp);
	7437	+ if (rc) {
	7438	+ netdev_err(bp->dev, "hwrm query qportcfg failure rc: %d\n", rc);
	7439	+ return rc;
	7440	+ }
5293	7441	if (bp->hwrm_spec_code >= 0x10803) {
	7442	+ rc = bnxt_alloc_ctx_mem(bp);
	7443	+ if (rc)
	7444	+ return rc;
5294	7445	rc = bnxt_hwrm_func_resc_qcaps(bp, true);
5295	7446	if (!rc)
5296	7447	bp->fw_cap \|= BNXT_FW_CAP_NEW_RM;
5297	7448	}
5298	7449	return 0;
	7450	+}
	7451	+
	7452	+static int bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(struct bnxt *bp)
	7453	+{
	7454	+ struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
	7455	+ struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp;
	7456	+ int rc = 0;
	7457	+ u32 flags;
	7458	+
	7459	+ if (!(bp->fw_cap & BNXT_FW_CAP_CFA_ADV_FLOW))
	7460	+ return 0;
	7461	+
	7462	+ resp = bp->hwrm_cmd_resp_addr;
	7463	+ bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, -1, -1);
	7464	+
	7465	+ mutex_lock(&bp->hwrm_cmd_lock);
	7466	+ rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
	7467	+ if (rc)
	7468	+ goto hwrm_cfa_adv_qcaps_exit;
	7469	+
	7470	+ flags = le32_to_cpu(resp->flags);
	7471	+ if (flags &
	7472	+ CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED)
	7473	+ bp->fw_cap \|= BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2;
	7474	+
	7475	+hwrm_cfa_adv_qcaps_exit:
	7476	+ mutex_unlock(&bp->hwrm_cmd_lock);
	7477	+ return rc;
	7478	+}
	7479	+
	7480	+static int __bnxt_alloc_fw_health(struct bnxt *bp)
	7481	+{
	7482	+ if (bp->fw_health)
	7483	+ return 0;
	7484	+
	7485	+ bp->fw_health = kzalloc(sizeof(*bp->fw_health), GFP_KERNEL);
	7486	+ if (!bp->fw_health)
	7487	+ return -ENOMEM;
	7488	+
	7489	+ return 0;
	7490	+}
	7491	+
	7492	+static int bnxt_alloc_fw_health(struct bnxt *bp)
	7493	+{
	7494	+ int rc;
	7495	+
	7496	+ if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET) &&
	7497	+ !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
	7498	+ return 0;
	7499	+
	7500	+ rc = __bnxt_alloc_fw_health(bp);
	7501	+ if (rc) {
	7502	+ bp->fw_cap &= ~BNXT_FW_CAP_HOT_RESET;
	7503	+ bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
	7504	+ return rc;
	7505	+ }
	7506	+
	7507	+ return 0;
	7508	+}
	7509	+
	7510	+static void __bnxt_map_fw_health_reg(struct bnxt *bp, u32 reg)
	7511	+{
	7512	+ writel(reg & BNXT_GRC_BASE_MASK, bp->bar0 +
	7513	+ BNXT_GRCPF_REG_WINDOW_BASE_OUT +
	7514	+ BNXT_FW_HEALTH_WIN_MAP_OFF);
	7515	+}
	7516	+
	7517	+static void bnxt_try_map_fw_health_reg(struct bnxt *bp)
	7518	+{
	7519	+ void __iomem *hs;
	7520	+ u32 status_loc;
	7521	+ u32 reg_type;
	7522	+ u32 sig;
	7523	+
	7524	+ __bnxt_map_fw_health_reg(bp, HCOMM_STATUS_STRUCT_LOC);
	7525	+ hs = bp->bar0 + BNXT_FW_HEALTH_WIN_OFF(HCOMM_STATUS_STRUCT_LOC);
	7526	+
	7527	+ sig = readl(hs + offsetof(struct hcomm_status, sig_ver));
	7528	+ if ((sig & HCOMM_STATUS_SIGNATURE_MASK) != HCOMM_STATUS_SIGNATURE_VAL) {
	7529	+ if (bp->fw_health)
	7530	+ bp->fw_health->status_reliable = false;
	7531	+ return;
	7532	+ }
	7533	+
	7534	+ if (__bnxt_alloc_fw_health(bp)) {
	7535	+ netdev_warn(bp->dev, "no memory for firmware status checks\n");
	7536	+ return;
	7537	+ }
	7538	+
	7539	+ status_loc = readl(hs + offsetof(struct hcomm_status, fw_status_loc));
	7540	+ bp->fw_health->regs[BNXT_FW_HEALTH_REG] = status_loc;
	7541	+ reg_type = BNXT_FW_HEALTH_REG_TYPE(status_loc);
	7542	+ if (reg_type == BNXT_FW_HEALTH_REG_TYPE_GRC) {
	7543	+ __bnxt_map_fw_health_reg(bp, status_loc);
	7544	+ bp->fw_health->mapped_regs[BNXT_FW_HEALTH_REG] =
	7545	+ BNXT_FW_HEALTH_WIN_OFF(status_loc);
	7546	+ }
	7547	+
	7548	+ bp->fw_health->status_reliable = true;
	7549	+}
	7550	+
	7551	+static int bnxt_map_fw_health_regs(struct bnxt *bp)
	7552	+{
	7553	+ struct bnxt_fw_health *fw_health = bp->fw_health;
	7554	+ u32 reg_base = 0xffffffff;
	7555	+ int i;
	7556	+
	7557	+ /* Only pre-map the monitoring GRC registers using window 3 */
	7558	+ for (i = 0; i < 4; i++) {
	7559	+ u32 reg = fw_health->regs[i];
	7560	+
	7561	+ if (BNXT_FW_HEALTH_REG_TYPE(reg) != BNXT_FW_HEALTH_REG_TYPE_GRC)
	7562	+ continue;
	7563	+ if (reg_base == 0xffffffff)
	7564	+ reg_base = reg & BNXT_GRC_BASE_MASK;
	7565	+ if ((reg & BNXT_GRC_BASE_MASK) != reg_base)
	7566	+ return -ERANGE;
	7567	+ fw_health->mapped_regs[i] = BNXT_FW_HEALTH_WIN_OFF(reg);
	7568	+ }
	7569	+ if (reg_base == 0xffffffff)
	7570	+ return 0;
	7571	+
	7572	+ __bnxt_map_fw_health_reg(bp, reg_base);
	7573	+ return 0;
	7574	+}
	7575	+
	7576	+static int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
	7577	+{
	7578	+ struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
	7579	+ struct bnxt_fw_health *fw_health = bp->fw_health;
	7580	+ struct hwrm_error_recovery_qcfg_input req = {0};
	7581	+ int rc, i;
	7582	+
	7583	+ if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
	7584	+ return 0;
	7585	+
	7586	+ bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_ERROR_RECOVERY_QCFG, -1, -1);
	7587	+ mutex_lock(&bp->hwrm_cmd_lock);
	7588	+ rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
	7589	+ if (rc)
	7590	+ goto err_recovery_out;
	7591	+ fw_health->flags = le32_to_cpu(resp->flags);
	7592	+ if ((fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) &&
	7593	+ !(bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL)) {
	7594	+ rc = -EINVAL;
	7595	+ goto err_recovery_out;
	7596	+ }
	7597	+ fw_health->polling_dsecs = le32_to_cpu(resp->driver_polling_freq);
	7598	+ fw_health->master_func_wait_dsecs =
	7599	+ le32_to_cpu(resp->master_func_wait_period);
	7600	+ fw_health->normal_func_wait_dsecs =
	7601	+ le32_to_cpu(resp->normal_func_wait_period);
	7602	+ fw_health->post_reset_wait_dsecs =
	7603	+ le32_to_cpu(resp->master_func_wait_period_after_reset);
	7604	+ fw_health->post_reset_max_wait_dsecs =
	7605	+ le32_to_cpu(resp->max_bailout_time_after_reset);
	7606	+ fw_health->regs[BNXT_FW_HEALTH_REG] =
	7607	+ le32_to_cpu(resp->fw_health_status_reg);
	7608	+ fw_health->regs[BNXT_FW_HEARTBEAT_REG] =
	7609	+ le32_to_cpu(resp->fw_heartbeat_reg);
	7610	+ fw_health->regs[BNXT_FW_RESET_CNT_REG] =
	7611	+ le32_to_cpu(resp->fw_reset_cnt_reg);
	7612	+ fw_health->regs[BNXT_FW_RESET_INPROG_REG] =
	7613	+ le32_to_cpu(resp->reset_inprogress_reg);
	7614	+ fw_health->fw_reset_inprog_reg_mask =
	7615	+ le32_to_cpu(resp->reset_inprogress_reg_mask);
	7616	+ fw_health->fw_reset_seq_cnt = resp->reg_array_cnt;
	7617	+ if (fw_health->fw_reset_seq_cnt >= 16) {
	7618	+ rc = -EINVAL;
	7619	+ goto err_recovery_out;
	7620	+ }
	7621	+ for (i = 0; i < fw_health->fw_reset_seq_cnt; i++) {
	7622	+ fw_health->fw_reset_seq_regs[i] =
	7623	+ le32_to_cpu(resp->reset_reg[i]);
	7624	+ fw_health->fw_reset_seq_vals[i] =
	7625	+ le32_to_cpu(resp->reset_reg_val[i]);
	7626	+ fw_health->fw_reset_seq_delay_msec[i] =
	7627	+ resp->delay_after_reset[i];
	7628	+ }
	7629	+err_recovery_out:
	7630	+ mutex_unlock(&bp->hwrm_cmd_lock);
	7631	+ if (!rc)
	7632	+ rc = bnxt_map_fw_health_regs(bp);
	7633	+ if (rc)
	7634	+ bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
	7635	+ return rc;
5299	7636	}
5300	7637
5301	7638	static int bnxt_hwrm_func_reset(struct bnxt *bp)
..	..	@@ -5306,6 +7643,16 @@
5306	7643	req.enables = 0;
5307	7644
5308	7645	return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
	7646	+}
	7647	+
	7648	+static void bnxt_nvm_cfg_ver_get(struct bnxt *bp)
	7649	+{
	7650	+ struct hwrm_nvm_get_dev_info_output nvm_info;
	7651	+
	7652	+ if (!bnxt_hwrm_nvm_get_dev_info(bp, &nvm_info))
	7653	+ snprintf(bp->nvm_cfg_ver, FW_VER_STR_LEN, "%d.%d.%d",
	7654	+ nvm_info.nvm_cfg_ver_maj, nvm_info.nvm_cfg_ver_min,
	7655	+ nvm_info.nvm_cfg_ver_upd);
5309	7656	}
5310	7657
5311	7658	static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
..	..	@@ -5335,13 +7682,15 @@
5335	7682	no_rdma = !(bp->flags & BNXT_FLAG_ROCE_CAP);
5336	7683	qptr = &resp->queue_id0;
5337	7684	for (i = 0, j = 0; i < bp->max_tc; i++) {
5338		- bp->q_info[j].queue_id = *qptr++;
	7685	+ bp->q_info[j].queue_id = *qptr;
	7686	+ bp->q_ids[i] = *qptr++;
5339	7687	bp->q_info[j].queue_profile = *qptr++;
5340	7688	bp->tc_to_qidx[j] = j;
5341	7689	if (!BNXT_CNPQ(bp->q_info[j].queue_profile) \|\|
5342	7690	(no_rdma && BNXT_PF(bp)))
5343	7691	j++;
5344	7692	}
	7693	+ bp->max_q = bp->max_tc;
5345	7694	bp->max_tc = max_t(u8, j, 1);
5346	7695
5347	7696	if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
..	..	@@ -5355,20 +7704,31 @@
5355	7704	return rc;
5356	7705	}
5357	7706
5358		-static int bnxt_hwrm_ver_get(struct bnxt *bp)
	7707	+static int __bnxt_hwrm_ver_get(struct bnxt *bp, bool silent)
5359	7708	{
5360		- int rc;
5361	7709	struct hwrm_ver_get_input req = {0};
5362		- struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
5363		- u32 dev_caps_cfg;
	7710	+ int rc;
5364	7711
5365		- bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
5366	7712	bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
5367	7713	req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
5368	7714	req.hwrm_intf_min = HWRM_VERSION_MINOR;
5369	7715	req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
	7716	+
	7717	+ rc = bnxt_hwrm_do_send_msg(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT,
	7718	+ silent);
	7719	+ return rc;
	7720	+}
	7721	+
	7722	+static int bnxt_hwrm_ver_get(struct bnxt *bp)
	7723	+{
	7724	+ struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
	7725	+ u16 fw_maj, fw_min, fw_bld, fw_rsv;
	7726	+ u32 dev_caps_cfg, hwrm_ver;
	7727	+ int rc, len;
	7728	+
	7729	+ bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
5370	7730	mutex_lock(&bp->hwrm_cmd_lock);
5371		- rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
	7731	+ rc = __bnxt_hwrm_ver_get(bp, false);
5372	7732	if (rc)
5373	7733	goto hwrm_ver_get_exit;
5374	7734
..	..	@@ -5383,18 +7743,58 @@
5383	7743	resp->hwrm_intf_upd_8b);
5384	7744	netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
5385	7745	}
5386		- snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d.%d",
5387		- resp->hwrm_fw_maj_8b, resp->hwrm_fw_min_8b,
5388		- resp->hwrm_fw_bld_8b, resp->hwrm_fw_rsvd_8b);
	7746	+
	7747	+ hwrm_ver = HWRM_VERSION_MAJOR << 16 \| HWRM_VERSION_MINOR << 8 \|
	7748	+ HWRM_VERSION_UPDATE;
	7749	+
	7750	+ if (bp->hwrm_spec_code > hwrm_ver)
	7751	+ snprintf(bp->hwrm_ver_supp, FW_VER_STR_LEN, "%d.%d.%d",
	7752	+ HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR,
	7753	+ HWRM_VERSION_UPDATE);
	7754	+ else
	7755	+ snprintf(bp->hwrm_ver_supp, FW_VER_STR_LEN, "%d.%d.%d",
	7756	+ resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
	7757	+ resp->hwrm_intf_upd_8b);
	7758	+
	7759	+ fw_maj = le16_to_cpu(resp->hwrm_fw_major);
	7760	+ if (bp->hwrm_spec_code > 0x10803 && fw_maj) {
	7761	+ fw_min = le16_to_cpu(resp->hwrm_fw_minor);
	7762	+ fw_bld = le16_to_cpu(resp->hwrm_fw_build);
	7763	+ fw_rsv = le16_to_cpu(resp->hwrm_fw_patch);
	7764	+ len = FW_VER_STR_LEN;
	7765	+ } else {
	7766	+ fw_maj = resp->hwrm_fw_maj_8b;
	7767	+ fw_min = resp->hwrm_fw_min_8b;
	7768	+ fw_bld = resp->hwrm_fw_bld_8b;
	7769	+ fw_rsv = resp->hwrm_fw_rsvd_8b;
	7770	+ len = BC_HWRM_STR_LEN;
	7771	+ }
	7772	+ bp->fw_ver_code = BNXT_FW_VER_CODE(fw_maj, fw_min, fw_bld, fw_rsv);
	7773	+ snprintf(bp->fw_ver_str, len, "%d.%d.%d.%d", fw_maj, fw_min, fw_bld,
	7774	+ fw_rsv);
	7775	+
	7776	+ if (strlen(resp->active_pkg_name)) {
	7777	+ int fw_ver_len = strlen(bp->fw_ver_str);
	7778	+
	7779	+ snprintf(bp->fw_ver_str + fw_ver_len,
	7780	+ FW_VER_STR_LEN - fw_ver_len - 1, "/pkg %s",
	7781	+ resp->active_pkg_name);
	7782	+ bp->fw_cap \|= BNXT_FW_CAP_PKG_VER;
	7783	+ }
5389	7784
5390	7785	bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
5391	7786	if (!bp->hwrm_cmd_timeout)
5392	7787	bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
5393	7788
5394		- if (resp->hwrm_intf_maj_8b >= 1)
	7789	+ if (resp->hwrm_intf_maj_8b >= 1) {
5395	7790	bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
	7791	+ bp->hwrm_max_ext_req_len = le16_to_cpu(resp->max_ext_req_len);
	7792	+ }
	7793	+ if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
	7794	+ bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
5396	7795
5397	7796	bp->chip_num = le16_to_cpu(resp->chip_num);
	7797	+ bp->chip_rev = resp->chip_rev;
5398	7798	if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
5399	7799	!resp->chip_metal)
5400	7800	bp->flags \|= BNXT_FLAG_CHIP_NITRO_A0;
..	..	@@ -5403,6 +7803,21 @@
5403	7803	if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
5404	7804	(dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED))
5405	7805	bp->fw_cap \|= BNXT_FW_CAP_SHORT_CMD;
	7806	+
	7807	+ if (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED)
	7808	+ bp->fw_cap \|= BNXT_FW_CAP_KONG_MB_CHNL;
	7809	+
	7810	+ if (dev_caps_cfg &
	7811	+ VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED)
	7812	+ bp->fw_cap \|= BNXT_FW_CAP_OVS_64BIT_HANDLE;
	7813	+
	7814	+ if (dev_caps_cfg &
	7815	+ VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
	7816	+ bp->fw_cap \|= BNXT_FW_CAP_TRUSTED_VF;
	7817	+
	7818	+ if (dev_caps_cfg &
	7819	+ VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED)
	7820	+ bp->fw_cap \|= BNXT_FW_CAP_CFA_ADV_FLOW;
5406	7821
5407	7822	hwrm_ver_get_exit:
5408	7823	mutex_unlock(&bp->hwrm_cmd_lock);
..	..	@@ -5430,50 +7845,194 @@
5430	7845	return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5431	7846	}
5432	7847
5433		-static int bnxt_hwrm_port_qstats(struct bnxt *bp)
	7848	+static void bnxt_add_one_ctr(u64 hw, u64 *sw, u64 mask)
5434	7849	{
5435		- int rc;
	7850	+ u64 sw_tmp;
	7851	+
	7852	+ hw &= mask;
	7853	+ sw_tmp = (*sw & ~mask) \| hw;
	7854	+ if (hw < (*sw & mask))
	7855	+ sw_tmp += mask + 1;
	7856	+ WRITE_ONCE(*sw, sw_tmp);
	7857	+}
	7858	+
	7859	+static void __bnxt_accumulate_stats(__le64 hw_stats, u64 sw_stats, u64 *masks,
	7860	+ int count, bool ignore_zero)
	7861	+{
	7862	+ int i;
	7863	+
	7864	+ for (i = 0; i < count; i++) {
	7865	+ u64 hw = le64_to_cpu(READ_ONCE(hw_stats[i]));
	7866	+
	7867	+ if (ignore_zero && !hw)
	7868	+ continue;
	7869	+
	7870	+ if (masks[i] == -1ULL)
	7871	+ sw_stats[i] = hw;
	7872	+ else
	7873	+ bnxt_add_one_ctr(hw, &sw_stats[i], masks[i]);
	7874	+ }
	7875	+}
	7876	+
	7877	+static void bnxt_accumulate_stats(struct bnxt_stats_mem *stats)
	7878	+{
	7879	+ if (!stats->hw_stats)
	7880	+ return;
	7881	+
	7882	+ __bnxt_accumulate_stats(stats->hw_stats, stats->sw_stats,
	7883	+ stats->hw_masks, stats->len / 8, false);
	7884	+}
	7885	+
	7886	+static void bnxt_accumulate_all_stats(struct bnxt *bp)
	7887	+{
	7888	+ struct bnxt_stats_mem *ring0_stats;
	7889	+ bool ignore_zero = false;
	7890	+ int i;
	7891	+
	7892	+ /* Chip bug. Counter intermittently becomes 0. */
	7893	+ if (bp->flags & BNXT_FLAG_CHIP_P5)
	7894	+ ignore_zero = true;
	7895	+
	7896	+ for (i = 0; i < bp->cp_nr_rings; i++) {
	7897	+ struct bnxt_napi *bnapi = bp->bnapi[i];
	7898	+ struct bnxt_cp_ring_info *cpr;
	7899	+ struct bnxt_stats_mem *stats;
	7900	+
	7901	+ cpr = &bnapi->cp_ring;
	7902	+ stats = &cpr->stats;
	7903	+ if (!i)
	7904	+ ring0_stats = stats;
	7905	+ __bnxt_accumulate_stats(stats->hw_stats, stats->sw_stats,
	7906	+ ring0_stats->hw_masks,
	7907	+ ring0_stats->len / 8, ignore_zero);
	7908	+ }
	7909	+ if (bp->flags & BNXT_FLAG_PORT_STATS) {
	7910	+ struct bnxt_stats_mem *stats = &bp->port_stats;
	7911	+ __le64 *hw_stats = stats->hw_stats;
	7912	+ u64 *sw_stats = stats->sw_stats;
	7913	+ u64 *masks = stats->hw_masks;
	7914	+ int cnt;
	7915	+
	7916	+ cnt = sizeof(struct rx_port_stats) / 8;
	7917	+ __bnxt_accumulate_stats(hw_stats, sw_stats, masks, cnt, false);
	7918	+
	7919	+ hw_stats += BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
	7920	+ sw_stats += BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
	7921	+ masks += BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
	7922	+ cnt = sizeof(struct tx_port_stats) / 8;
	7923	+ __bnxt_accumulate_stats(hw_stats, sw_stats, masks, cnt, false);
	7924	+ }
	7925	+ if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
	7926	+ bnxt_accumulate_stats(&bp->rx_port_stats_ext);
	7927	+ bnxt_accumulate_stats(&bp->tx_port_stats_ext);
	7928	+ }
	7929	+}
	7930	+
	7931	+static int bnxt_hwrm_port_qstats(struct bnxt *bp, u8 flags)
	7932	+{
5436	7933	struct bnxt_pf_info *pf = &bp->pf;
5437	7934	struct hwrm_port_qstats_input req = {0};
5438	7935
5439	7936	if (!(bp->flags & BNXT_FLAG_PORT_STATS))
5440	7937	return 0;
5441	7938
	7939	+ if (flags && !(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED))
	7940	+ return -EOPNOTSUPP;
	7941	+
	7942	+ req.flags = flags;
5442	7943	bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
5443	7944	req.port_id = cpu_to_le16(pf->port_id);
5444		- req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
5445		- req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
5446		- rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5447		- return rc;
	7945	+ req.tx_stat_host_addr = cpu_to_le64(bp->port_stats.hw_stats_map +
	7946	+ BNXT_TX_PORT_STATS_BYTE_OFFSET);
	7947	+ req.rx_stat_host_addr = cpu_to_le64(bp->port_stats.hw_stats_map);
	7948	+ return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5448	7949	}
5449	7950
5450		-static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp)
	7951	+static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp, u8 flags)
5451	7952	{
	7953	+ struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
	7954	+ struct hwrm_queue_pri2cos_qcfg_input req2 = {0};
5452	7955	struct hwrm_port_qstats_ext_input req = {0};
5453	7956	struct bnxt_pf_info *pf = &bp->pf;
	7957	+ u32 tx_stat_size;
	7958	+ int rc;
5454	7959
5455	7960	if (!(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
5456	7961	return 0;
5457	7962
	7963	+ if (flags && !(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED))
	7964	+ return -EOPNOTSUPP;
	7965	+
5458	7966	bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS_EXT, -1, -1);
	7967	+ req.flags = flags;
5459	7968	req.port_id = cpu_to_le16(pf->port_id);
5460	7969	req.rx_stat_size = cpu_to_le16(sizeof(struct rx_port_stats_ext));
5461		- req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_ext_map);
5462		- return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
	7970	+ req.rx_stat_host_addr = cpu_to_le64(bp->rx_port_stats_ext.hw_stats_map);
	7971	+ tx_stat_size = bp->tx_port_stats_ext.hw_stats ?
	7972	+ sizeof(struct tx_port_stats_ext) : 0;
	7973	+ req.tx_stat_size = cpu_to_le16(tx_stat_size);
	7974	+ req.tx_stat_host_addr = cpu_to_le64(bp->tx_port_stats_ext.hw_stats_map);
	7975	+ mutex_lock(&bp->hwrm_cmd_lock);
	7976	+ rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
	7977	+ if (!rc) {
	7978	+ bp->fw_rx_stats_ext_size = le16_to_cpu(resp->rx_stat_size) / 8;
	7979	+ bp->fw_tx_stats_ext_size = tx_stat_size ?
	7980	+ le16_to_cpu(resp->tx_stat_size) / 8 : 0;
	7981	+ } else {
	7982	+ bp->fw_rx_stats_ext_size = 0;
	7983	+ bp->fw_tx_stats_ext_size = 0;
	7984	+ }
	7985	+ if (flags)
	7986	+ goto qstats_done;
	7987	+
	7988	+ if (bp->fw_tx_stats_ext_size <=
	7989	+ offsetof(struct tx_port_stats_ext, pfc_pri0_tx_duration_us) / 8) {
	7990	+ mutex_unlock(&bp->hwrm_cmd_lock);
	7991	+ bp->pri2cos_valid = 0;
	7992	+ return rc;
	7993	+ }
	7994	+
	7995	+ bnxt_hwrm_cmd_hdr_init(bp, &req2, HWRM_QUEUE_PRI2COS_QCFG, -1, -1);
	7996	+ req2.flags = cpu_to_le32(QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN);
	7997	+
	7998	+ rc = _hwrm_send_message(bp, &req2, sizeof(req2), HWRM_CMD_TIMEOUT);
	7999	+ if (!rc) {
	8000	+ struct hwrm_queue_pri2cos_qcfg_output *resp2;
	8001	+ u8 *pri2cos;
	8002	+ int i, j;
	8003	+
	8004	+ resp2 = bp->hwrm_cmd_resp_addr;
	8005	+ pri2cos = &resp2->pri0_cos_queue_id;
	8006	+ for (i = 0; i < 8; i++) {
	8007	+ u8 queue_id = pri2cos[i];
	8008	+ u8 queue_idx;
	8009	+
	8010	+ /* Per port queue IDs start from 0, 10, 20, etc */
	8011	+ queue_idx = queue_id % 10;
	8012	+ if (queue_idx > BNXT_MAX_QUEUE) {
	8013	+ bp->pri2cos_valid = false;
	8014	+ goto qstats_done;
	8015	+ }
	8016	+ for (j = 0; j < bp->max_q; j++) {
	8017	+ if (bp->q_ids[j] == queue_id)
	8018	+ bp->pri2cos_idx[i] = queue_idx;
	8019	+ }
	8020	+ }
	8021	+ bp->pri2cos_valid = 1;
	8022	+ }
	8023	+qstats_done:
	8024	+ mutex_unlock(&bp->hwrm_cmd_lock);
	8025	+ return rc;
5463	8026	}
5464	8027
5465	8028	static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
5466	8029	{
5467		- if (bp->vxlan_port_cnt) {
	8030	+ if (bp->vxlan_fw_dst_port_id != INVALID_HW_RING_ID)
5468	8031	bnxt_hwrm_tunnel_dst_port_free(
5469	8032	bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5470		- }
5471		- bp->vxlan_port_cnt = 0;
5472		- if (bp->nge_port_cnt) {
	8033	+ if (bp->nge_fw_dst_port_id != INVALID_HW_RING_ID)
5473	8034	bnxt_hwrm_tunnel_dst_port_free(
5474	8035	bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
5475		- }
5476		- bp->nge_port_cnt = 0;
5477	8036	}
5478	8037
5479	8038	static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
..	..	@@ -5483,6 +8042,8 @@
5483	8042
5484	8043	if (set_tpa)
5485	8044	tpa_flags = bp->flags & BNXT_FLAG_TPA;
	8045	+ else if (BNXT_NO_FW_ACCESS(bp))
	8046	+ return 0;
5486	8047	for (i = 0; i < bp->nr_vnics; i++) {
5487	8048	rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
5488	8049	if (rc) {
..	..	@@ -5502,19 +8063,29 @@
5502	8063	bnxt_hwrm_vnic_set_rss(bp, i, false);
5503	8064	}
5504	8065
5505		-static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
5506		- bool irq_re_init)
	8066	+static void bnxt_clear_vnic(struct bnxt *bp)
5507	8067	{
5508		- if (bp->vnic_info) {
5509		- bnxt_hwrm_clear_vnic_filter(bp);
	8068	+ if (!bp->vnic_info)
	8069	+ return;
	8070	+
	8071	+ bnxt_hwrm_clear_vnic_filter(bp);
	8072	+ if (!(bp->flags & BNXT_FLAG_CHIP_P5)) {
5510	8073	/* clear all RSS setting before free vnic ctx */
5511	8074	bnxt_hwrm_clear_vnic_rss(bp);
5512	8075	bnxt_hwrm_vnic_ctx_free(bp);
5513		- /* before free the vnic, undo the vnic tpa settings */
5514		- if (bp->flags & BNXT_FLAG_TPA)
5515		- bnxt_set_tpa(bp, false);
5516		- bnxt_hwrm_vnic_free(bp);
5517	8076	}
	8077	+ /* before free the vnic, undo the vnic tpa settings */
	8078	+ if (bp->flags & BNXT_FLAG_TPA)
	8079	+ bnxt_set_tpa(bp, false);
	8080	+ bnxt_hwrm_vnic_free(bp);
	8081	+ if (bp->flags & BNXT_FLAG_CHIP_P5)
	8082	+ bnxt_hwrm_vnic_ctx_free(bp);
	8083	+}
	8084	+
	8085	+static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
	8086	+ bool irq_re_init)
	8087	+{
	8088	+ bnxt_clear_vnic(bp);
5518	8089	bnxt_hwrm_ring_free(bp, close_path);
5519	8090	bnxt_hwrm_ring_grp_free(bp);
5520	8091	if (irq_re_init) {
..	..	@@ -5526,7 +8097,6 @@
5526	8097	static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode)
5527	8098	{
5528	8099	struct hwrm_func_cfg_input req = {0};
5529		- int rc;
5530	8100
5531	8101	bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
5532	8102	req.fid = cpu_to_le16(0xffff);
..	..	@@ -5537,16 +8107,12 @@
5537	8107	req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA;
5538	8108	else
5539	8109	return -EINVAL;
5540		- rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5541		- if (rc)
5542		- rc = -EIO;
5543		- return rc;
	8110	+ return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5544	8111	}
5545	8112
5546	8113	static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size)
5547	8114	{
5548	8115	struct hwrm_func_cfg_input req = {0};
5549		- int rc;
5550	8116
5551	8117	if (BNXT_VF(bp) \|\| bp->hwrm_spec_code < 0x10803)
5552	8118	return 0;
..	..	@@ -5558,13 +8124,10 @@
5558	8124	if (size == 128)
5559	8125	req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128;
5560	8126
5561		- rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5562		- if (rc)
5563		- rc = -EIO;
5564		- return rc;
	8127	+ return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5565	8128	}
5566	8129
5567		-static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
	8130	+static int __bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
5568	8131	{
5569	8132	struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5570	8133	int rc;
..	..	@@ -5620,10 +8183,60 @@
5620	8183	return rc;
5621	8184	}
5622	8185
	8186	+static int __bnxt_setup_vnic_p5(struct bnxt *bp, u16 vnic_id)
	8187	+{
	8188	+ int rc, i, nr_ctxs;
	8189	+
	8190	+ nr_ctxs = bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings);
	8191	+ for (i = 0; i < nr_ctxs; i++) {
	8192	+ rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, i);
	8193	+ if (rc) {
	8194	+ netdev_err(bp->dev, "hwrm vnic %d ctx %d alloc failure rc: %x\n",
	8195	+ vnic_id, i, rc);
	8196	+ break;
	8197	+ }
	8198	+ bp->rsscos_nr_ctxs++;
	8199	+ }
	8200	+ if (i < nr_ctxs)
	8201	+ return -ENOMEM;
	8202	+
	8203	+ rc = bnxt_hwrm_vnic_set_rss_p5(bp, vnic_id, true);
	8204	+ if (rc) {
	8205	+ netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %d\n",
	8206	+ vnic_id, rc);
	8207	+ return rc;
	8208	+ }
	8209	+ rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
	8210	+ if (rc) {
	8211	+ netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
	8212	+ vnic_id, rc);
	8213	+ return rc;
	8214	+ }
	8215	+ if (bp->flags & BNXT_FLAG_AGG_RINGS) {
	8216	+ rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
	8217	+ if (rc) {
	8218	+ netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
	8219	+ vnic_id, rc);
	8220	+ }
	8221	+ }
	8222	+ return rc;
	8223	+}
	8224	+
	8225	+static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
	8226	+{
	8227	+ if (bp->flags & BNXT_FLAG_CHIP_P5)
	8228	+ return __bnxt_setup_vnic_p5(bp, vnic_id);
	8229	+ else
	8230	+ return __bnxt_setup_vnic(bp, vnic_id);
	8231	+}
	8232	+
5623	8233	static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
5624	8234	{
5625	8235	#ifdef CONFIG_RFS_ACCEL
5626	8236	int i, rc = 0;
	8237	+
	8238	+ if (bp->flags & BNXT_FLAG_CHIP_P5)
	8239	+ return 0;
5627	8240
5628	8241	for (i = 0; i < bp->rx_nr_rings; i++) {
5629	8242	struct bnxt_vnic_info *vnic;
..	..	@@ -5905,9 +8518,17 @@
5905	8518	bp->irq_tbl[0].handler = bnxt_inta;
5906	8519	}
5907	8520
	8521	+static int bnxt_init_int_mode(struct bnxt *bp);
	8522	+
5908	8523	static int bnxt_setup_int_mode(struct bnxt *bp)
5909	8524	{
5910	8525	int rc;
	8526	+
	8527	+ if (!bp->irq_tbl) {
	8528	+ rc = bnxt_init_int_mode(bp);
	8529	+ if (rc \|\| !bp->irq_tbl)
	8530	+ return rc ?: -ENODEV;
	8531	+ }
5911	8532
5912	8533	if (bp->flags & BNXT_FLAG_USING_MSIX)
5913	8534	bnxt_setup_msix(bp);
..	..	@@ -5935,24 +8556,27 @@
5935	8556	return bp->hw_resc.max_stat_ctxs;
5936	8557	}
5937	8558
5938		-void bnxt_set_max_func_stat_ctxs(struct bnxt *bp, unsigned int max)
5939		-{
5940		- bp->hw_resc.max_stat_ctxs = max;
5941		-}
5942		-
5943	8559	unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp)
5944	8560	{
5945	8561	return bp->hw_resc.max_cp_rings;
5946	8562	}
5947	8563
5948		-unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp)
	8564	+static unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp)
5949	8565	{
5950		- return bp->hw_resc.max_cp_rings - bnxt_get_ulp_msix_num(bp);
	8566	+ unsigned int cp = bp->hw_resc.max_cp_rings;
	8567	+
	8568	+ if (!(bp->flags & BNXT_FLAG_CHIP_P5))
	8569	+ cp -= bnxt_get_ulp_msix_num(bp);
	8570	+
	8571	+ return cp;
5951	8572	}
5952	8573
5953	8574	static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)
5954	8575	{
5955	8576	struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
	8577	+
	8578	+ if (bp->flags & BNXT_FLAG_CHIP_P5)
	8579	+ return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_nqs);
5956	8580
5957	8581	return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings);
5958	8582	}
..	..	@@ -5962,6 +8586,22 @@
5962	8586	bp->hw_resc.max_irqs = max_irqs;
5963	8587	}
5964	8588
	8589	+unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp)
	8590	+{
	8591	+ unsigned int cp;
	8592	+
	8593	+ cp = bnxt_get_max_func_cp_rings_for_en(bp);
	8594	+ if (bp->flags & BNXT_FLAG_CHIP_P5)
	8595	+ return cp - bp->rx_nr_rings - bp->tx_nr_rings;
	8596	+ else
	8597	+ return cp - bp->cp_nr_rings;
	8598	+}
	8599	+
	8600	+unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp)
	8601	+{
	8602	+ return bnxt_get_max_func_stat_ctxs(bp) - bnxt_get_func_stat_ctxs(bp);
	8603	+}
	8604	+
5965	8605	int bnxt_get_avail_msix(struct bnxt *bp, int num)
5966	8606	{
5967	8607	int max_cp = bnxt_get_max_func_cp_rings(bp);
..	..	@@ -5969,7 +8609,9 @@
5969	8609	int total_req = bp->cp_nr_rings + num;
5970	8610	int max_idx, avail_msix;
5971	8611
5972		- max_idx = min_t(int, bp->total_irqs, max_cp);
	8612	+ max_idx = bp->total_irqs;
	8613	+ if (!(bp->flags & BNXT_FLAG_CHIP_P5))
	8614	+ max_idx = min_t(int, bp->total_irqs, max_cp);
5973	8615	avail_msix = max_idx - bp->cp_nr_rings;
5974	8616	if (!BNXT_NEW_RM(bp) \|\| avail_msix >= num)
5975	8617	return avail_msix;
..	..	@@ -5987,7 +8629,7 @@
5987	8629	if (!BNXT_NEW_RM(bp))
5988	8630	return bnxt_get_max_func_irqs(bp);
5989	8631
5990		- return bnxt_cp_rings_in_use(bp);
	8632	+ return bnxt_nq_rings_in_use(bp);
5991	8633	}
5992	8634
5993	8635	static int bnxt_init_msix(struct bnxt *bp)
..	..	@@ -6072,7 +8714,7 @@
6072	8714
6073	8715	static int bnxt_init_int_mode(struct bnxt *bp)
6074	8716	{
6075		- int rc = 0;
	8717	+ int rc = -ENODEV;
6076	8718
6077	8719	if (bp->flags & BNXT_FLAG_MSIX_CAP)
6078	8720	rc = bnxt_init_msix(bp);
..	..	@@ -6094,22 +8736,23 @@
6094	8736	bp->flags &= ~BNXT_FLAG_USING_MSIX;
6095	8737	}
6096	8738
6097		-int bnxt_reserve_rings(struct bnxt *bp)
	8739	+int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init)
6098	8740	{
6099	8741	int tcs = netdev_get_num_tc(bp->dev);
6100		- bool reinit_irq = false;
	8742	+ bool irq_cleared = false;
6101	8743	int rc;
6102	8744
6103	8745	if (!bnxt_need_reserve_rings(bp))
6104	8746	return 0;
6105	8747
6106		- if (BNXT_NEW_RM(bp) && (bnxt_get_num_msix(bp) != bp->total_irqs)) {
	8748	+ if (irq_re_init && BNXT_NEW_RM(bp) &&
	8749	+ bnxt_get_num_msix(bp) != bp->total_irqs) {
6107	8750	bnxt_ulp_irq_stop(bp);
6108	8751	bnxt_clear_int_mode(bp);
6109		- reinit_irq = true;
	8752	+ irq_cleared = true;
6110	8753	}
6111	8754	rc = __bnxt_reserve_rings(bp);
6112		- if (reinit_irq) {
	8755	+ if (irq_cleared) {
6113	8756	if (!rc)
6114	8757	rc = bnxt_init_int_mode(bp);
6115	8758	bnxt_ulp_irq_restart(bp, rc);
..	..	@@ -6124,7 +8767,6 @@
6124	8767	bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
6125	8768	return -ENOMEM;
6126	8769	}
6127		- bp->num_stat_ctxs = bp->cp_nr_rings;
6128	8770	return 0;
6129	8771	}
6130	8772
..	..	@@ -6225,10 +8867,9 @@
6225	8867	for (i = 0; i < bp->cp_nr_rings; i++) {
6226	8868	struct bnxt_napi *bnapi = bp->bnapi[i];
6227	8869
6228		- napi_hash_del(&bnapi->napi);
6229		- netif_napi_del(&bnapi->napi);
	8870	+ __netif_napi_del(&bnapi->napi);
6230	8871	}
6231		- /* We called napi_hash_del() before netif_napi_del(), we need
	8872	+ /* We called __netif_napi_del(), we need
6232	8873	* to respect an RCU grace period before freeing napi structures.
6233	8874	*/
6234	8875	synchronize_net();
..	..	@@ -6241,12 +8882,15 @@
6241	8882	struct bnxt_napi *bnapi;
6242	8883
6243	8884	if (bp->flags & BNXT_FLAG_USING_MSIX) {
6244		- if (BNXT_CHIP_TYPE_NITRO_A0(bp))
	8885	+ int (poll_fn)(struct napi_struct , int) = bnxt_poll;
	8886	+
	8887	+ if (bp->flags & BNXT_FLAG_CHIP_P5)
	8888	+ poll_fn = bnxt_poll_p5;
	8889	+ else if (BNXT_CHIP_TYPE_NITRO_A0(bp))
6245	8890	cp_nr_rings--;
6246	8891	for (i = 0; i < cp_nr_rings; i++) {
6247	8892	bnapi = bp->bnapi[i];
6248		- netif_napi_add(bp->dev, &bnapi->napi,
6249		- bnxt_poll, 64);
	8893	+ netif_napi_add(bp->dev, &bnapi->napi, poll_fn, 64);
6250	8894	}
6251	8895	if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
6252	8896	bnapi = bp->bnapi[cp_nr_rings];
..	..	@@ -6280,14 +8924,19 @@
6280	8924	int i;
6281	8925
6282	8926	for (i = 0; i < bp->cp_nr_rings; i++) {
6283		- struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
6284		- bp->bnapi[i]->in_reset = false;
	8927	+ struct bnxt_napi *bnapi = bp->bnapi[i];
	8928	+ struct bnxt_cp_ring_info *cpr;
6285	8929
6286		- if (bp->bnapi[i]->rx_ring) {
	8930	+ cpr = &bnapi->cp_ring;
	8931	+ if (bnapi->in_reset)
	8932	+ cpr->sw_stats.rx.rx_resets++;
	8933	+ bnapi->in_reset = false;
	8934	+
	8935	+ if (bnapi->rx_ring) {
6287	8936	INIT_WORK(&cpr->dim.work, bnxt_dim_work);
6288		- cpr->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
	8937	+ cpr->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
6289	8938	}
6290		- napi_enable(&bp->bnapi[i]->napi);
	8939	+ napi_enable(&bnapi->napi);
6291	8940	}
6292	8941	}
6293	8942
..	..	@@ -6326,6 +8975,30 @@
6326	8975	netif_carrier_on(bp->dev);
6327	8976	}
6328	8977
	8978	+static char bnxt_report_fec(struct bnxt_link_info link_info)
	8979	+{
	8980	+ u8 active_fec = link_info->active_fec_sig_mode &
	8981	+ PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK;
	8982	+
	8983	+ switch (active_fec) {
	8984	+ default:
	8985	+ case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE:
	8986	+ return "None";
	8987	+ case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE:
	8988	+ return "Clause 74 BaseR";
	8989	+ case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE:
	8990	+ return "Clause 91 RS(528,514)";
	8991	+ case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE:
	8992	+ return "Clause 91 RS544_1XN";
	8993	+ case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE:
	8994	+ return "Clause 91 RS(544,514)";
	8995	+ case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE:
	8996	+ return "Clause 91 RS272_1XN";
	8997	+ case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE:
	8998	+ return "Clause 91 RS(272,257)";
	8999	+ }
	9000	+}
	9001	+
6329	9002	static void bnxt_report_link(struct bnxt *bp)
6330	9003	{
6331	9004	if (bp->link_info.link_up) {
..	..	@@ -6360,14 +9033,23 @@
6360	9033	"not active");
6361	9034	fec = bp->link_info.fec_cfg;
6362	9035	if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED))
6363		- netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n",
	9036	+ netdev_info(bp->dev, "FEC autoneg %s encoding: %s\n",
6364	9037	(fec & BNXT_FEC_AUTONEG) ? "on" : "off",
6365		- (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" :
6366		- (fec & BNXT_FEC_ENC_RS) ? "RS" : "None");
	9038	+ bnxt_report_fec(&bp->link_info));
6367	9039	} else {
6368	9040	netif_carrier_off(bp->dev);
6369	9041	netdev_err(bp->dev, "NIC Link is Down\n");
6370	9042	}
	9043	+}
	9044	+
	9045	+static bool bnxt_phy_qcaps_no_speed(struct hwrm_port_phy_qcaps_output *resp)
	9046	+{
	9047	+ if (!resp->supported_speeds_auto_mode &&
	9048	+ !resp->supported_speeds_force_mode &&
	9049	+ !resp->supported_pam4_speeds_auto_mode &&
	9050	+ !resp->supported_pam4_speeds_force_mode)
	9051	+ return true;
	9052	+ return false;
6371	9053	}
6372	9054
6373	9055	static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
..	..	@@ -6377,6 +9059,10 @@
6377	9059	struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6378	9060	struct bnxt_link_info *link_info = &bp->link_info;
6379	9061
	9062	+ bp->flags &= ~BNXT_FLAG_EEE_CAP;
	9063	+ if (bp->test_info)
	9064	+ bp->test_info->flags &= ~(BNXT_TEST_FL_EXT_LPBK \|
	9065	+ BNXT_TEST_FL_AN_PHY_LPBK);
6380	9066	if (bp->hwrm_spec_code < 0x10201)
6381	9067	return 0;
6382	9068
..	..	@@ -6402,9 +9088,35 @@
6402	9088	if (bp->test_info)
6403	9089	bp->test_info->flags \|= BNXT_TEST_FL_EXT_LPBK;
6404	9090	}
	9091	+ if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED) {
	9092	+ if (bp->test_info)
	9093	+ bp->test_info->flags \|= BNXT_TEST_FL_AN_PHY_LPBK;
	9094	+ }
	9095	+ if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED) {
	9096	+ if (BNXT_PF(bp))
	9097	+ bp->fw_cap \|= BNXT_FW_CAP_SHARED_PORT_CFG;
	9098	+ }
	9099	+ if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET)
	9100	+ bp->fw_cap \|= BNXT_FW_CAP_PORT_STATS_NO_RESET;
	9101	+
	9102	+ if (bp->hwrm_spec_code >= 0x10a01) {
	9103	+ if (bnxt_phy_qcaps_no_speed(resp)) {
	9104	+ link_info->phy_state = BNXT_PHY_STATE_DISABLED;
	9105	+ netdev_warn(bp->dev, "Ethernet link disabled\n");
	9106	+ } else if (link_info->phy_state == BNXT_PHY_STATE_DISABLED) {
	9107	+ link_info->phy_state = BNXT_PHY_STATE_ENABLED;
	9108	+ netdev_info(bp->dev, "Ethernet link enabled\n");
	9109	+ /* Phy re-enabled, reprobe the speeds */
	9110	+ link_info->support_auto_speeds = 0;
	9111	+ link_info->support_pam4_auto_speeds = 0;
	9112	+ }
	9113	+ }
6405	9114	if (resp->supported_speeds_auto_mode)
6406	9115	link_info->support_auto_speeds =
6407	9116	le16_to_cpu(resp->supported_speeds_auto_mode);
	9117	+ if (resp->supported_pam4_speeds_auto_mode)
	9118	+ link_info->support_pam4_auto_speeds =
	9119	+ le16_to_cpu(resp->supported_pam4_speeds_auto_mode);
6408	9120
6409	9121	bp->port_count = resp->port_cnt;
6410	9122
..	..	@@ -6413,14 +9125,21 @@
6413	9125	return rc;
6414	9126	}
6415	9127
6416		-static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
	9128	+static bool bnxt_support_dropped(u16 advertising, u16 supported)
	9129	+{
	9130	+ u16 diff = advertising ^ supported;
	9131	+
	9132	+ return ((supported \| diff) != supported);
	9133	+}
	9134	+
	9135	+int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
6417	9136	{
6418	9137	int rc = 0;
6419	9138	struct bnxt_link_info *link_info = &bp->link_info;
6420	9139	struct hwrm_port_phy_qcfg_input req = {0};
6421	9140	struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
6422	9141	u8 link_up = link_info->link_up;
6423		- u16 diff;
	9142	+ bool support_changed = false;
6424	9143
6425	9144	bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
6426	9145
..	..	@@ -6447,10 +9166,17 @@
6447	9166	else
6448	9167	link_info->link_speed = 0;
6449	9168	link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
	9169	+ link_info->force_pam4_link_speed =
	9170	+ le16_to_cpu(resp->force_pam4_link_speed);
6450	9171	link_info->support_speeds = le16_to_cpu(resp->support_speeds);
	9172	+ link_info->support_pam4_speeds = le16_to_cpu(resp->support_pam4_speeds);
6451	9173	link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
	9174	+ link_info->auto_pam4_link_speeds =
	9175	+ le16_to_cpu(resp->auto_pam4_link_speed_mask);
6452	9176	link_info->lp_auto_link_speeds =
6453	9177	le16_to_cpu(resp->link_partner_adv_speeds);
	9178	+ link_info->lp_auto_pam4_link_speeds =
	9179	+ resp->link_partner_pam4_adv_speeds;
6454	9180	link_info->preemphasis = le32_to_cpu(resp->preemphasis);
6455	9181	link_info->phy_ver[0] = resp->phy_maj;
6456	9182	link_info->phy_ver[1] = resp->phy_min;
..	..	@@ -6499,9 +9225,10 @@
6499	9225	}
6500	9226
6501	9227	link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED;
6502		- if (bp->hwrm_spec_code >= 0x10504)
	9228	+ if (bp->hwrm_spec_code >= 0x10504) {
6503	9229	link_info->fec_cfg = le16_to_cpu(resp->fec_cfg);
6504		-
	9230	+ link_info->active_fec_sig_mode = resp->active_fec_signal_mode;
	9231	+ }
6505	9232	/* TODO: need to add more logic to report VF link */
6506	9233	if (chng_link_state) {
6507	9234	if (link_info->phy_link_status == BNXT_LINK_LINK)
..	..	@@ -6516,20 +9243,24 @@
6516	9243	}
6517	9244	mutex_unlock(&bp->hwrm_cmd_lock);
6518	9245
6519		- if (!BNXT_SINGLE_PF(bp))
	9246	+ if (!BNXT_PHY_CFG_ABLE(bp))
6520	9247	return 0;
6521	9248
6522		- diff = link_info->support_auto_speeds ^ link_info->advertising;
6523		- if ((link_info->support_auto_speeds \| diff) !=
6524		- link_info->support_auto_speeds) {
6525		- /* An advertised speed is no longer supported, so we need to
6526		- * update the advertisement settings. Caller holds RTNL
6527		- * so we can modify link settings.
6528		- */
	9249	+ /* Check if any advertised speeds are no longer supported. The caller
	9250	+ * holds the link_lock mutex, so we can modify link_info settings.
	9251	+ */
	9252	+ if (bnxt_support_dropped(link_info->advertising,
	9253	+ link_info->support_auto_speeds)) {
6529	9254	link_info->advertising = link_info->support_auto_speeds;
6530		- if (link_info->autoneg & BNXT_AUTONEG_SPEED)
6531		- bnxt_hwrm_set_link_setting(bp, true, false);
	9255	+ support_changed = true;
6532	9256	}
	9257	+ if (bnxt_support_dropped(link_info->advertising_pam4,
	9258	+ link_info->support_pam4_auto_speeds)) {
	9259	+ link_info->advertising_pam4 = link_info->support_pam4_auto_speeds;
	9260	+ support_changed = true;
	9261	+ }
	9262	+ if (support_changed && (link_info->autoneg & BNXT_AUTONEG_SPEED))
	9263	+ bnxt_hwrm_set_link_setting(bp, true, false);
6533	9264	return 0;
6534	9265	}
6535	9266
..	..	@@ -6588,27 +9319,30 @@
6588	9319	}
6589	9320	}
6590	9321
6591		-static void bnxt_hwrm_set_link_common(struct bnxt *bp,
6592		- struct hwrm_port_phy_cfg_input *req)
	9322	+static void bnxt_hwrm_set_link_common(struct bnxt bp, struct hwrm_port_phy_cfg_input req)
6593	9323	{
6594		- u8 autoneg = bp->link_info.autoneg;
6595		- u16 fw_link_speed = bp->link_info.req_link_speed;
6596		- u16 advertising = bp->link_info.advertising;
6597		-
6598		- if (autoneg & BNXT_AUTONEG_SPEED) {
6599		- req->auto_mode \|=
6600		- PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
6601		-
6602		- req->enables \|= cpu_to_le32(
6603		- PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
6604		- req->auto_link_speed_mask = cpu_to_le16(advertising);
6605		-
	9324	+ if (bp->link_info.autoneg & BNXT_AUTONEG_SPEED) {
	9325	+ req->auto_mode \|= PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
	9326	+ if (bp->link_info.advertising) {
	9327	+ req->enables \|= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
	9328	+ req->auto_link_speed_mask = cpu_to_le16(bp->link_info.advertising);
	9329	+ }
	9330	+ if (bp->link_info.advertising_pam4) {
	9331	+ req->enables \|=
	9332	+ cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK);
	9333	+ req->auto_link_pam4_speed_mask =
	9334	+ cpu_to_le16(bp->link_info.advertising_pam4);
	9335	+ }
6606	9336	req->enables \|= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
6607		- req->flags \|=
6608		- cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
	9337	+ req->flags \|= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
6609	9338	} else {
6610		- req->force_link_speed = cpu_to_le16(fw_link_speed);
6611	9339	req->flags \|= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
	9340	+ if (bp->link_info.req_signal_mode == BNXT_SIG_MODE_PAM4) {
	9341	+ req->force_pam4_link_speed = cpu_to_le16(bp->link_info.req_link_speed);
	9342	+ req->enables \|= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED);
	9343	+ } else {
	9344	+ req->force_link_speed = cpu_to_le16(bp->link_info.req_link_speed);
	9345	+ }
6612	9346	}
6613	9347
6614	9348	/* tell chimp that the setting takes effect immediately */
..	..	@@ -6698,11 +9432,15 @@
6698	9432	return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6699	9433	}
6700	9434
	9435	+static int bnxt_fw_init_one(struct bnxt *bp);
	9436	+
6701	9437	static int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
6702	9438	{
6703	9439	struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
6704	9440	struct hwrm_func_drv_if_change_input req = {0};
	9441	+ bool fw_reset = !bp->irq_tbl;
6705	9442	bool resc_reinit = false;
	9443	+ u32 flags = 0;
6706	9444	int rc;
6707	9445
6708	9446	if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
..	..	@@ -6713,24 +9451,64 @@
6713	9451	req.flags = cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP);
6714	9452	mutex_lock(&bp->hwrm_cmd_lock);
6715	9453	rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6716		- if (!rc && (resp->flags &
6717		- cpu_to_le32(FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE)))
6718		- resc_reinit = true;
	9454	+ if (!rc)
	9455	+ flags = le32_to_cpu(resp->flags);
6719	9456	mutex_unlock(&bp->hwrm_cmd_lock);
	9457	+ if (rc)
	9458	+ return rc;
6720	9459
6721		- if (up && resc_reinit && BNXT_NEW_RM(bp)) {
6722		- struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
	9460	+ if (!up)
	9461	+ return 0;
6723	9462
6724		- rc = bnxt_hwrm_func_resc_qcaps(bp, true);
6725		- hw_resc->resv_cp_rings = 0;
6726		- hw_resc->resv_tx_rings = 0;
6727		- hw_resc->resv_rx_rings = 0;
6728		- hw_resc->resv_hw_ring_grps = 0;
6729		- hw_resc->resv_vnics = 0;
6730		- bp->tx_nr_rings = 0;
6731		- bp->rx_nr_rings = 0;
	9463	+ if (flags & FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE)
	9464	+ resc_reinit = true;
	9465	+ if (flags & FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE)
	9466	+ fw_reset = true;
	9467	+
	9468	+ if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state) && !fw_reset) {
	9469	+ netdev_err(bp->dev, "RESET_DONE not set during FW reset.\n");
	9470	+ set_bit(BNXT_STATE_ABORT_ERR, &bp->state);
	9471	+ return -ENODEV;
6732	9472	}
6733		- return rc;
	9473	+ if (resc_reinit \|\| fw_reset) {
	9474	+ if (fw_reset) {
	9475	+ if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
	9476	+ bnxt_ulp_stop(bp);
	9477	+ bnxt_free_ctx_mem(bp);
	9478	+ kfree(bp->ctx);
	9479	+ bp->ctx = NULL;
	9480	+ bnxt_dcb_free(bp);
	9481	+ rc = bnxt_fw_init_one(bp);
	9482	+ if (rc) {
	9483	+ set_bit(BNXT_STATE_ABORT_ERR, &bp->state);
	9484	+ return rc;
	9485	+ }
	9486	+ bnxt_clear_int_mode(bp);
	9487	+ rc = bnxt_init_int_mode(bp);
	9488	+ if (rc) {
	9489	+ netdev_err(bp->dev, "init int mode failed\n");
	9490	+ return rc;
	9491	+ }
	9492	+ set_bit(BNXT_STATE_FW_RESET_DET, &bp->state);
	9493	+ }
	9494	+ if (BNXT_NEW_RM(bp)) {
	9495	+ struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
	9496	+
	9497	+ rc = bnxt_hwrm_func_resc_qcaps(bp, true);
	9498	+ hw_resc->resv_cp_rings = 0;
	9499	+ hw_resc->resv_stat_ctxs = 0;
	9500	+ hw_resc->resv_irqs = 0;
	9501	+ hw_resc->resv_tx_rings = 0;
	9502	+ hw_resc->resv_rx_rings = 0;
	9503	+ hw_resc->resv_hw_ring_grps = 0;
	9504	+ hw_resc->resv_vnics = 0;
	9505	+ if (!fw_reset) {
	9506	+ bp->tx_nr_rings = 0;
	9507	+ bp->rx_nr_rings = 0;
	9508	+ }
	9509	+ }
	9510	+ }
	9511	+ return 0;
6734	9512	}
6735	9513
6736	9514	static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
..	..	@@ -6740,6 +9518,7 @@
6740	9518	struct bnxt_pf_info *pf = &bp->pf;
6741	9519	int rc;
6742	9520
	9521	+ bp->num_leds = 0;
6743	9522	if (BNXT_VF(bp) \|\| bp->hwrm_spec_code < 0x10601)
6744	9523	return 0;
6745	9524
..	..	@@ -6794,14 +9573,12 @@
6794	9573	int bnxt_hwrm_free_wol_fltr(struct bnxt *bp)
6795	9574	{
6796	9575	struct hwrm_wol_filter_free_input req = {0};
6797		- int rc;
6798	9576
6799	9577	bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1);
6800	9578	req.port_id = cpu_to_le16(bp->pf.port_id);
6801	9579	req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID);
6802	9580	req.wol_filter_id = bp->wol_filter_id;
6803		- rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6804		- return rc;
	9581	+ return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6805	9582	}
6806	9583
6807	9584	static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle)
..	..	@@ -6834,6 +9611,7 @@
6834	9611	{
6835	9612	u16 handle = 0;
6836	9613
	9614	+ bp->wol = 0;
6837	9615	if (!BNXT_PF(bp) \|\| !(bp->flags & BNXT_FLAG_WOL_CAP))
6838	9616	return;
6839	9617
..	..	@@ -6891,6 +9669,9 @@
6891	9669	bnxt_hwmon_close(bp);
6892	9670	return;
6893	9671	}
	9672	+
	9673	+ if (bp->hwmon_dev)
	9674	+ return;
6894	9675
6895	9676	bp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev,
6896	9677	DRV_MODULE_NAME, bp,
..	..	@@ -6961,21 +9742,26 @@
6961	9742	if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
6962	9743	if (BNXT_AUTO_MODE(link_info->auto_mode))
6963	9744	update_link = true;
6964		- if (link_info->req_link_speed != link_info->force_link_speed)
	9745	+ if (link_info->req_signal_mode == BNXT_SIG_MODE_NRZ &&
	9746	+ link_info->req_link_speed != link_info->force_link_speed)
	9747	+ update_link = true;
	9748	+ else if (link_info->req_signal_mode == BNXT_SIG_MODE_PAM4 &&
	9749	+ link_info->req_link_speed != link_info->force_pam4_link_speed)
6965	9750	update_link = true;
6966	9751	if (link_info->req_duplex != link_info->duplex_setting)
6967	9752	update_link = true;
6968	9753	} else {
6969	9754	if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
6970	9755	update_link = true;
6971		- if (link_info->advertising != link_info->auto_link_speeds)
	9756	+ if (link_info->advertising != link_info->auto_link_speeds \|\|
	9757	+ link_info->advertising_pam4 != link_info->auto_pam4_link_speeds)
6972	9758	update_link = true;
6973	9759	}
6974	9760
6975	9761	/* The last close may have shutdown the link, so need to call
6976	9762	* PHY_CFG to bring it back up.
6977	9763	*/
6978		- if (!netif_carrier_ok(bp->dev))
	9764	+ if (!bp->link_info.link_up)
6979	9765	update_link = true;
6980	9766
6981	9767	if (!bnxt_eee_config_ok(bp))
..	..	@@ -7023,10 +9809,10 @@
7023	9809	netdev_err(bp->dev, "Failed to reserve default rings at open\n");
7024	9810	return rc;
7025	9811	}
7026		- rc = bnxt_reserve_rings(bp);
7027		- if (rc)
7028		- return rc;
7029	9812	}
	9813	+ rc = bnxt_reserve_rings(bp, irq_re_init);
	9814	+ if (rc)
	9815	+ return rc;
7030	9816	if ((bp->flags & BNXT_FLAG_RFS) &&
7031	9817	!(bp->flags & BNXT_FLAG_USING_MSIX)) {
7032	9818	/* disable RFS if falling back to INTA */
..	..	@@ -7073,7 +9859,7 @@
7073	9859	}
7074	9860
7075	9861	if (irq_re_init)
7076		- udp_tunnel_get_rx_info(bp->dev);
	9862	+ udp_tunnel_nic_reset_ntf(bp->dev);
7077	9863
7078	9864	set_bit(BNXT_STATE_OPEN, &bp->state);
7079	9865	bnxt_enable_int(bp);
..	..	@@ -7103,7 +9889,10 @@
7103	9889	{
7104	9890	int rc = 0;
7105	9891
7106		- rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
	9892	+ if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state))
	9893	+ rc = -EIO;
	9894	+ if (!rc)
	9895	+ rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
7107	9896	if (rc) {
7108	9897	netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
7109	9898	dev_close(bp->dev);
..	..	@@ -7118,6 +9907,12 @@
7118	9907	int bnxt_half_open_nic(struct bnxt *bp)
7119	9908	{
7120	9909	int rc = 0;
	9910	+
	9911	+ if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) {
	9912	+ netdev_err(bp->dev, "A previous firmware reset has not completed, aborting half open\n");
	9913	+ rc = -ENODEV;
	9914	+ goto half_open_err;
	9915	+ }
7121	9916
7122	9917	rc = bnxt_alloc_mem(bp, false);
7123	9918	if (rc) {
..	..	@@ -7148,17 +9943,42 @@
7148	9943	bnxt_free_mem(bp, false);
7149	9944	}
7150	9945
	9946	+static void bnxt_reenable_sriov(struct bnxt *bp)
	9947	+{
	9948	+ if (BNXT_PF(bp)) {
	9949	+ struct bnxt_pf_info *pf = &bp->pf;
	9950	+ int n = pf->active_vfs;
	9951	+
	9952	+ if (n)
	9953	+ bnxt_cfg_hw_sriov(bp, &n, true);
	9954	+ }
	9955	+}
	9956	+
7151	9957	static int bnxt_open(struct net_device *dev)
7152	9958	{
7153	9959	struct bnxt *bp = netdev_priv(dev);
7154	9960	int rc;
7155	9961
7156		- bnxt_hwrm_if_change(bp, true);
7157		- rc = __bnxt_open_nic(bp, true, true);
7158		- if (rc)
7159		- bnxt_hwrm_if_change(bp, false);
	9962	+ if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) {
	9963	+ netdev_err(bp->dev, "A previous firmware reset did not complete, aborting\n");
	9964	+ return -ENODEV;
	9965	+ }
7160	9966
7161		- bnxt_hwmon_open(bp);
	9967	+ rc = bnxt_hwrm_if_change(bp, true);
	9968	+ if (rc)
	9969	+ return rc;
	9970	+ rc = __bnxt_open_nic(bp, true, true);
	9971	+ if (rc) {
	9972	+ bnxt_hwrm_if_change(bp, false);
	9973	+ } else {
	9974	+ if (test_and_clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state)) {
	9975	+ if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
	9976	+ bnxt_ulp_start(bp, 0);
	9977	+ bnxt_reenable_sriov(bp);
	9978	+ }
	9979	+ }
	9980	+ bnxt_hwmon_open(bp);
	9981	+ }
7162	9982
7163	9983	return rc;
7164	9984	}
..	..	@@ -7211,6 +10031,18 @@
7211	10031	{
7212	10032	int rc = 0;
7213	10033
	10034	+ if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
	10035	+ /* If we get here, it means firmware reset is in progress
	10036	+ * while we are trying to close. We can safely proceed with
	10037	+ * the close because we are holding rtnl_lock(). Some firmware
	10038	+ * messages may fail as we proceed to close. We set the
	10039	+ * ABORT_ERR flag here so that the FW reset thread will later
	10040	+ * abort when it gets the rtnl_lock() and sees the flag.
	10041	+ */
	10042	+ netdev_warn(bp->dev, "FW reset in progress during close, FW reset will be aborted\n");
	10043	+ set_bit(BNXT_STATE_ABORT_ERR, &bp->state);
	10044	+ }
	10045	+
7214	10046	#ifdef CONFIG_BNXT_SRIOV
7215	10047	if (bp->sriov_cfg) {
7216	10048	rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
..	..	@@ -7235,24 +10067,88 @@
7235	10067	return 0;
7236	10068	}
7237	10069
	10070	+static int bnxt_hwrm_port_phy_read(struct bnxt *bp, u16 phy_addr, u16 reg,
	10071	+ u16 *val)
	10072	+{
	10073	+ struct hwrm_port_phy_mdio_read_output *resp = bp->hwrm_cmd_resp_addr;
	10074	+ struct hwrm_port_phy_mdio_read_input req = {0};
	10075	+ int rc;
	10076	+
	10077	+ if (bp->hwrm_spec_code < 0x10a00)
	10078	+ return -EOPNOTSUPP;
	10079	+
	10080	+ bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_READ, -1, -1);
	10081	+ req.port_id = cpu_to_le16(bp->pf.port_id);
	10082	+ req.phy_addr = phy_addr;
	10083	+ req.reg_addr = cpu_to_le16(reg & 0x1f);
	10084	+ if (mdio_phy_id_is_c45(phy_addr)) {
	10085	+ req.cl45_mdio = 1;
	10086	+ req.phy_addr = mdio_phy_id_prtad(phy_addr);
	10087	+ req.dev_addr = mdio_phy_id_devad(phy_addr);
	10088	+ req.reg_addr = cpu_to_le16(reg);
	10089	+ }
	10090	+
	10091	+ mutex_lock(&bp->hwrm_cmd_lock);
	10092	+ rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
	10093	+ if (!rc)
	10094	+ *val = le16_to_cpu(resp->reg_data);
	10095	+ mutex_unlock(&bp->hwrm_cmd_lock);
	10096	+ return rc;
	10097	+}
	10098	+
	10099	+static int bnxt_hwrm_port_phy_write(struct bnxt *bp, u16 phy_addr, u16 reg,
	10100	+ u16 val)
	10101	+{
	10102	+ struct hwrm_port_phy_mdio_write_input req = {0};
	10103	+
	10104	+ if (bp->hwrm_spec_code < 0x10a00)
	10105	+ return -EOPNOTSUPP;
	10106	+
	10107	+ bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_WRITE, -1, -1);
	10108	+ req.port_id = cpu_to_le16(bp->pf.port_id);
	10109	+ req.phy_addr = phy_addr;
	10110	+ req.reg_addr = cpu_to_le16(reg & 0x1f);
	10111	+ if (mdio_phy_id_is_c45(phy_addr)) {
	10112	+ req.cl45_mdio = 1;
	10113	+ req.phy_addr = mdio_phy_id_prtad(phy_addr);
	10114	+ req.dev_addr = mdio_phy_id_devad(phy_addr);
	10115	+ req.reg_addr = cpu_to_le16(reg);
	10116	+ }
	10117	+ req.reg_data = cpu_to_le16(val);
	10118	+
	10119	+ return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
	10120	+}
	10121	+
7238	10122	/* rtnl_lock held */
7239	10123	static int bnxt_ioctl(struct net_device dev, struct ifreq ifr, int cmd)
7240	10124	{
	10125	+ struct mii_ioctl_data *mdio = if_mii(ifr);
	10126	+ struct bnxt *bp = netdev_priv(dev);
	10127	+ int rc;
	10128	+
7241	10129	switch (cmd) {
7242	10130	case SIOCGMIIPHY:
7243		- /* fallthru */
	10131	+ mdio->phy_id = bp->link_info.phy_addr;
	10132	+
	10133	+ fallthrough;
7244	10134	case SIOCGMIIREG: {
	10135	+ u16 mii_regval = 0;
	10136	+
7245	10137	if (!netif_running(dev))
7246	10138	return -EAGAIN;
7247	10139
7248		- return 0;
	10140	+ rc = bnxt_hwrm_port_phy_read(bp, mdio->phy_id, mdio->reg_num,
	10141	+ &mii_regval);
	10142	+ mdio->val_out = mii_regval;
	10143	+ return rc;
7249	10144	}
7250	10145
7251	10146	case SIOCSMIIREG:
7252	10147	if (!netif_running(dev))
7253	10148	return -EAGAIN;
7254	10149
7255		- return 0;
	10150	+ return bnxt_hwrm_port_phy_write(bp, mdio->phy_id, mdio->reg_num,
	10151	+ mdio->val_in);
7256	10152
7257	10153	default:
7258	10154	/* do nothing */
..	..	@@ -7266,34 +10162,33 @@
7266	10162	{
7267	10163	int i;
7268	10164
7269		-
7270	10165	for (i = 0; i < bp->cp_nr_rings; i++) {
7271	10166	struct bnxt_napi *bnapi = bp->bnapi[i];
7272	10167	struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
7273		- struct ctx_hw_stats *hw_stats = cpr->hw_stats;
	10168	+ u64 *sw = cpr->stats.sw_stats;
7274	10169
7275		- stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
7276		- stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
7277		- stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
	10170	+ stats->rx_packets += BNXT_GET_RING_STATS64(sw, rx_ucast_pkts);
	10171	+ stats->rx_packets += BNXT_GET_RING_STATS64(sw, rx_mcast_pkts);
	10172	+ stats->rx_packets += BNXT_GET_RING_STATS64(sw, rx_bcast_pkts);
7278	10173
7279		- stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
7280		- stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
7281		- stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
	10174	+ stats->tx_packets += BNXT_GET_RING_STATS64(sw, tx_ucast_pkts);
	10175	+ stats->tx_packets += BNXT_GET_RING_STATS64(sw, tx_mcast_pkts);
	10176	+ stats->tx_packets += BNXT_GET_RING_STATS64(sw, tx_bcast_pkts);
7282	10177
7283		- stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
7284		- stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
7285		- stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
	10178	+ stats->rx_bytes += BNXT_GET_RING_STATS64(sw, rx_ucast_bytes);
	10179	+ stats->rx_bytes += BNXT_GET_RING_STATS64(sw, rx_mcast_bytes);
	10180	+ stats->rx_bytes += BNXT_GET_RING_STATS64(sw, rx_bcast_bytes);
7286	10181
7287		- stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
7288		- stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
7289		- stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
	10182	+ stats->tx_bytes += BNXT_GET_RING_STATS64(sw, tx_ucast_bytes);
	10183	+ stats->tx_bytes += BNXT_GET_RING_STATS64(sw, tx_mcast_bytes);
	10184	+ stats->tx_bytes += BNXT_GET_RING_STATS64(sw, tx_bcast_bytes);
7290	10185
7291	10186	stats->rx_missed_errors +=
7292		- le64_to_cpu(hw_stats->rx_discard_pkts);
	10187	+ BNXT_GET_RING_STATS64(sw, rx_discard_pkts);
7293	10188
7294		- stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
	10189	+ stats->multicast += BNXT_GET_RING_STATS64(sw, rx_mcast_pkts);
7295	10190
7296		- stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
	10191	+ stats->tx_dropped += BNXT_GET_RING_STATS64(sw, tx_error_pkts);
7297	10192	}
7298	10193	}
7299	10194
..	..	@@ -7331,19 +10226,26 @@
7331	10226	bnxt_add_prev_stats(bp, stats);
7332	10227
7333	10228	if (bp->flags & BNXT_FLAG_PORT_STATS) {
7334		- struct rx_port_stats *rx = bp->hw_rx_port_stats;
7335		- struct tx_port_stats *tx = bp->hw_tx_port_stats;
	10229	+ u64 *rx = bp->port_stats.sw_stats;
	10230	+ u64 *tx = bp->port_stats.sw_stats +
	10231	+ BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
7336	10232
7337		- stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
7338		- stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
7339		- stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
7340		- le64_to_cpu(rx->rx_ovrsz_frames) +
7341		- le64_to_cpu(rx->rx_runt_frames);
7342		- stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
7343		- le64_to_cpu(rx->rx_jbr_frames);
7344		- stats->collisions = le64_to_cpu(tx->tx_total_collisions);
7345		- stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
7346		- stats->tx_errors = le64_to_cpu(tx->tx_err);
	10233	+ stats->rx_crc_errors =
	10234	+ BNXT_GET_RX_PORT_STATS64(rx, rx_fcs_err_frames);
	10235	+ stats->rx_frame_errors =
	10236	+ BNXT_GET_RX_PORT_STATS64(rx, rx_align_err_frames);
	10237	+ stats->rx_length_errors =
	10238	+ BNXT_GET_RX_PORT_STATS64(rx, rx_undrsz_frames) +
	10239	+ BNXT_GET_RX_PORT_STATS64(rx, rx_ovrsz_frames) +
	10240	+ BNXT_GET_RX_PORT_STATS64(rx, rx_runt_frames);
	10241	+ stats->rx_errors =
	10242	+ BNXT_GET_RX_PORT_STATS64(rx, rx_false_carrier_frames) +
	10243	+ BNXT_GET_RX_PORT_STATS64(rx, rx_jbr_frames);
	10244	+ stats->collisions =
	10245	+ BNXT_GET_TX_PORT_STATS64(tx, tx_total_collisions);
	10246	+ stats->tx_fifo_errors =
	10247	+ BNXT_GET_TX_PORT_STATS64(tx, tx_fifo_underruns);
	10248	+ stats->tx_errors = BNXT_GET_TX_PORT_STATS64(tx, tx_err);
7347	10249	}
7348	10250	clear_bit(BNXT_STATE_READ_STATS, &bp->state);
7349	10251	}
..	..	@@ -7404,14 +10306,16 @@
7404	10306	static void bnxt_set_rx_mode(struct net_device *dev)
7405	10307	{
7406	10308	struct bnxt *bp = netdev_priv(dev);
7407		- struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7408		- u32 mask = vnic->rx_mask;
	10309	+ struct bnxt_vnic_info *vnic;
7409	10310	bool mc_update = false;
7410	10311	bool uc_update;
	10312	+ u32 mask;
7411	10313
7412		- if (!netif_running(dev))
	10314	+ if (!test_bit(BNXT_STATE_OPEN, &bp->state))
7413	10315	return;
7414	10316
	10317	+ vnic = &bp->vnic_info[0];
	10318	+ mask = vnic->rx_mask;
7415	10319	mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS \|
7416	10320	CFA_L2_SET_RX_MASK_REQ_MASK_MCAST \|
7417	10321	CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST \|
..	..	@@ -7530,6 +10434,14 @@
7530	10434	/* If the chip and firmware supports RFS */
7531	10435	static bool bnxt_rfs_supported(struct bnxt *bp)
7532	10436	{
	10437	+ if (bp->flags & BNXT_FLAG_CHIP_P5) {
	10438	+ if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2)
	10439	+ return true;
	10440	+ return false;
	10441	+ }
	10442	+ /* 212 firmware is broken for aRFS */
	10443	+ if (BNXT_FW_MAJ(bp) == 212)
	10444	+ return false;
7533	10445	if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
7534	10446	return true;
7535	10447	if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
..	..	@@ -7543,7 +10455,9 @@
7543	10455	#ifdef CONFIG_RFS_ACCEL
7544	10456	int vnics, max_vnics, max_rss_ctxs;
7545	10457
7546		- if (!(bp->flags & BNXT_FLAG_MSIX_CAP) \|\| !bnxt_can_reserve_rings(bp))
	10458	+ if (bp->flags & BNXT_FLAG_CHIP_P5)
	10459	+ return bnxt_rfs_supported(bp);
	10460	+ if (!(bp->flags & BNXT_FLAG_MSIX_CAP) \|\| !bnxt_can_reserve_rings(bp) \|\| !bp->rx_nr_rings)
7547	10461	return false;
7548	10462
7549	10463	vnics = 1 + bp->rx_nr_rings;
..	..	@@ -7567,12 +10481,12 @@
7567	10481	if (vnics == bp->hw_resc.resv_vnics)
7568	10482	return true;
7569	10483
7570		- bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, vnics);
	10484	+ bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, vnics);
7571	10485	if (vnics <= bp->hw_resc.resv_vnics)
7572	10486	return true;
7573	10487
7574	10488	netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n");
7575		- bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 1);
	10489	+ bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, 1);
7576	10490	return false;
7577	10491	#else
7578	10492	return false;
..	..	@@ -7600,24 +10514,16 @@
7600	10514	/* Both CTAG and STAG VLAN accelaration on the RX side have to be
7601	10515	* turned on or off together.
7602	10516	*/
7603		- vlan_features = features & (NETIF_F_HW_VLAN_CTAG_RX \|
7604		- NETIF_F_HW_VLAN_STAG_RX);
7605		- if (vlan_features != (NETIF_F_HW_VLAN_CTAG_RX \|
7606		- NETIF_F_HW_VLAN_STAG_RX)) {
7607		- if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
7608		- features &= ~(NETIF_F_HW_VLAN_CTAG_RX \|
7609		- NETIF_F_HW_VLAN_STAG_RX);
	10517	+ vlan_features = features & BNXT_HW_FEATURE_VLAN_ALL_RX;
	10518	+ if (vlan_features != BNXT_HW_FEATURE_VLAN_ALL_RX) {
	10519	+ if (dev->features & BNXT_HW_FEATURE_VLAN_ALL_RX)
	10520	+ features &= ~BNXT_HW_FEATURE_VLAN_ALL_RX;
7610	10521	else if (vlan_features)
7611		- features \|= NETIF_F_HW_VLAN_CTAG_RX \|
7612		- NETIF_F_HW_VLAN_STAG_RX;
	10522	+ features \|= BNXT_HW_FEATURE_VLAN_ALL_RX;
7613	10523	}
7614	10524	#ifdef CONFIG_BNXT_SRIOV
7615		- if (BNXT_VF(bp)) {
7616		- if (bp->vf.vlan) {
7617		- features &= ~(NETIF_F_HW_VLAN_CTAG_RX \|
7618		- NETIF_F_HW_VLAN_STAG_RX);
7619		- }
7620		- }
	10525	+ if (BNXT_VF(bp) && bp->vf.vlan)
	10526	+ features &= ~BNXT_HW_FEATURE_VLAN_ALL_RX;
7621	10527	#endif
7622	10528	return features;
7623	10529	}
..	..	@@ -7640,7 +10546,7 @@
7640	10546	if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
7641	10547	flags &= ~BNXT_FLAG_TPA;
7642	10548
7643		- if (features & NETIF_F_HW_VLAN_CTAG_RX)
	10549	+ if (features & BNXT_HW_FEATURE_VLAN_ALL_RX)
7644	10550	flags \|= BNXT_FLAG_STRIP_VLAN;
7645	10551
7646	10552	if (features & NETIF_F_NTUPLE)
..	..	@@ -7650,7 +10556,8 @@
7650	10556	if (changes & BNXT_FLAG_TPA) {
7651	10557	update_tpa = true;
7652	10558	if ((bp->flags & BNXT_FLAG_TPA) == 0 \|\|
7653		- (flags & BNXT_FLAG_TPA) == 0)
	10559	+ (flags & BNXT_FLAG_TPA) == 0 \|\|
	10560	+ (bp->flags & BNXT_FLAG_CHIP_P5))
7654	10561	re_init = true;
7655	10562	}
7656	10563
..	..	@@ -7660,9 +10567,8 @@
7660	10567	if (flags != bp->flags) {
7661	10568	u32 old_flags = bp->flags;
7662	10569
7663		- bp->flags = flags;
7664		-
7665	10570	if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
	10571	+ bp->flags = flags;
7666	10572	if (update_tpa)
7667	10573	bnxt_set_ring_params(bp);
7668	10574	return rc;
..	..	@@ -7670,12 +10576,14 @@
7670	10576
7671	10577	if (re_init) {
7672	10578	bnxt_close_nic(bp, false, false);
	10579	+ bp->flags = flags;
7673	10580	if (update_tpa)
7674	10581	bnxt_set_ring_params(bp);
7675	10582
7676	10583	return bnxt_open_nic(bp, false, false);
7677	10584	}
7678	10585	if (update_tpa) {
	10586	+ bp->flags = flags;
7679	10587	rc = bnxt_set_tpa(bp,
7680	10588	(flags & BNXT_FLAG_TPA) ?
7681	10589	true : false);
..	..	@@ -7683,6 +10591,58 @@
7683	10591	bp->flags = old_flags;
7684	10592	}
7685	10593	}
	10594	+ return rc;
	10595	+}
	10596	+
	10597	+int bnxt_dbg_hwrm_rd_reg(struct bnxt *bp, u32 reg_off, u16 num_words,
	10598	+ u32 *reg_buf)
	10599	+{
	10600	+ struct hwrm_dbg_read_direct_output *resp = bp->hwrm_cmd_resp_addr;
	10601	+ struct hwrm_dbg_read_direct_input req = {0};
	10602	+ __le32 *dbg_reg_buf;
	10603	+ dma_addr_t mapping;
	10604	+ int rc, i;
	10605	+
	10606	+ dbg_reg_buf = dma_alloc_coherent(&bp->pdev->dev, num_words * 4,
	10607	+ &mapping, GFP_KERNEL);
	10608	+ if (!dbg_reg_buf)
	10609	+ return -ENOMEM;
	10610	+ bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_READ_DIRECT, -1, -1);
	10611	+ req.host_dest_addr = cpu_to_le64(mapping);
	10612	+ req.read_addr = cpu_to_le32(reg_off + CHIMP_REG_VIEW_ADDR);
	10613	+ req.read_len32 = cpu_to_le32(num_words);
	10614	+ mutex_lock(&bp->hwrm_cmd_lock);
	10615	+ rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
	10616	+ if (rc \|\| resp->error_code) {
	10617	+ rc = -EIO;
	10618	+ goto dbg_rd_reg_exit;
	10619	+ }
	10620	+ for (i = 0; i < num_words; i++)
	10621	+ reg_buf[i] = le32_to_cpu(dbg_reg_buf[i]);
	10622	+
	10623	+dbg_rd_reg_exit:
	10624	+ mutex_unlock(&bp->hwrm_cmd_lock);
	10625	+ dma_free_coherent(&bp->pdev->dev, num_words * 4, dbg_reg_buf, mapping);
	10626	+ return rc;
	10627	+}
	10628	+
	10629	+static int bnxt_dbg_hwrm_ring_info_get(struct bnxt *bp, u8 ring_type,
	10630	+ u32 ring_id, u32 prod, u32 cons)
	10631	+{
	10632	+ struct hwrm_dbg_ring_info_get_output *resp = bp->hwrm_cmd_resp_addr;
	10633	+ struct hwrm_dbg_ring_info_get_input req = {0};
	10634	+ int rc;
	10635	+
	10636	+ bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_RING_INFO_GET, -1, -1);
	10637	+ req.ring_type = ring_type;
	10638	+ req.fw_ring_id = cpu_to_le32(ring_id);
	10639	+ mutex_lock(&bp->hwrm_cmd_lock);
	10640	+ rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
	10641	+ if (!rc) {
	10642	+ *prod = le32_to_cpu(resp->producer_index);
	10643	+ *cons = le32_to_cpu(resp->consumer_index);
	10644	+ }
	10645	+ mutex_unlock(&bp->hwrm_cmd_lock);
7686	10646	return rc;
7687	10647	}
7688	10648
..	..	@@ -7737,6 +10697,23 @@
7737	10697	}
7738	10698	}
7739	10699
	10700	+static int bnxt_hwrm_rx_ring_reset(struct bnxt *bp, int ring_nr)
	10701	+{
	10702	+ struct bnxt_rx_ring_info *rxr = &bp->rx_ring[ring_nr];
	10703	+ struct hwrm_ring_reset_input req = {0};
	10704	+ struct bnxt_napi *bnapi = rxr->bnapi;
	10705	+ struct bnxt_cp_ring_info *cpr;
	10706	+ u16 cp_ring_id;
	10707	+
	10708	+ cpr = &bnapi->cp_ring;
	10709	+ cp_ring_id = cpr->cp_ring_struct.fw_ring_id;
	10710	+ bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_RESET, cp_ring_id, -1);
	10711	+ req.ring_type = RING_RESET_REQ_RING_TYPE_RX_RING_GRP;
	10712	+ req.ring_id = cpu_to_le16(bp->grp_info[bnapi->index].fw_grp_id);
	10713	+ return hwrm_send_message_silent(bp, &req, sizeof(req),
	10714	+ HWRM_CMD_TIMEOUT);
	10715	+}
	10716	+
7740	10717	static void bnxt_reset_task(struct bnxt *bp, bool silent)
7741	10718	{
7742	10719	if (!silent)
..	..	@@ -7744,16 +10721,19 @@
7744	10721	if (netif_running(bp->dev)) {
7745	10722	int rc;
7746	10723
7747		- if (!silent)
	10724	+ if (silent) {
	10725	+ bnxt_close_nic(bp, false, false);
	10726	+ bnxt_open_nic(bp, false, false);
	10727	+ } else {
7748	10728	bnxt_ulp_stop(bp);
7749		- bnxt_close_nic(bp, false, false);
7750		- rc = bnxt_open_nic(bp, false, false);
7751		- if (!silent && !rc)
7752		- bnxt_ulp_start(bp);
	10729	+ bnxt_close_nic(bp, true, false);
	10730	+ rc = bnxt_open_nic(bp, true, false);
	10731	+ bnxt_ulp_start(bp, rc);
	10732	+ }
7753	10733	}
7754	10734	}
7755	10735
7756		-static void bnxt_tx_timeout(struct net_device *dev)
	10736	+static void bnxt_tx_timeout(struct net_device *dev, unsigned int txqueue)
7757	10737	{
7758	10738	struct bnxt *bp = netdev_priv(dev);
7759	10739
..	..	@@ -7762,19 +10742,54 @@
7762	10742	bnxt_queue_sp_work(bp);
7763	10743	}
7764	10744
	10745	+static void bnxt_fw_health_check(struct bnxt *bp)
	10746	+{
	10747	+ struct bnxt_fw_health *fw_health = bp->fw_health;
	10748	+ u32 val;
	10749	+
	10750	+ if (!fw_health->enabled \|\| test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
	10751	+ return;
	10752	+
	10753	+ /* Make sure it is enabled before checking the tmr_counter. */
	10754	+ smp_rmb();
	10755	+ if (fw_health->tmr_counter) {
	10756	+ fw_health->tmr_counter--;
	10757	+ return;
	10758	+ }
	10759	+
	10760	+ val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG);
	10761	+ if (val == fw_health->last_fw_heartbeat)
	10762	+ goto fw_reset;
	10763	+
	10764	+ fw_health->last_fw_heartbeat = val;
	10765	+
	10766	+ val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG);
	10767	+ if (val != fw_health->last_fw_reset_cnt)
	10768	+ goto fw_reset;
	10769	+
	10770	+ fw_health->tmr_counter = fw_health->tmr_multiplier;
	10771	+ return;
	10772	+
	10773	+fw_reset:
	10774	+ set_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event);
	10775	+ bnxt_queue_sp_work(bp);
	10776	+}
	10777	+
7765	10778	static void bnxt_timer(struct timer_list *t)
7766	10779	{
7767	10780	struct bnxt *bp = from_timer(bp, t, timer);
7768	10781	struct net_device *dev = bp->dev;
7769	10782
7770		- if (!netif_running(dev))
	10783	+ if (!netif_running(dev) \|\| !test_bit(BNXT_STATE_OPEN, &bp->state))
7771	10784	return;
7772	10785
7773	10786	if (atomic_read(&bp->intr_sem) != 0)
7774	10787	goto bnxt_restart_timer;
7775	10788
7776		- if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS) &&
7777		- bp->stats_coal_ticks) {
	10789	+ if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
	10790	+ bnxt_fw_health_check(bp);
	10791	+
	10792	+ if (bp->link_info.link_up && bp->stats_coal_ticks) {
7778	10793	set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
7779	10794	bnxt_queue_sp_work(bp);
7780	10795	}
..	..	@@ -7784,14 +10799,27 @@
7784	10799	bnxt_queue_sp_work(bp);
7785	10800	}
7786	10801
	10802	+#ifdef CONFIG_RFS_ACCEL
	10803	+ if ((bp->flags & BNXT_FLAG_RFS) && bp->ntp_fltr_count) {
	10804	+ set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
	10805	+ bnxt_queue_sp_work(bp);
	10806	+ }
	10807	+#endif /CONFIG_RFS_ACCEL/
	10808	+
7787	10809	if (bp->link_info.phy_retry) {
7788	10810	if (time_after(jiffies, bp->link_info.phy_retry_expires)) {
7789		- bp->link_info.phy_retry = 0;
	10811	+ bp->link_info.phy_retry = false;
7790	10812	netdev_warn(bp->dev, "failed to update phy settings after maximum retries.\n");
7791	10813	} else {
7792	10814	set_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event);
7793	10815	bnxt_queue_sp_work(bp);
7794	10816	}
	10817	+ }
	10818	+
	10819	+ if ((bp->flags & BNXT_FLAG_CHIP_P5) && !bp->chip_rev &&
	10820	+ netif_carrier_ok(dev)) {
	10821	+ set_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event);
	10822	+ bnxt_queue_sp_work(bp);
7795	10823	}
7796	10824	bnxt_restart_timer:
7797	10825	mod_timer(&bp->timer, jiffies + bp->current_interval);
..	..	@@ -7823,7 +10851,266 @@
7823	10851	bnxt_rtnl_unlock_sp(bp);
7824	10852	}
7825	10853
	10854	+/* Only called from bnxt_sp_task() */
	10855	+static void bnxt_rx_ring_reset(struct bnxt *bp)
	10856	+{
	10857	+ int i;
	10858	+
	10859	+ bnxt_rtnl_lock_sp(bp);
	10860	+ if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
	10861	+ bnxt_rtnl_unlock_sp(bp);
	10862	+ return;
	10863	+ }
	10864	+ /* Disable and flush TPA before resetting the RX ring */
	10865	+ if (bp->flags & BNXT_FLAG_TPA)
	10866	+ bnxt_set_tpa(bp, false);
	10867	+ for (i = 0; i < bp->rx_nr_rings; i++) {
	10868	+ struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
	10869	+ struct bnxt_cp_ring_info *cpr;
	10870	+ int rc;
	10871	+
	10872	+ if (!rxr->bnapi->in_reset)
	10873	+ continue;
	10874	+
	10875	+ rc = bnxt_hwrm_rx_ring_reset(bp, i);
	10876	+ if (rc) {
	10877	+ if (rc == -EINVAL \|\| rc == -EOPNOTSUPP)
	10878	+ netdev_info_once(bp->dev, "RX ring reset not supported by firmware, falling back to global reset\n");
	10879	+ else
	10880	+ netdev_warn(bp->dev, "RX ring reset failed, rc = %d, falling back to global reset\n",
	10881	+ rc);
	10882	+ bnxt_reset_task(bp, true);
	10883	+ break;
	10884	+ }
	10885	+ bnxt_free_one_rx_ring_skbs(bp, i);
	10886	+ rxr->rx_prod = 0;
	10887	+ rxr->rx_agg_prod = 0;
	10888	+ rxr->rx_sw_agg_prod = 0;
	10889	+ rxr->rx_next_cons = 0;
	10890	+ rxr->bnapi->in_reset = false;
	10891	+ bnxt_alloc_one_rx_ring(bp, i);
	10892	+ cpr = &rxr->bnapi->cp_ring;
	10893	+ cpr->sw_stats.rx.rx_resets++;
	10894	+ if (bp->flags & BNXT_FLAG_AGG_RINGS)
	10895	+ bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
	10896	+ bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
	10897	+ }
	10898	+ if (bp->flags & BNXT_FLAG_TPA)
	10899	+ bnxt_set_tpa(bp, true);
	10900	+ bnxt_rtnl_unlock_sp(bp);
	10901	+}
	10902	+
	10903	+static void bnxt_fw_reset_close(struct bnxt *bp)
	10904	+{
	10905	+ bnxt_ulp_stop(bp);
	10906	+ /* When firmware is fatal state, disable PCI device to prevent
	10907	+ * any potential bad DMAs before freeing kernel memory.
	10908	+ */
	10909	+ if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))
	10910	+ pci_disable_device(bp->pdev);
	10911	+ __bnxt_close_nic(bp, true, false);
	10912	+ bnxt_clear_int_mode(bp);
	10913	+ bnxt_hwrm_func_drv_unrgtr(bp);
	10914	+ if (pci_is_enabled(bp->pdev))
	10915	+ pci_disable_device(bp->pdev);
	10916	+ bnxt_free_ctx_mem(bp);
	10917	+ kfree(bp->ctx);
	10918	+ bp->ctx = NULL;
	10919	+}
	10920	+
	10921	+static bool is_bnxt_fw_ok(struct bnxt *bp)
	10922	+{
	10923	+ struct bnxt_fw_health *fw_health = bp->fw_health;
	10924	+ bool no_heartbeat = false, has_reset = false;
	10925	+ u32 val;
	10926	+
	10927	+ val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG);
	10928	+ if (val == fw_health->last_fw_heartbeat)
	10929	+ no_heartbeat = true;
	10930	+
	10931	+ val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG);
	10932	+ if (val != fw_health->last_fw_reset_cnt)
	10933	+ has_reset = true;
	10934	+
	10935	+ if (!no_heartbeat && has_reset)
	10936	+ return true;
	10937	+
	10938	+ return false;
	10939	+}
	10940	+
	10941	+/* rtnl_lock is acquired before calling this function */
	10942	+static void bnxt_force_fw_reset(struct bnxt *bp)
	10943	+{
	10944	+ struct bnxt_fw_health *fw_health = bp->fw_health;
	10945	+ u32 wait_dsecs;
	10946	+
	10947	+ if (!test_bit(BNXT_STATE_OPEN, &bp->state) \|\|
	10948	+ test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
	10949	+ return;
	10950	+
	10951	+ set_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
	10952	+ bnxt_fw_reset_close(bp);
	10953	+ wait_dsecs = fw_health->master_func_wait_dsecs;
	10954	+ if (fw_health->master) {
	10955	+ if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU)
	10956	+ wait_dsecs = 0;
	10957	+ bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW;
	10958	+ } else {
	10959	+ bp->fw_reset_timestamp = jiffies + wait_dsecs * HZ / 10;
	10960	+ wait_dsecs = fw_health->normal_func_wait_dsecs;
	10961	+ bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
	10962	+ }
	10963	+
	10964	+ bp->fw_reset_min_dsecs = fw_health->post_reset_wait_dsecs;
	10965	+ bp->fw_reset_max_dsecs = fw_health->post_reset_max_wait_dsecs;
	10966	+ bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10);
	10967	+}
	10968	+
	10969	+void bnxt_fw_exception(struct bnxt *bp)
	10970	+{
	10971	+ netdev_warn(bp->dev, "Detected firmware fatal condition, initiating reset\n");
	10972	+ set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state);
	10973	+ bnxt_rtnl_lock_sp(bp);
	10974	+ bnxt_force_fw_reset(bp);
	10975	+ bnxt_rtnl_unlock_sp(bp);
	10976	+}
	10977	+
	10978	+/* Returns the number of registered VFs, or 1 if VF configuration is pending, or
	10979	+ * < 0 on error.
	10980	+ */
	10981	+static int bnxt_get_registered_vfs(struct bnxt *bp)
	10982	+{
	10983	+#ifdef CONFIG_BNXT_SRIOV
	10984	+ int rc;
	10985	+
	10986	+ if (!BNXT_PF(bp))
	10987	+ return 0;
	10988	+
	10989	+ rc = bnxt_hwrm_func_qcfg(bp);
	10990	+ if (rc) {
	10991	+ netdev_err(bp->dev, "func_qcfg cmd failed, rc = %d\n", rc);
	10992	+ return rc;
	10993	+ }
	10994	+ if (bp->pf.registered_vfs)
	10995	+ return bp->pf.registered_vfs;
	10996	+ if (bp->sriov_cfg)
	10997	+ return 1;
	10998	+#endif
	10999	+ return 0;
	11000	+}
	11001	+
	11002	+void bnxt_fw_reset(struct bnxt *bp)
	11003	+{
	11004	+ bnxt_rtnl_lock_sp(bp);
	11005	+ if (test_bit(BNXT_STATE_OPEN, &bp->state) &&
	11006	+ !test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
	11007	+ int n = 0, tmo;
	11008	+
	11009	+ set_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
	11010	+ if (bp->pf.active_vfs &&
	11011	+ !test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))
	11012	+ n = bnxt_get_registered_vfs(bp);
	11013	+ if (n < 0) {
	11014	+ netdev_err(bp->dev, "Firmware reset aborted, rc = %d\n",
	11015	+ n);
	11016	+ clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
	11017	+ dev_close(bp->dev);
	11018	+ goto fw_reset_exit;
	11019	+ } else if (n > 0) {
	11020	+ u16 vf_tmo_dsecs = n * 10;
	11021	+
	11022	+ if (bp->fw_reset_max_dsecs < vf_tmo_dsecs)
	11023	+ bp->fw_reset_max_dsecs = vf_tmo_dsecs;
	11024	+ bp->fw_reset_state =
	11025	+ BNXT_FW_RESET_STATE_POLL_VF;
	11026	+ bnxt_queue_fw_reset_work(bp, HZ / 10);
	11027	+ goto fw_reset_exit;
	11028	+ }
	11029	+ bnxt_fw_reset_close(bp);
	11030	+ if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) {
	11031	+ bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN;
	11032	+ tmo = HZ / 10;
	11033	+ } else {
	11034	+ bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
	11035	+ tmo = bp->fw_reset_min_dsecs * HZ / 10;
	11036	+ }
	11037	+ bnxt_queue_fw_reset_work(bp, tmo);
	11038	+ }
	11039	+fw_reset_exit:
	11040	+ bnxt_rtnl_unlock_sp(bp);
	11041	+}
	11042	+
	11043	+static void bnxt_chk_missed_irq(struct bnxt *bp)
	11044	+{
	11045	+ int i;
	11046	+
	11047	+ if (!(bp->flags & BNXT_FLAG_CHIP_P5))
	11048	+ return;
	11049	+
	11050	+ for (i = 0; i < bp->cp_nr_rings; i++) {
	11051	+ struct bnxt_napi *bnapi = bp->bnapi[i];
	11052	+ struct bnxt_cp_ring_info *cpr;
	11053	+ u32 fw_ring_id;
	11054	+ int j;
	11055	+
	11056	+ if (!bnapi)
	11057	+ continue;
	11058	+
	11059	+ cpr = &bnapi->cp_ring;
	11060	+ for (j = 0; j < 2; j++) {
	11061	+ struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
	11062	+ u32 val[2];
	11063	+
	11064	+ if (!cpr2 \|\| cpr2->has_more_work \|\|
	11065	+ !bnxt_has_work(bp, cpr2))
	11066	+ continue;
	11067	+
	11068	+ if (cpr2->cp_raw_cons != cpr2->last_cp_raw_cons) {
	11069	+ cpr2->last_cp_raw_cons = cpr2->cp_raw_cons;
	11070	+ continue;
	11071	+ }
	11072	+ fw_ring_id = cpr2->cp_ring_struct.fw_ring_id;
	11073	+ bnxt_dbg_hwrm_ring_info_get(bp,
	11074	+ DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL,
	11075	+ fw_ring_id, &val[0], &val[1]);
	11076	+ cpr->sw_stats.cmn.missed_irqs++;
	11077	+ }
	11078	+ }
	11079	+}
	11080	+
7826	11081	static void bnxt_cfg_ntp_filters(struct bnxt *);
	11082	+
	11083	+static void bnxt_init_ethtool_link_settings(struct bnxt *bp)
	11084	+{
	11085	+ struct bnxt_link_info *link_info = &bp->link_info;
	11086	+
	11087	+ if (BNXT_AUTO_MODE(link_info->auto_mode)) {
	11088	+ link_info->autoneg = BNXT_AUTONEG_SPEED;
	11089	+ if (bp->hwrm_spec_code >= 0x10201) {
	11090	+ if (link_info->auto_pause_setting &
	11091	+ PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
	11092	+ link_info->autoneg \|= BNXT_AUTONEG_FLOW_CTRL;
	11093	+ } else {
	11094	+ link_info->autoneg \|= BNXT_AUTONEG_FLOW_CTRL;
	11095	+ }
	11096	+ link_info->advertising = link_info->auto_link_speeds;
	11097	+ link_info->advertising_pam4 = link_info->auto_pam4_link_speeds;
	11098	+ } else {
	11099	+ link_info->req_link_speed = link_info->force_link_speed;
	11100	+ link_info->req_signal_mode = BNXT_SIG_MODE_NRZ;
	11101	+ if (link_info->force_pam4_link_speed) {
	11102	+ link_info->req_link_speed =
	11103	+ link_info->force_pam4_link_speed;
	11104	+ link_info->req_signal_mode = BNXT_SIG_MODE_PAM4;
	11105	+ }
	11106	+ link_info->req_duplex = link_info->duplex_setting;
	11107	+ }
	11108	+ if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
	11109	+ link_info->req_flow_ctrl =
	11110	+ link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
	11111	+ else
	11112	+ link_info->req_flow_ctrl = link_info->force_pause_setting;
	11113	+}
7827	11114
7828	11115	static void bnxt_sp_task(struct work_struct *work)
7829	11116	{
..	..	@@ -7843,27 +11130,10 @@
7843	11130	bnxt_cfg_ntp_filters(bp);
7844	11131	if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
7845	11132	bnxt_hwrm_exec_fwd_req(bp);
7846		- if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
7847		- bnxt_hwrm_tunnel_dst_port_alloc(
7848		- bp, bp->vxlan_port,
7849		- TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
7850		- }
7851		- if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
7852		- bnxt_hwrm_tunnel_dst_port_free(
7853		- bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
7854		- }
7855		- if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) {
7856		- bnxt_hwrm_tunnel_dst_port_alloc(
7857		- bp, bp->nge_port,
7858		- TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
7859		- }
7860		- if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) {
7861		- bnxt_hwrm_tunnel_dst_port_free(
7862		- bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
7863		- }
7864	11133	if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) {
7865		- bnxt_hwrm_port_qstats(bp);
7866		- bnxt_hwrm_port_qstats_ext(bp);
	11134	+ bnxt_hwrm_port_qstats(bp, 0);
	11135	+ bnxt_hwrm_port_qstats_ext(bp, 0);
	11136	+ bnxt_accumulate_all_stats(bp);
7867	11137	}
7868	11138
7869	11139	if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
..	..	@@ -7875,10 +11145,14 @@
7875	11145	bnxt_hwrm_phy_qcaps(bp);
7876	11146
7877	11147	rc = bnxt_update_link(bp, true);
7878		- mutex_unlock(&bp->link_lock);
7879	11148	if (rc)
7880	11149	netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
7881	11150	rc);
	11151	+
	11152	+ if (test_and_clear_bit(BNXT_LINK_CFG_CHANGE_SP_EVENT,
	11153	+ &bp->sp_event))
	11154	+ bnxt_init_ethtool_link_settings(bp);
	11155	+ mutex_unlock(&bp->link_lock);
7882	11156	}
7883	11157	if (test_and_clear_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event)) {
7884	11158	int rc;
..	..	@@ -7902,6 +11176,9 @@
7902	11176	if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event))
7903	11177	bnxt_tc_flow_stats_work(bp);
7904	11178
	11179	+ if (test_and_clear_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event))
	11180	+ bnxt_chk_missed_irq(bp);
	11181	+
7905	11182	/* These functions below will clear BNXT_STATE_IN_SP_TASK. They
7906	11183	* must be the last functions to be called before exiting.
7907	11184	*/
..	..	@@ -7910,6 +11187,18 @@
7910	11187
7911	11188	if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
7912	11189	bnxt_reset(bp, true);
	11190	+
	11191	+ if (test_and_clear_bit(BNXT_RST_RING_SP_EVENT, &bp->sp_event))
	11192	+ bnxt_rx_ring_reset(bp);
	11193	+
	11194	+ if (test_and_clear_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event))
	11195	+ bnxt_devlink_health_report(bp, BNXT_FW_RESET_NOTIFY_SP_EVENT);
	11196	+
	11197	+ if (test_and_clear_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event)) {
	11198	+ if (!is_bnxt_fw_ok(bp))
	11199	+ bnxt_devlink_health_report(bp,
	11200	+ BNXT_FW_EXCEPTION_SP_EVENT);
	11201	+ }
7913	11202
7914	11203	smp_mb__before_atomic();
7915	11204	clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
..	..	@@ -7920,7 +11209,7 @@
7920	11209	int tx_xdp)
7921	11210	{
7922	11211	int max_rx, max_tx, tx_sets = 1;
7923		- int tx_rings_needed;
	11212	+ int tx_rings_needed, stats;
7924	11213	int rx_rings = rx;
7925	11214	int cp, vnics, rc;
7926	11215
..	..	@@ -7939,16 +11228,19 @@
7939	11228	return -ENOMEM;
7940	11229
7941	11230	vnics = 1;
7942		- if (bp->flags & BNXT_FLAG_RFS)
	11231	+ if ((bp->flags & (BNXT_FLAG_RFS \| BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS)
7943	11232	vnics += rx_rings;
7944	11233
7945	11234	if (bp->flags & BNXT_FLAG_AGG_RINGS)
7946	11235	rx_rings <<= 1;
7947	11236	cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx;
7948		- if (BNXT_NEW_RM(bp))
	11237	+ stats = cp;
	11238	+ if (BNXT_NEW_RM(bp)) {
7949	11239	cp += bnxt_get_ulp_msix_num(bp);
	11240	+ stats += bnxt_get_ulp_stat_ctxs(bp);
	11241	+ }
7950	11242	return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp,
7951		- vnics);
	11243	+ stats, vnics);
7952	11244	}
7953	11245
7954	11246	static void bnxt_unmap_bars(struct bnxt bp, struct pci_dev pdev)
..	..	@@ -7973,7 +11265,8 @@
7973	11265	{
7974	11266	bnxt_unmap_bars(bp, bp->pdev);
7975	11267	pci_release_regions(bp->pdev);
7976		- pci_disable_device(bp->pdev);
	11268	+ if (pci_is_enabled(bp->pdev))
	11269	+ pci_disable_device(bp->pdev);
7977	11270	}
7978	11271
7979	11272	static void bnxt_init_dflt_coal(struct bnxt *bp)
..	..	@@ -7984,7 +11277,7 @@
7984	11277	* 1 coal_buf x bufs_per_record = 1 completion record.
7985	11278	*/
7986	11279	coal = &bp->rx_coal;
7987		- coal->coal_ticks = 14;
	11280	+ coal->coal_ticks = 10;
7988	11281	coal->coal_bufs = 30;
7989	11282	coal->coal_ticks_irq = 1;
7990	11283	coal->coal_bufs_irq = 2;
..	..	@@ -8000,6 +11293,403 @@
8000	11293	coal->bufs_per_record = 1;
8001	11294
8002	11295	bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
	11296	+}
	11297	+
	11298	+static int bnxt_fw_reset_via_optee(struct bnxt *bp)
	11299	+{
	11300	+#ifdef CONFIG_TEE_BNXT_FW
	11301	+ int rc = tee_bnxt_fw_load();
	11302	+
	11303	+ if (rc)
	11304	+ netdev_err(bp->dev, "Failed FW reset via OP-TEE, rc=%d\n", rc);
	11305	+
	11306	+ return rc;
	11307	+#else
	11308	+ netdev_err(bp->dev, "OP-TEE not supported\n");
	11309	+ return -ENODEV;
	11310	+#endif
	11311	+}
	11312	+
	11313	+static int bnxt_fw_init_one_p1(struct bnxt *bp)
	11314	+{
	11315	+ int rc;
	11316	+
	11317	+ bp->fw_cap = 0;
	11318	+ rc = bnxt_hwrm_ver_get(bp);
	11319	+ bnxt_try_map_fw_health_reg(bp);
	11320	+ if (rc) {
	11321	+ if (bp->fw_health && bp->fw_health->status_reliable) {
	11322	+ u32 sts = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG);
	11323	+
	11324	+ netdev_err(bp->dev,
	11325	+ "Firmware not responding, status: 0x%x\n",
	11326	+ sts);
	11327	+ if (sts & FW_STATUS_REG_CRASHED_NO_MASTER) {
	11328	+ netdev_warn(bp->dev, "Firmware recover via OP-TEE requested\n");
	11329	+ rc = bnxt_fw_reset_via_optee(bp);
	11330	+ if (!rc)
	11331	+ rc = bnxt_hwrm_ver_get(bp);
	11332	+ }
	11333	+ }
	11334	+ if (rc)
	11335	+ return rc;
	11336	+ }
	11337	+
	11338	+ if (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL) {
	11339	+ rc = bnxt_alloc_kong_hwrm_resources(bp);
	11340	+ if (rc)
	11341	+ bp->fw_cap &= ~BNXT_FW_CAP_KONG_MB_CHNL;
	11342	+ }
	11343	+
	11344	+ if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) \|\|
	11345	+ bp->hwrm_max_ext_req_len > BNXT_HWRM_MAX_REQ_LEN) {
	11346	+ rc = bnxt_alloc_hwrm_short_cmd_req(bp);
	11347	+ if (rc)
	11348	+ return rc;
	11349	+ }
	11350	+ bnxt_nvm_cfg_ver_get(bp);
	11351	+
	11352	+ rc = bnxt_hwrm_func_reset(bp);
	11353	+ if (rc)
	11354	+ return -ENODEV;
	11355	+
	11356	+ bnxt_hwrm_fw_set_time(bp);
	11357	+ return 0;
	11358	+}
	11359	+
	11360	+static int bnxt_fw_init_one_p2(struct bnxt *bp)
	11361	+{
	11362	+ int rc;
	11363	+
	11364	+ /* Get the MAX capabilities for this function */
	11365	+ rc = bnxt_hwrm_func_qcaps(bp);
	11366	+ if (rc) {
	11367	+ netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
	11368	+ rc);
	11369	+ return -ENODEV;
	11370	+ }
	11371	+
	11372	+ rc = bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(bp);
	11373	+ if (rc)
	11374	+ netdev_warn(bp->dev, "hwrm query adv flow mgnt failure rc: %d\n",
	11375	+ rc);
	11376	+
	11377	+ if (bnxt_alloc_fw_health(bp)) {
	11378	+ netdev_warn(bp->dev, "no memory for firmware error recovery\n");
	11379	+ } else {
	11380	+ rc = bnxt_hwrm_error_recovery_qcfg(bp);
	11381	+ if (rc)
	11382	+ netdev_warn(bp->dev, "hwrm query error recovery failure rc: %d\n",
	11383	+ rc);
	11384	+ }
	11385	+
	11386	+ rc = bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, false);
	11387	+ if (rc)
	11388	+ return -ENODEV;
	11389	+
	11390	+ bnxt_hwrm_func_qcfg(bp);
	11391	+ bnxt_hwrm_vnic_qcaps(bp);
	11392	+ bnxt_hwrm_port_led_qcaps(bp);
	11393	+ bnxt_ethtool_init(bp);
	11394	+ bnxt_dcb_init(bp);
	11395	+ return 0;
	11396	+}
	11397	+
	11398	+static void bnxt_set_dflt_rss_hash_type(struct bnxt *bp)
	11399	+{
	11400	+ bp->flags &= ~BNXT_FLAG_UDP_RSS_CAP;
	11401	+ bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 \|
	11402	+ VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 \|
	11403	+ VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 \|
	11404	+ VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
	11405	+ if (BNXT_CHIP_P4_PLUS(bp) && bp->hwrm_spec_code >= 0x10501) {
	11406	+ bp->flags \|= BNXT_FLAG_UDP_RSS_CAP;
	11407	+ bp->rss_hash_cfg \|= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 \|
	11408	+ VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
	11409	+ }
	11410	+}
	11411	+
	11412	+static void bnxt_set_dflt_rfs(struct bnxt *bp)
	11413	+{
	11414	+ struct net_device *dev = bp->dev;
	11415	+
	11416	+ dev->hw_features &= ~NETIF_F_NTUPLE;
	11417	+ dev->features &= ~NETIF_F_NTUPLE;
	11418	+ bp->flags &= ~BNXT_FLAG_RFS;
	11419	+ if (bnxt_rfs_supported(bp)) {
	11420	+ dev->hw_features \|= NETIF_F_NTUPLE;
	11421	+ if (bnxt_rfs_capable(bp)) {
	11422	+ bp->flags \|= BNXT_FLAG_RFS;
	11423	+ dev->features \|= NETIF_F_NTUPLE;
	11424	+ }
	11425	+ }
	11426	+}
	11427	+
	11428	+static void bnxt_fw_init_one_p3(struct bnxt *bp)
	11429	+{
	11430	+ struct pci_dev *pdev = bp->pdev;
	11431	+
	11432	+ bnxt_set_dflt_rss_hash_type(bp);
	11433	+ bnxt_set_dflt_rfs(bp);
	11434	+
	11435	+ bnxt_get_wol_settings(bp);
	11436	+ if (bp->flags & BNXT_FLAG_WOL_CAP)
	11437	+ device_set_wakeup_enable(&pdev->dev, bp->wol);
	11438	+ else
	11439	+ device_set_wakeup_capable(&pdev->dev, false);
	11440	+
	11441	+ bnxt_hwrm_set_cache_line_size(bp, cache_line_size());
	11442	+ bnxt_hwrm_coal_params_qcaps(bp);
	11443	+}
	11444	+
	11445	+static int bnxt_probe_phy(struct bnxt *bp, bool fw_dflt);
	11446	+
	11447	+static int bnxt_fw_init_one(struct bnxt *bp)
	11448	+{
	11449	+ int rc;
	11450	+
	11451	+ rc = bnxt_fw_init_one_p1(bp);
	11452	+ if (rc) {
	11453	+ netdev_err(bp->dev, "Firmware init phase 1 failed\n");
	11454	+ return rc;
	11455	+ }
	11456	+ rc = bnxt_fw_init_one_p2(bp);
	11457	+ if (rc) {
	11458	+ netdev_err(bp->dev, "Firmware init phase 2 failed\n");
	11459	+ return rc;
	11460	+ }
	11461	+ rc = bnxt_probe_phy(bp, false);
	11462	+ if (rc)
	11463	+ return rc;
	11464	+ rc = bnxt_approve_mac(bp, bp->dev->dev_addr, false);
	11465	+ if (rc)
	11466	+ return rc;
	11467	+
	11468	+ /* In case fw capabilities have changed, destroy the unneeded
	11469	+ * reporters and create newly capable ones.
	11470	+ */
	11471	+ bnxt_dl_fw_reporters_destroy(bp, false);
	11472	+ bnxt_dl_fw_reporters_create(bp);
	11473	+ bnxt_fw_init_one_p3(bp);
	11474	+ return 0;
	11475	+}
	11476	+
	11477	+static void bnxt_fw_reset_writel(struct bnxt *bp, int reg_idx)
	11478	+{
	11479	+ struct bnxt_fw_health *fw_health = bp->fw_health;
	11480	+ u32 reg = fw_health->fw_reset_seq_regs[reg_idx];
	11481	+ u32 val = fw_health->fw_reset_seq_vals[reg_idx];
	11482	+ u32 reg_type, reg_off, delay_msecs;
	11483	+
	11484	+ delay_msecs = fw_health->fw_reset_seq_delay_msec[reg_idx];
	11485	+ reg_type = BNXT_FW_HEALTH_REG_TYPE(reg);
	11486	+ reg_off = BNXT_FW_HEALTH_REG_OFF(reg);
	11487	+ switch (reg_type) {
	11488	+ case BNXT_FW_HEALTH_REG_TYPE_CFG:
	11489	+ pci_write_config_dword(bp->pdev, reg_off, val);
	11490	+ break;
	11491	+ case BNXT_FW_HEALTH_REG_TYPE_GRC:
	11492	+ writel(reg_off & BNXT_GRC_BASE_MASK,
	11493	+ bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
	11494	+ reg_off = (reg_off & BNXT_GRC_OFFSET_MASK) + 0x2000;
	11495	+ fallthrough;
	11496	+ case BNXT_FW_HEALTH_REG_TYPE_BAR0:
	11497	+ writel(val, bp->bar0 + reg_off);
	11498	+ break;
	11499	+ case BNXT_FW_HEALTH_REG_TYPE_BAR1:
	11500	+ writel(val, bp->bar1 + reg_off);
	11501	+ break;
	11502	+ }
	11503	+ if (delay_msecs) {
	11504	+ pci_read_config_dword(bp->pdev, 0, &val);
	11505	+ msleep(delay_msecs);
	11506	+ }
	11507	+}
	11508	+
	11509	+static void bnxt_reset_all(struct bnxt *bp)
	11510	+{
	11511	+ struct bnxt_fw_health *fw_health = bp->fw_health;
	11512	+ int i, rc;
	11513	+
	11514	+ if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) {
	11515	+ bnxt_fw_reset_via_optee(bp);
	11516	+ bp->fw_reset_timestamp = jiffies;
	11517	+ return;
	11518	+ }
	11519	+
	11520	+ if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST) {
	11521	+ for (i = 0; i < fw_health->fw_reset_seq_cnt; i++)
	11522	+ bnxt_fw_reset_writel(bp, i);
	11523	+ } else if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) {
	11524	+ struct hwrm_fw_reset_input req = {0};
	11525	+
	11526	+ bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_RESET, -1, -1);
	11527	+ req.resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr);
	11528	+ req.embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP;
	11529	+ req.selfrst_status = FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP;
	11530	+ req.flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL;
	11531	+ rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
	11532	+ if (rc)
	11533	+ netdev_warn(bp->dev, "Unable to reset FW rc=%d\n", rc);
	11534	+ }
	11535	+ bp->fw_reset_timestamp = jiffies;
	11536	+}
	11537	+
	11538	+static void bnxt_fw_reset_task(struct work_struct *work)
	11539	+{
	11540	+ struct bnxt *bp = container_of(work, struct bnxt, fw_reset_task.work);
	11541	+ int rc;
	11542	+
	11543	+ if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
	11544	+ netdev_err(bp->dev, "bnxt_fw_reset_task() called when not in fw reset mode!\n");
	11545	+ return;
	11546	+ }
	11547	+
	11548	+ switch (bp->fw_reset_state) {
	11549	+ case BNXT_FW_RESET_STATE_POLL_VF: {
	11550	+ int n = bnxt_get_registered_vfs(bp);
	11551	+ int tmo;
	11552	+
	11553	+ if (n < 0) {
	11554	+ netdev_err(bp->dev, "Firmware reset aborted, subsequent func_qcfg cmd failed, rc = %d, %d msecs since reset timestamp\n",
	11555	+ n, jiffies_to_msecs(jiffies -
	11556	+ bp->fw_reset_timestamp));
	11557	+ goto fw_reset_abort;
	11558	+ } else if (n > 0) {
	11559	+ if (time_after(jiffies, bp->fw_reset_timestamp +
	11560	+ (bp->fw_reset_max_dsecs * HZ / 10))) {
	11561	+ clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
	11562	+ bp->fw_reset_state = 0;
	11563	+ netdev_err(bp->dev, "Firmware reset aborted, bnxt_get_registered_vfs() returns %d\n",
	11564	+ n);
	11565	+ return;
	11566	+ }
	11567	+ bnxt_queue_fw_reset_work(bp, HZ / 10);
	11568	+ return;
	11569	+ }
	11570	+ bp->fw_reset_timestamp = jiffies;
	11571	+ rtnl_lock();
	11572	+ if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) {
	11573	+ rtnl_unlock();
	11574	+ goto fw_reset_abort;
	11575	+ }
	11576	+ bnxt_fw_reset_close(bp);
	11577	+ if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) {
	11578	+ bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN;
	11579	+ tmo = HZ / 10;
	11580	+ } else {
	11581	+ bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
	11582	+ tmo = bp->fw_reset_min_dsecs * HZ / 10;
	11583	+ }
	11584	+ rtnl_unlock();
	11585	+ bnxt_queue_fw_reset_work(bp, tmo);
	11586	+ return;
	11587	+ }
	11588	+ case BNXT_FW_RESET_STATE_POLL_FW_DOWN: {
	11589	+ u32 val;
	11590	+
	11591	+ val = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG);
	11592	+ if (!(val & BNXT_FW_STATUS_SHUTDOWN) &&
	11593	+ !time_after(jiffies, bp->fw_reset_timestamp +
	11594	+ (bp->fw_reset_max_dsecs * HZ / 10))) {
	11595	+ bnxt_queue_fw_reset_work(bp, HZ / 5);
	11596	+ return;
	11597	+ }
	11598	+
	11599	+ if (!bp->fw_health->master) {
	11600	+ u32 wait_dsecs = bp->fw_health->normal_func_wait_dsecs;
	11601	+
	11602	+ bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
	11603	+ bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10);
	11604	+ return;
	11605	+ }
	11606	+ bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW;
	11607	+ }
	11608	+ fallthrough;
	11609	+ case BNXT_FW_RESET_STATE_RESET_FW:
	11610	+ bnxt_reset_all(bp);
	11611	+ bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
	11612	+ bnxt_queue_fw_reset_work(bp, bp->fw_reset_min_dsecs * HZ / 10);
	11613	+ return;
	11614	+ case BNXT_FW_RESET_STATE_ENABLE_DEV:
	11615	+ if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) {
	11616	+ u32 val;
	11617	+
	11618	+ val = bnxt_fw_health_readl(bp,
	11619	+ BNXT_FW_RESET_INPROG_REG);
	11620	+ if (val)
	11621	+ netdev_warn(bp->dev, "FW reset inprog %x after min wait time.\n",
	11622	+ val);
	11623	+ }
	11624	+ clear_bit(BNXT_STATE_FW_FATAL_COND, &bp->state);
	11625	+ if (pci_enable_device(bp->pdev)) {
	11626	+ netdev_err(bp->dev, "Cannot re-enable PCI device\n");
	11627	+ goto fw_reset_abort;
	11628	+ }
	11629	+ pci_set_master(bp->pdev);
	11630	+ bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW;
	11631	+ fallthrough;
	11632	+ case BNXT_FW_RESET_STATE_POLL_FW:
	11633	+ bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT;
	11634	+ rc = __bnxt_hwrm_ver_get(bp, true);
	11635	+ if (rc) {
	11636	+ if (time_after(jiffies, bp->fw_reset_timestamp +
	11637	+ (bp->fw_reset_max_dsecs * HZ / 10))) {
	11638	+ netdev_err(bp->dev, "Firmware reset aborted\n");
	11639	+ goto fw_reset_abort_status;
	11640	+ }
	11641	+ bnxt_queue_fw_reset_work(bp, HZ / 5);
	11642	+ return;
	11643	+ }
	11644	+ bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
	11645	+ bp->fw_reset_state = BNXT_FW_RESET_STATE_OPENING;
	11646	+ fallthrough;
	11647	+ case BNXT_FW_RESET_STATE_OPENING:
	11648	+ while (!rtnl_trylock()) {
	11649	+ bnxt_queue_fw_reset_work(bp, HZ / 10);
	11650	+ return;
	11651	+ }
	11652	+ rc = bnxt_open(bp->dev);
	11653	+ if (rc) {
	11654	+ netdev_err(bp->dev, "bnxt_open_nic() failed\n");
	11655	+ clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
	11656	+ dev_close(bp->dev);
	11657	+ }
	11658	+
	11659	+ if ((bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY) &&
	11660	+ bp->fw_health->enabled) {
	11661	+ bp->fw_health->last_fw_reset_cnt =
	11662	+ bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG);
	11663	+ }
	11664	+ bp->fw_reset_state = 0;
	11665	+ /* Make sure fw_reset_state is 0 before clearing the flag */
	11666	+ smp_mb__before_atomic();
	11667	+ clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
	11668	+ bnxt_ulp_start(bp, rc);
	11669	+ if (!rc)
	11670	+ bnxt_reenable_sriov(bp);
	11671	+ bnxt_dl_health_recovery_done(bp);
	11672	+ bnxt_dl_health_status_update(bp, true);
	11673	+ rtnl_unlock();
	11674	+ break;
	11675	+ }
	11676	+ return;
	11677	+
	11678	+fw_reset_abort_status:
	11679	+ if (bp->fw_health->status_reliable \|\|
	11680	+ (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) {
	11681	+ u32 sts = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG);
	11682	+
	11683	+ netdev_err(bp->dev, "fw_health_status 0x%x\n", sts);
	11684	+ }
	11685	+fw_reset_abort:
	11686	+ clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
	11687	+ if (bp->fw_reset_state != BNXT_FW_RESET_STATE_POLL_VF)
	11688	+ bnxt_dl_health_status_update(bp, false);
	11689	+ bp->fw_reset_state = 0;
	11690	+ rtnl_lock();
	11691	+ dev_close(bp->dev);
	11692	+ rtnl_unlock();
8003	11693	}
8004	11694
8005	11695	static int bnxt_init_board(struct pci_dev pdev, struct net_device dev)
..	..	@@ -8041,16 +11731,12 @@
8041	11731	bp->dev = dev;
8042	11732	bp->pdev = pdev;
8043	11733
	11734	+ /* Doorbell BAR bp->bar1 is mapped after bnxt_fw_init_one_p2()
	11735	+ * determines the BAR size.
	11736	+ */
8044	11737	bp->bar0 = pci_ioremap_bar(pdev, 0);
8045	11738	if (!bp->bar0) {
8046	11739	dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
8047		- rc = -ENOMEM;
8048		- goto init_err_release;
8049		- }
8050		-
8051		- bp->bar1 = pci_ioremap_bar(pdev, 2);
8052		- if (!bp->bar1) {
8053		- dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
8054	11740	rc = -ENOMEM;
8055	11741	goto init_err_release;
8056	11742	}
..	..	@@ -8065,8 +11751,12 @@
8065	11751	pci_enable_pcie_error_reporting(pdev);
8066	11752
8067	11753	INIT_WORK(&bp->sp_task, bnxt_sp_task);
	11754	+ INIT_DELAYED_WORK(&bp->fw_reset_task, bnxt_fw_reset_task);
8068	11755
8069	11756	spin_lock_init(&bp->ntp_fltr_lock);
	11757	+#if BITS_PER_LONG == 32
	11758	+ spin_lock_init(&bp->db_lock);
	11759	+#endif
8070	11760
8071	11761	bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
8072	11762	bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
..	..	@@ -8075,6 +11765,9 @@
8075	11765
8076	11766	timer_setup(&bp->timer, bnxt_timer, 0);
8077	11767	bp->current_interval = BNXT_TIMER_INTERVAL;
	11768	+
	11769	+ bp->vxlan_fw_dst_port_id = INVALID_HW_RING_ID;
	11770	+ bp->nge_fw_dst_port_id = INVALID_HW_RING_ID;
8078	11771
8079	11772	clear_bit(BNXT_STATE_OPEN, &bp->state);
8080	11773	return 0;
..	..	@@ -8170,7 +11863,6 @@
8170	11863	bp->tx_nr_rings += bp->tx_nr_rings_xdp;
8171	11864	bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
8172	11865	bp->tx_nr_rings + bp->rx_nr_rings;
8173		- bp->num_stat_ctxs = bp->cp_nr_rings;
8174	11866
8175	11867	if (netif_running(bp->dev))
8176	11868	return bnxt_open_nic(bp, true, false);
..	..	@@ -8195,32 +11887,19 @@
8195	11887	}
8196	11888	}
8197	11889
8198		-static int bnxt_setup_tc_block(struct net_device *dev,
8199		- struct tc_block_offload *f)
8200		-{
8201		- struct bnxt *bp = netdev_priv(dev);
8202		-
8203		- if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
8204		- return -EOPNOTSUPP;
8205		-
8206		- switch (f->command) {
8207		- case TC_BLOCK_BIND:
8208		- return tcf_block_cb_register(f->block, bnxt_setup_tc_block_cb,
8209		- bp, bp, f->extack);
8210		- case TC_BLOCK_UNBIND:
8211		- tcf_block_cb_unregister(f->block, bnxt_setup_tc_block_cb, bp);
8212		- return 0;
8213		- default:
8214		- return -EOPNOTSUPP;
8215		- }
8216		-}
	11890	+LIST_HEAD(bnxt_block_cb_list);
8217	11891
8218	11892	static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type,
8219	11893	void *type_data)
8220	11894	{
	11895	+ struct bnxt *bp = netdev_priv(dev);
	11896	+
8221	11897	switch (type) {
8222	11898	case TC_SETUP_BLOCK:
8223		- return bnxt_setup_tc_block(dev, type_data);
	11899	+ return flow_block_cb_setup_simple(type_data,
	11900	+ &bnxt_block_cb_list,
	11901	+ bnxt_setup_tc_block_cb,
	11902	+ bp, bp, true);
8224	11903	case TC_SETUP_QDISC_MQPRIO: {
8225	11904	struct tc_mqprio_qopt *mqprio = type_data;
8226	11905
..	..	@@ -8274,6 +11953,7 @@
8274	11953	struct ethhdr eth = (struct ethhdr )skb_mac_header(skb);
8275	11954	int rc = 0, idx, bit_id, l2_idx = 0;
8276	11955	struct hlist_head *head;
	11956	+ u32 flags;
8277	11957
8278	11958	if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
8279	11959	struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
..	..	@@ -8313,8 +11993,9 @@
8313	11993	rc = -EPROTONOSUPPORT;
8314	11994	goto err_free;
8315	11995	}
8316		- if ((fkeys->control.flags & FLOW_DIS_ENCAPSULATION) &&
8317		- bp->hwrm_spec_code < 0x10601) {
	11996	+ flags = fkeys->control.flags;
	11997	+ if (((flags & FLOW_DIS_ENCAPSULATION) &&
	11998	+ bp->hwrm_spec_code < 0x10601) \|\| (flags & FLOW_DIS_IS_FRAGMENT)) {
8318	11999	rc = -EPROTONOSUPPORT;
8319	12000	goto err_free;
8320	12001	}
..	..	@@ -8327,8 +12008,8 @@
8327	12008	rcu_read_lock();
8328	12009	hlist_for_each_entry_rcu(fltr, head, hash) {
8329	12010	if (bnxt_fltr_match(fltr, new_fltr)) {
	12011	+ rc = fltr->sw_id;
8330	12012	rcu_read_unlock();
8331		- rc = 0;
8332	12013	goto err_free;
8333	12014	}
8334	12015	}
..	..	@@ -8404,7 +12085,7 @@
8404	12085	}
8405	12086	}
8406	12087	if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
8407		- netdev_info(bp->dev, "Receive PF driver unload event!");
	12088	+ netdev_info(bp->dev, "Receive PF driver unload event!\n");
8408	12089	}
8409	12090
8410	12091	#else
..	..	@@ -8415,84 +12096,33 @@
8415	12096
8416	12097	#endif /* CONFIG_RFS_ACCEL */
8417	12098
8418		-static void bnxt_udp_tunnel_add(struct net_device *dev,
8419		- struct udp_tunnel_info *ti)
	12099	+static int bnxt_udp_tunnel_sync(struct net_device *netdev, unsigned int table)
8420	12100	{
8421		- struct bnxt *bp = netdev_priv(dev);
	12101	+ struct bnxt *bp = netdev_priv(netdev);
	12102	+ struct udp_tunnel_info ti;
	12103	+ unsigned int cmd;
8422	12104
8423		- if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
8424		- return;
	12105	+ udp_tunnel_nic_get_port(netdev, table, 0, &ti);
	12106	+ if (ti.type == UDP_TUNNEL_TYPE_VXLAN)
	12107	+ cmd = TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN;
	12108	+ else
	12109	+ cmd = TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE;
8425	12110
8426		- if (!netif_running(dev))
8427		- return;
	12111	+ if (ti.port)
	12112	+ return bnxt_hwrm_tunnel_dst_port_alloc(bp, ti.port, cmd);
8428	12113
8429		- switch (ti->type) {
8430		- case UDP_TUNNEL_TYPE_VXLAN:
8431		- if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port)
8432		- return;
8433		-
8434		- bp->vxlan_port_cnt++;
8435		- if (bp->vxlan_port_cnt == 1) {
8436		- bp->vxlan_port = ti->port;
8437		- set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
8438		- bnxt_queue_sp_work(bp);
8439		- }
8440		- break;
8441		- case UDP_TUNNEL_TYPE_GENEVE:
8442		- if (bp->nge_port_cnt && bp->nge_port != ti->port)
8443		- return;
8444		-
8445		- bp->nge_port_cnt++;
8446		- if (bp->nge_port_cnt == 1) {
8447		- bp->nge_port = ti->port;
8448		- set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event);
8449		- }
8450		- break;
8451		- default:
8452		- return;
8453		- }
8454		-
8455		- bnxt_queue_sp_work(bp);
	12114	+ return bnxt_hwrm_tunnel_dst_port_free(bp, cmd);
8456	12115	}
8457	12116
8458		-static void bnxt_udp_tunnel_del(struct net_device *dev,
8459		- struct udp_tunnel_info *ti)
8460		-{
8461		- struct bnxt *bp = netdev_priv(dev);
8462		-
8463		- if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
8464		- return;
8465		-
8466		- if (!netif_running(dev))
8467		- return;
8468		-
8469		- switch (ti->type) {
8470		- case UDP_TUNNEL_TYPE_VXLAN:
8471		- if (!bp->vxlan_port_cnt \|\| bp->vxlan_port != ti->port)
8472		- return;
8473		- bp->vxlan_port_cnt--;
8474		-
8475		- if (bp->vxlan_port_cnt != 0)
8476		- return;
8477		-
8478		- set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
8479		- break;
8480		- case UDP_TUNNEL_TYPE_GENEVE:
8481		- if (!bp->nge_port_cnt \|\| bp->nge_port != ti->port)
8482		- return;
8483		- bp->nge_port_cnt--;
8484		-
8485		- if (bp->nge_port_cnt != 0)
8486		- return;
8487		-
8488		- set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event);
8489		- break;
8490		- default:
8491		- return;
8492		- }
8493		-
8494		- bnxt_queue_sp_work(bp);
8495		-}
	12117	+static const struct udp_tunnel_nic_info bnxt_udp_tunnels = {
	12118	+ .sync_table = bnxt_udp_tunnel_sync,
	12119	+ .flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP \|
	12120	+ UDP_TUNNEL_NIC_INFO_OPEN_ONLY,
	12121	+ .tables = {
	12122	+ { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, },
	12123	+ { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_GENEVE, },
	12124	+ },
	12125	+};
8496	12126
8497	12127	static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8498	12128	struct net_device *dev, u32 filter_mask,
..	..	@@ -8505,7 +12135,7 @@
8505	12135	}
8506	12136
8507	12137	static int bnxt_bridge_setlink(struct net_device dev, struct nlmsghdr nlh,
8508		- u16 flags)
	12138	+ u16 flags, struct netlink_ext_ack *extack)
8509	12139	{
8510	12140	struct bnxt *bp = netdev_priv(dev);
8511	12141	struct nlattr attr, br_spec;
..	..	@@ -8539,52 +12169,30 @@
8539	12169	return rc;
8540	12170	}
8541	12171
8542		-static int bnxt_get_phys_port_name(struct net_device dev, char buf,
8543		- size_t len)
	12172	+int bnxt_get_port_parent_id(struct net_device *dev,
	12173	+ struct netdev_phys_item_id *ppid)
8544	12174	{
8545	12175	struct bnxt *bp = netdev_priv(dev);
8546		- int rc;
8547	12176
8548		- /* The PF and it's VF-reps only support the switchdev framework */
8549		- if (!BNXT_PF(bp))
8550		- return -EOPNOTSUPP;
8551		-
8552		- rc = snprintf(buf, len, "p%d", bp->pf.port_id);
8553		-
8554		- if (rc >= len)
8555		- return -EOPNOTSUPP;
8556		- return 0;
8557		-}
8558		-
8559		-int bnxt_port_attr_get(struct bnxt bp, struct switchdev_attr attr)
8560		-{
8561	12177	if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV)
8562	12178	return -EOPNOTSUPP;
8563	12179
8564	12180	/* The PF and it's VF-reps only support the switchdev framework */
8565		- if (!BNXT_PF(bp))
	12181	+ if (!BNXT_PF(bp) \|\| !(bp->flags & BNXT_FLAG_DSN_VALID))
8566	12182	return -EOPNOTSUPP;
8567	12183
8568		- switch (attr->id) {
8569		- case SWITCHDEV_ATTR_ID_PORT_PARENT_ID:
8570		- attr->u.ppid.id_len = sizeof(bp->switch_id);
8571		- memcpy(attr->u.ppid.id, bp->switch_id, attr->u.ppid.id_len);
8572		- break;
8573		- default:
8574		- return -EOPNOTSUPP;
8575		- }
	12184	+ ppid->id_len = sizeof(bp->dsn);
	12185	+ memcpy(ppid->id, bp->dsn, ppid->id_len);
	12186	+
8576	12187	return 0;
8577	12188	}
8578	12189
8579		-static int bnxt_swdev_port_attr_get(struct net_device *dev,
8580		- struct switchdev_attr *attr)
	12190	+static struct devlink_port bnxt_get_devlink_port(struct net_device dev)
8581	12191	{
8582		- return bnxt_port_attr_get(netdev_priv(dev), attr);
8583		-}
	12192	+ struct bnxt *bp = netdev_priv(dev);
8584	12193
8585		-static const struct switchdev_ops bnxt_switchdev_ops = {
8586		- .switchdev_port_attr_get = bnxt_swdev_port_attr_get
8587		-};
	12194	+ return &bp->dl_port;
	12195	+}
8588	12196
8589	12197	static const struct net_device_ops bnxt_netdev_ops = {
8590	12198	.ndo_open = bnxt_open,
..	..	@@ -8612,12 +12220,13 @@
8612	12220	#ifdef CONFIG_RFS_ACCEL
8613	12221	.ndo_rx_flow_steer = bnxt_rx_flow_steer,
8614	12222	#endif
8615		- .ndo_udp_tunnel_add = bnxt_udp_tunnel_add,
8616		- .ndo_udp_tunnel_del = bnxt_udp_tunnel_del,
	12223	+ .ndo_udp_tunnel_add = udp_tunnel_nic_add_port,
	12224	+ .ndo_udp_tunnel_del = udp_tunnel_nic_del_port,
8617	12225	.ndo_bpf = bnxt_xdp,
	12226	+ .ndo_xdp_xmit = bnxt_xdp_xmit,
8618	12227	.ndo_bridge_getlink = bnxt_bridge_getlink,
8619	12228	.ndo_bridge_setlink = bnxt_bridge_setlink,
8620		- .ndo_get_phys_port_name = bnxt_get_phys_port_name
	12229	+ .ndo_get_devlink_port = bnxt_get_devlink_port,
8621	12230	};
8622	12231
8623	12232	static void bnxt_remove_one(struct pci_dev *pdev)
..	..	@@ -8625,16 +12234,22 @@
8625	12234	struct net_device *dev = pci_get_drvdata(pdev);
8626	12235	struct bnxt *bp = netdev_priv(dev);
8627	12236
8628		- if (BNXT_PF(bp)) {
	12237	+ if (BNXT_PF(bp))
8629	12238	bnxt_sriov_disable(bp);
8630		- bnxt_dl_unregister(bp);
8631		- }
8632	12239
	12240	+ if (BNXT_PF(bp))
	12241	+ devlink_port_type_clear(&bp->dl_port);
8633	12242	pci_disable_pcie_error_reporting(pdev);
8634	12243	unregister_netdev(dev);
8635		- bnxt_shutdown_tc(bp);
8636		- bnxt_cancel_sp_work(bp);
	12244	+ clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
	12245	+ /* Flush any pending tasks */
	12246	+ cancel_work_sync(&bp->sp_task);
	12247	+ cancel_delayed_work_sync(&bp->fw_reset_task);
8637	12248	bp->sp_event = 0;
	12249	+
	12250	+ bnxt_dl_fw_reporters_destroy(bp, true);
	12251	+ bnxt_dl_unregister(bp);
	12252	+ bnxt_shutdown_tc(bp);
8638	12253
8639	12254	bnxt_clear_int_mode(bp);
8640	12255	bnxt_hwrm_func_drv_unrgtr(bp);
..	..	@@ -8644,11 +12259,19 @@
8644	12259	bnxt_dcb_free(bp);
8645	12260	kfree(bp->edev);
8646	12261	bp->edev = NULL;
	12262	+ kfree(bp->fw_health);
	12263	+ bp->fw_health = NULL;
8647	12264	bnxt_cleanup_pci(bp);
	12265	+ bnxt_free_ctx_mem(bp);
	12266	+ kfree(bp->ctx);
	12267	+ bp->ctx = NULL;
	12268	+ kfree(bp->rss_indir_tbl);
	12269	+ bp->rss_indir_tbl = NULL;
	12270	+ bnxt_free_port_stats(bp);
8648	12271	free_netdev(dev);
8649	12272	}
8650	12273
8651		-static int bnxt_probe_phy(struct bnxt *bp)
	12274	+static int bnxt_probe_phy(struct bnxt *bp, bool fw_dflt)
8652	12275	{
8653	12276	int rc = 0;
8654	12277	struct bnxt_link_info *link_info = &bp->link_info;
..	..	@@ -8659,7 +12282,8 @@
8659	12282	rc);
8660	12283	return rc;
8661	12284	}
8662		- mutex_init(&bp->link_lock);
	12285	+ if (!fw_dflt)
	12286	+ return 0;
8663	12287
8664	12288	rc = bnxt_update_link(bp, false);
8665	12289	if (rc) {
..	..	@@ -8674,27 +12298,8 @@
8674	12298	if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
8675	12299	link_info->support_auto_speeds = link_info->support_speeds;
8676	12300
8677		- /initialize the ethool setting copy with NVM settings /
8678		- if (BNXT_AUTO_MODE(link_info->auto_mode)) {
8679		- link_info->autoneg = BNXT_AUTONEG_SPEED;
8680		- if (bp->hwrm_spec_code >= 0x10201) {
8681		- if (link_info->auto_pause_setting &
8682		- PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
8683		- link_info->autoneg \|= BNXT_AUTONEG_FLOW_CTRL;
8684		- } else {
8685		- link_info->autoneg \|= BNXT_AUTONEG_FLOW_CTRL;
8686		- }
8687		- link_info->advertising = link_info->auto_link_speeds;
8688		- } else {
8689		- link_info->req_link_speed = link_info->force_link_speed;
8690		- link_info->req_duplex = link_info->duplex_setting;
8691		- }
8692		- if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
8693		- link_info->req_flow_ctrl =
8694		- link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
8695		- else
8696		- link_info->req_flow_ctrl = link_info->force_pause_setting;
8697		- return rc;
	12301	+ bnxt_init_ethtool_link_settings(bp);
	12302	+ return 0;
8698	12303	}
8699	12304
8700	12305	static int bnxt_get_max_irq(struct pci_dev *pdev)
..	..	@@ -8712,13 +12317,16 @@
8712	12317	int *max_cp)
8713	12318	{
8714	12319	struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
8715		- int max_ring_grps = 0;
	12320	+ int max_ring_grps = 0, max_irq;
8716	12321
8717	12322	*max_tx = hw_resc->max_tx_rings;
8718	12323	*max_rx = hw_resc->max_rx_rings;
8719		- *max_cp = min_t(int, bnxt_get_max_func_cp_rings_for_en(bp),
8720		- hw_resc->max_irqs - bnxt_get_ulp_msix_num(bp));
8721		- max_cp = min_t(int, max_cp, hw_resc->max_stat_ctxs);
	12324	+ *max_cp = bnxt_get_max_func_cp_rings_for_en(bp);
	12325	+ max_irq = min_t(int, bnxt_get_max_func_irqs(bp) -
	12326	+ bnxt_get_ulp_msix_num(bp),
	12327	+ hw_resc->max_stat_ctxs - bnxt_get_ulp_stat_ctxs(bp));
	12328	+ if (!(bp->flags & BNXT_FLAG_CHIP_P5))
	12329	+ max_cp = min_t(int, max_cp, max_irq);
8722	12330	max_ring_grps = hw_resc->max_hw_ring_grps;
8723	12331	if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
8724	12332	*max_cp -= 1;
..	..	@@ -8726,6 +12334,11 @@
8726	12334	}
8727	12335	if (bp->flags & BNXT_FLAG_AGG_RINGS)
8728	12336	*max_rx >>= 1;
	12337	+ if (bp->flags & BNXT_FLAG_CHIP_P5) {
	12338	+ bnxt_trim_rings(bp, max_rx, max_tx, *max_cp, false);
	12339	+ /* On P5 chips, max_cp output param should be available NQs */
	12340	+ *max_cp = max_irq;
	12341	+ }
8729	12342	max_rx = min_t(int, max_rx, max_ring_grps);
8730	12343	}
8731	12344
..	..	@@ -8807,7 +12420,7 @@
8807	12420
8808	12421	if (sh)
8809	12422	bp->flags \|= BNXT_FLAG_SHARED_RINGS;
8810		- dflt_rings = netif_get_num_default_rss_queues();
	12423	+ dflt_rings = is_kdump_kernel() ? 1 : netif_get_num_default_rss_queues();
8811	12424	/* Reduce default rings on multi-port cards so that total default
8812	12425	* rings do not exceed CPU count.
8813	12426	*/
..	..	@@ -8842,7 +12455,6 @@
8842	12455	netdev_warn(bp->dev, "2nd rings reservation failed.\n");
8843	12456	bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
8844	12457	}
8845		- bp->num_stat_ctxs = bp->cp_nr_rings;
8846	12458	if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
8847	12459	bp->rx_nr_rings++;
8848	12460	bp->cp_nr_rings++;
..	..	@@ -8873,10 +12485,9 @@
8873	12485	goto init_dflt_ring_err;
8874	12486
8875	12487	bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
8876		- if (bnxt_rfs_supported(bp) && bnxt_rfs_capable(bp)) {
8877		- bp->flags \|= BNXT_FLAG_RFS;
8878		- bp->dev->features \|= NETIF_F_NTUPLE;
8879		- }
	12488	+
	12489	+ bnxt_set_dflt_rfs(bp);
	12490	+
8880	12491	init_dflt_ring_err:
8881	12492	bnxt_ulp_irq_restart(bp, rc);
8882	12493	return rc;
..	..	@@ -8934,9 +12545,94 @@
8934	12545	return rc;
8935	12546	}
8936	12547
	12548	+#define BNXT_VPD_LEN 512
	12549	+static void bnxt_vpd_read_info(struct bnxt *bp)
	12550	+{
	12551	+ struct pci_dev *pdev = bp->pdev;
	12552	+ int i, len, pos, ro_size, size;
	12553	+ ssize_t vpd_size;
	12554	+ u8 *vpd_data;
	12555	+
	12556	+ vpd_data = kmalloc(BNXT_VPD_LEN, GFP_KERNEL);
	12557	+ if (!vpd_data)
	12558	+ return;
	12559	+
	12560	+ vpd_size = pci_read_vpd(pdev, 0, BNXT_VPD_LEN, vpd_data);
	12561	+ if (vpd_size <= 0) {
	12562	+ netdev_err(bp->dev, "Unable to read VPD\n");
	12563	+ goto exit;
	12564	+ }
	12565	+
	12566	+ i = pci_vpd_find_tag(vpd_data, 0, vpd_size, PCI_VPD_LRDT_RO_DATA);
	12567	+ if (i < 0) {
	12568	+ netdev_err(bp->dev, "VPD READ-Only not found\n");
	12569	+ goto exit;
	12570	+ }
	12571	+
	12572	+ ro_size = pci_vpd_lrdt_size(&vpd_data[i]);
	12573	+ i += PCI_VPD_LRDT_TAG_SIZE;
	12574	+ if (i + ro_size > vpd_size)
	12575	+ goto exit;
	12576	+
	12577	+ pos = pci_vpd_find_info_keyword(vpd_data, i, ro_size,
	12578	+ PCI_VPD_RO_KEYWORD_PARTNO);
	12579	+ if (pos < 0)
	12580	+ goto read_sn;
	12581	+
	12582	+ len = pci_vpd_info_field_size(&vpd_data[pos]);
	12583	+ pos += PCI_VPD_INFO_FLD_HDR_SIZE;
	12584	+ if (len + pos > vpd_size)
	12585	+ goto read_sn;
	12586	+
	12587	+ size = min(len, BNXT_VPD_FLD_LEN - 1);
	12588	+ memcpy(bp->board_partno, &vpd_data[pos], size);
	12589	+
	12590	+read_sn:
	12591	+ pos = pci_vpd_find_info_keyword(vpd_data, i, ro_size,
	12592	+ PCI_VPD_RO_KEYWORD_SERIALNO);
	12593	+ if (pos < 0)
	12594	+ goto exit;
	12595	+
	12596	+ len = pci_vpd_info_field_size(&vpd_data[pos]);
	12597	+ pos += PCI_VPD_INFO_FLD_HDR_SIZE;
	12598	+ if (len + pos > vpd_size)
	12599	+ goto exit;
	12600	+
	12601	+ size = min(len, BNXT_VPD_FLD_LEN - 1);
	12602	+ memcpy(bp->board_serialno, &vpd_data[pos], size);
	12603	+exit:
	12604	+ kfree(vpd_data);
	12605	+}
	12606	+
	12607	+static int bnxt_pcie_dsn_get(struct bnxt *bp, u8 dsn[])
	12608	+{
	12609	+ struct pci_dev *pdev = bp->pdev;
	12610	+ u64 qword;
	12611	+
	12612	+ qword = pci_get_dsn(pdev);
	12613	+ if (!qword) {
	12614	+ netdev_info(bp->dev, "Unable to read adapter's DSN\n");
	12615	+ return -EOPNOTSUPP;
	12616	+ }
	12617	+
	12618	+ put_unaligned_le64(qword, dsn);
	12619	+
	12620	+ bp->flags \|= BNXT_FLAG_DSN_VALID;
	12621	+ return 0;
	12622	+}
	12623	+
	12624	+static int bnxt_map_db_bar(struct bnxt *bp)
	12625	+{
	12626	+ if (!bp->db_size)
	12627	+ return -ENODEV;
	12628	+ bp->bar1 = pci_iomap(bp->pdev, 2, bp->db_size);
	12629	+ if (!bp->bar1)
	12630	+ return -ENOMEM;
	12631	+ return 0;
	12632	+}
	12633	+
8937	12634	static int bnxt_init_one(struct pci_dev pdev, const struct pci_device_id ent)
8938	12635	{
8939		- static int version_printed;
8940	12636	struct net_device *dev;
8941	12637	struct bnxt *bp;
8942	12638	int rc, max_irqs;
..	..	@@ -8944,8 +12640,13 @@
8944	12640	if (pci_is_bridge(pdev))
8945	12641	return -ENODEV;
8946	12642
8947		- if (version_printed++ == 0)
8948		- pr_info("%s", version);
	12643	+ /* Clear any pending DMA transactions from crash kernel
	12644	+ * while loading driver in capture kernel.
	12645	+ */
	12646	+ if (is_kdump_kernel()) {
	12647	+ pci_clear_master(pdev);
	12648	+ pcie_flr(pdev);
	12649	+ }
8949	12650
8950	12651	max_irqs = bnxt_get_max_irq(pdev);
8951	12652	dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
..	..	@@ -8953,6 +12654,8 @@
8953	12654	return -ENOMEM;
8954	12655
8955	12656	bp = netdev_priv(dev);
	12657	+ bp->msg_enable = BNXT_DEF_MSG_ENABLE;
	12658	+ bnxt_set_max_func_irqs(bp, max_irqs);
8956	12659
8957	12660	if (bnxt_vf_pciid(ent->driver_data))
8958	12661	bp->flags \|= BNXT_FLAG_VF;
..	..	@@ -8967,29 +12670,42 @@
8967	12670	dev->netdev_ops = &bnxt_netdev_ops;
8968	12671	dev->watchdog_timeo = BNXT_TX_TIMEOUT;
8969	12672	dev->ethtool_ops = &bnxt_ethtool_ops;
8970		- SWITCHDEV_SET_OPS(dev, &bnxt_switchdev_ops);
8971	12673	pci_set_drvdata(pdev, dev);
	12674	+
	12675	+ if (BNXT_PF(bp))
	12676	+ bnxt_vpd_read_info(bp);
8972	12677
8973	12678	rc = bnxt_alloc_hwrm_resources(bp);
8974	12679	if (rc)
8975	12680	goto init_err_pci_clean;
8976	12681
8977	12682	mutex_init(&bp->hwrm_cmd_lock);
8978		- rc = bnxt_hwrm_ver_get(bp);
	12683	+ mutex_init(&bp->link_lock);
	12684	+
	12685	+ rc = bnxt_fw_init_one_p1(bp);
8979	12686	if (rc)
8980	12687	goto init_err_pci_clean;
8981	12688
8982		- if (bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) {
8983		- rc = bnxt_alloc_hwrm_short_cmd_req(bp);
8984		- if (rc)
8985		- goto init_err_pci_clean;
	12689	+ if (BNXT_CHIP_P5(bp)) {
	12690	+ bp->flags \|= BNXT_FLAG_CHIP_P5;
	12691	+ if (BNXT_CHIP_SR2(bp))
	12692	+ bp->flags \|= BNXT_FLAG_CHIP_SR2;
8986	12693	}
8987	12694
8988		- rc = bnxt_hwrm_func_reset(bp);
	12695	+ rc = bnxt_alloc_rss_indir_tbl(bp);
8989	12696	if (rc)
8990	12697	goto init_err_pci_clean;
8991	12698
8992		- bnxt_hwrm_fw_set_time(bp);
	12699	+ rc = bnxt_fw_init_one_p2(bp);
	12700	+ if (rc)
	12701	+ goto init_err_pci_clean;
	12702	+
	12703	+ rc = bnxt_map_db_bar(bp);
	12704	+ if (rc) {
	12705	+ dev_err(&pdev->dev, "Cannot map doorbell BAR rc = %d, aborting\n",
	12706	+ rc);
	12707	+ goto init_err_pci_clean;
	12708	+ }
8993	12709
8994	12710	dev->hw_features = NETIF_F_IP_CSUM \| NETIF_F_IPV6_CSUM \| NETIF_F_SG \|
8995	12711	NETIF_F_TSO \| NETIF_F_TSO6 \|
..	..	@@ -8999,7 +12715,7 @@
8999	12715	NETIF_F_GSO_PARTIAL \| NETIF_F_RXHASH \|
9000	12716	NETIF_F_RXCSUM \| NETIF_F_GRO;
9001	12717
9002		- if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
	12718	+ if (BNXT_SUPPORTS_TPA(bp))
9003	12719	dev->hw_features \|= NETIF_F_LRO;
9004	12720
9005	12721	dev->hw_enc_features =
..	..	@@ -9008,12 +12724,16 @@
9008	12724	NETIF_F_GSO_UDP_TUNNEL \| NETIF_F_GSO_GRE \|
9009	12725	NETIF_F_GSO_UDP_TUNNEL_CSUM \| NETIF_F_GSO_GRE_CSUM \|
9010	12726	NETIF_F_GSO_IPXIP4 \| NETIF_F_GSO_PARTIAL;
	12727	+ dev->udp_tunnel_nic_info = &bnxt_udp_tunnels;
	12728	+
9011	12729	dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM \|
9012	12730	NETIF_F_GSO_GRE_CSUM;
9013	12731	dev->vlan_features = dev->hw_features \| NETIF_F_HIGHDMA;
9014		- dev->hw_features \|= NETIF_F_HW_VLAN_CTAG_RX \| NETIF_F_HW_VLAN_CTAG_TX \|
9015		- NETIF_F_HW_VLAN_STAG_RX \| NETIF_F_HW_VLAN_STAG_TX;
9016		- if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
	12732	+ if (bp->fw_cap & BNXT_FW_CAP_VLAN_RX_STRIP)
	12733	+ dev->hw_features \|= BNXT_HW_FEATURE_VLAN_ALL_RX;
	12734	+ if (bp->fw_cap & BNXT_FW_CAP_VLAN_TX_INSERT)
	12735	+ dev->hw_features \|= BNXT_HW_FEATURE_VLAN_ALL_TX;
	12736	+ if (BNXT_SUPPORTS_TPA(bp))
9017	12737	dev->hw_features \|= NETIF_F_GRO_HW;
9018	12738	dev->features \|= dev->hw_features \| NETIF_F_HIGHDMA;
9019	12739	if (dev->features & NETIF_F_GRO_HW)
..	..	@@ -9024,61 +12744,41 @@
9024	12744	init_waitqueue_head(&bp->sriov_cfg_wait);
9025	12745	mutex_init(&bp->sriov_lock);
9026	12746	#endif
9027		- bp->gro_func = bnxt_gro_func_5730x;
9028		- if (BNXT_CHIP_P4_PLUS(bp))
9029		- bp->gro_func = bnxt_gro_func_5731x;
9030		- else
	12747	+ if (BNXT_SUPPORTS_TPA(bp)) {
	12748	+ bp->gro_func = bnxt_gro_func_5730x;
	12749	+ if (BNXT_CHIP_P4(bp))
	12750	+ bp->gro_func = bnxt_gro_func_5731x;
	12751	+ else if (BNXT_CHIP_P5(bp))
	12752	+ bp->gro_func = bnxt_gro_func_5750x;
	12753	+ }
	12754	+ if (!BNXT_CHIP_P4_PLUS(bp))
9031	12755	bp->flags \|= BNXT_FLAG_DOUBLE_DB;
9032		-
9033		- rc = bnxt_hwrm_func_drv_rgtr(bp);
9034		- if (rc)
9035		- goto init_err_pci_clean;
9036		-
9037		- rc = bnxt_hwrm_func_rgtr_async_events(bp, NULL, 0);
9038		- if (rc)
9039		- goto init_err_pci_clean;
9040	12756
9041	12757	bp->ulp_probe = bnxt_ulp_probe;
9042	12758
9043		- /* Get the MAX capabilities for this function */
9044		- rc = bnxt_hwrm_func_qcaps(bp);
9045		- if (rc) {
9046		- netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
9047		- rc);
9048		- rc = -1;
9049		- goto init_err_pci_clean;
9050		- }
9051	12759	rc = bnxt_init_mac_addr(bp);
9052	12760	if (rc) {
9053	12761	dev_err(&pdev->dev, "Unable to initialize mac address.\n");
9054	12762	rc = -EADDRNOTAVAIL;
9055	12763	goto init_err_pci_clean;
9056	12764	}
9057		- rc = bnxt_hwrm_queue_qportcfg(bp);
9058		- if (rc) {
9059		- netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
9060		- rc);
9061		- rc = -1;
9062		- goto init_err_pci_clean;
9063		- }
9064	12765
9065		- bnxt_hwrm_func_qcfg(bp);
9066		- bnxt_hwrm_port_led_qcaps(bp);
9067		- bnxt_ethtool_init(bp);
9068		- bnxt_dcb_init(bp);
	12766	+ if (BNXT_PF(bp)) {
	12767	+ /* Read the adapter's DSN to use as the eswitch switch_id */
	12768	+ rc = bnxt_pcie_dsn_get(bp, bp->dsn);
	12769	+ }
9069	12770
9070	12771	/* MTU range: 60 - FW defined max */
9071	12772	dev->min_mtu = ETH_ZLEN;
9072	12773	dev->max_mtu = bp->max_mtu;
9073	12774
9074		- rc = bnxt_probe_phy(bp);
	12775	+ rc = bnxt_probe_phy(bp, true);
9075	12776	if (rc)
9076	12777	goto init_err_pci_clean;
9077	12778
9078	12779	bnxt_set_rx_skb_mode(bp, false);
9079	12780	bnxt_set_tpa_flags(bp);
9080	12781	bnxt_set_ring_params(bp);
9081		- bnxt_set_max_func_irqs(bp, max_irqs);
9082	12782	rc = bnxt_set_dflt_rings(bp, true);
9083	12783	if (rc) {
9084	12784	netdev_err(bp->dev, "Not enough rings available.\n");
..	..	@@ -9086,27 +12786,9 @@
9086	12786	goto init_err_pci_clean;
9087	12787	}
9088	12788
9089		- /* Default RSS hash cfg. */
9090		- bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 \|
9091		- VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 \|
9092		- VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 \|
9093		- VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
9094		- if (BNXT_CHIP_P4_PLUS(bp) && bp->hwrm_spec_code >= 0x10501) {
9095		- bp->flags \|= BNXT_FLAG_UDP_RSS_CAP;
9096		- bp->rss_hash_cfg \|= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 \|
9097		- VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
9098		- }
	12789	+ bnxt_fw_init_one_p3(bp);
9099	12790
9100		- bnxt_hwrm_vnic_qcaps(bp);
9101		- if (bnxt_rfs_supported(bp)) {
9102		- dev->hw_features \|= NETIF_F_NTUPLE;
9103		- if (bnxt_rfs_capable(bp)) {
9104		- bp->flags \|= BNXT_FLAG_RFS;
9105		- dev->features \|= NETIF_F_NTUPLE;
9106		- }
9107		- }
9108		-
9109		- if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
	12791	+ if (dev->hw_features & BNXT_HW_FEATURE_VLAN_ALL_RX)
9110	12792	bp->flags \|= BNXT_FLAG_STRIP_VLAN;
9111	12793
9112	12794	rc = bnxt_init_int_mode(bp);
..	..	@@ -9118,14 +12800,6 @@
9118	12800	*/
9119	12801	bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
9120	12802
9121		- bnxt_get_wol_settings(bp);
9122		- if (bp->flags & BNXT_FLAG_WOL_CAP)
9123		- device_set_wakeup_enable(&pdev->dev, bp->wol);
9124		- else
9125		- device_set_wakeup_capable(&pdev->dev, false);
9126		-
9127		- bnxt_hwrm_set_cache_line_size(bp, cache_line_size());
9128		-
9129	12803	if (BNXT_PF(bp)) {
9130	12804	if (!bnxt_pf_wq) {
9131	12805	bnxt_pf_wq =
..	..	@@ -9136,15 +12810,21 @@
9136	12810	goto init_err_pci_clean;
9137	12811	}
9138	12812	}
9139		- bnxt_init_tc(bp);
	12813	+ rc = bnxt_init_tc(bp);
	12814	+ if (rc)
	12815	+ netdev_err(dev, "Failed to initialize TC flower offload, err = %d.\n",
	12816	+ rc);
9140	12817	}
	12818	+
	12819	+ bnxt_dl_register(bp);
9141	12820
9142	12821	rc = register_netdev(dev);
9143	12822	if (rc)
9144		- goto init_err_cleanup_tc;
	12823	+ goto init_err_cleanup;
9145	12824
9146	12825	if (BNXT_PF(bp))
9147		- bnxt_dl_register(bp);
	12826	+ devlink_port_type_eth_set(&bp->dl_port, bp->dev);
	12827	+ bnxt_dl_fw_reporters_create(bp);
9148	12828
9149	12829	netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
9150	12830	board_info[ent->driver_data].name,
..	..	@@ -9154,14 +12834,24 @@
9154	12834	pci_save_state(pdev);
9155	12835	return 0;
9156	12836
9157		-init_err_cleanup_tc:
	12837	+init_err_cleanup:
	12838	+ bnxt_dl_unregister(bp);
9158	12839	bnxt_shutdown_tc(bp);
9159	12840	bnxt_clear_int_mode(bp);
9160	12841
9161	12842	init_err_pci_clean:
	12843	+ bnxt_hwrm_func_drv_unrgtr(bp);
9162	12844	bnxt_free_hwrm_short_cmd_req(bp);
9163	12845	bnxt_free_hwrm_resources(bp);
	12846	+ bnxt_ethtool_free(bp);
	12847	+ kfree(bp->fw_health);
	12848	+ bp->fw_health = NULL;
9164	12849	bnxt_cleanup_pci(bp);
	12850	+ bnxt_free_ctx_mem(bp);
	12851	+ kfree(bp->ctx);
	12852	+ bp->ctx = NULL;
	12853	+ kfree(bp->rss_indir_tbl);
	12854	+ bp->rss_indir_tbl = NULL;
9165	12855
9166	12856	init_err_free:
9167	12857	free_netdev(dev);
..	..	@@ -9185,9 +12875,10 @@
9185	12875	dev_close(dev);
9186	12876
9187	12877	bnxt_ulp_shutdown(bp);
	12878	+ bnxt_clear_int_mode(bp);
	12879	+ pci_disable_device(pdev);
9188	12880
9189	12881	if (system_state == SYSTEM_POWER_OFF) {
9190		- bnxt_clear_int_mode(bp);
9191	12882	pci_wake_from_d3(pdev, bp->wol);
9192	12883	pci_set_power_state(pdev, PCI_D3hot);
9193	12884	}
..	..	@@ -9199,30 +12890,40 @@
9199	12890	#ifdef CONFIG_PM_SLEEP
9200	12891	static int bnxt_suspend(struct device *device)
9201	12892	{
9202		- struct pci_dev *pdev = to_pci_dev(device);
9203		- struct net_device *dev = pci_get_drvdata(pdev);
	12893	+ struct net_device *dev = dev_get_drvdata(device);
9204	12894	struct bnxt *bp = netdev_priv(dev);
9205	12895	int rc = 0;
9206	12896
9207	12897	rtnl_lock();
	12898	+ bnxt_ulp_stop(bp);
9208	12899	if (netif_running(dev)) {
9209	12900	netif_device_detach(dev);
9210	12901	rc = bnxt_close(dev);
9211	12902	}
9212	12903	bnxt_hwrm_func_drv_unrgtr(bp);
	12904	+ pci_disable_device(bp->pdev);
	12905	+ bnxt_free_ctx_mem(bp);
	12906	+ kfree(bp->ctx);
	12907	+ bp->ctx = NULL;
9213	12908	rtnl_unlock();
9214	12909	return rc;
9215	12910	}
9216	12911
9217	12912	static int bnxt_resume(struct device *device)
9218	12913	{
9219		- struct pci_dev *pdev = to_pci_dev(device);
9220		- struct net_device *dev = pci_get_drvdata(pdev);
	12914	+ struct net_device *dev = dev_get_drvdata(device);
9221	12915	struct bnxt *bp = netdev_priv(dev);
9222	12916	int rc = 0;
9223	12917
9224	12918	rtnl_lock();
9225		- if (bnxt_hwrm_ver_get(bp) \|\| bnxt_hwrm_func_drv_rgtr(bp)) {
	12919	+ rc = pci_enable_device(bp->pdev);
	12920	+ if (rc) {
	12921	+ netdev_err(dev, "Cannot re-enable PCI device during resume, err = %d\n",
	12922	+ rc);
	12923	+ goto resume_exit;
	12924	+ }
	12925	+ pci_set_master(bp->pdev);
	12926	+ if (bnxt_hwrm_ver_get(bp)) {
9226	12927	rc = -ENODEV;
9227	12928	goto resume_exit;
9228	12929	}
..	..	@@ -9231,6 +12932,16 @@
9231	12932	rc = -EBUSY;
9232	12933	goto resume_exit;
9233	12934	}
	12935	+
	12936	+ rc = bnxt_hwrm_func_qcaps(bp);
	12937	+ if (rc)
	12938	+ goto resume_exit;
	12939	+
	12940	+ if (bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, false)) {
	12941	+ rc = -ENODEV;
	12942	+ goto resume_exit;
	12943	+ }
	12944	+
9234	12945	bnxt_get_wol_settings(bp);
9235	12946	if (netif_running(dev)) {
9236	12947	rc = bnxt_open(dev);
..	..	@@ -9239,6 +12950,9 @@
9239	12950	}
9240	12951
9241	12952	resume_exit:
	12953	+ bnxt_ulp_start(bp, rc);
	12954	+ if (!rc)
	12955	+ bnxt_reenable_sriov(bp);
9242	12956	rtnl_unlock();
9243	12957	return rc;
9244	12958	}
..	..	@@ -9278,10 +12992,17 @@
9278	12992	return PCI_ERS_RESULT_DISCONNECT;
9279	12993	}
9280	12994
	12995	+ if (state == pci_channel_io_frozen)
	12996	+ set_bit(BNXT_STATE_PCI_CHANNEL_IO_FROZEN, &bp->state);
	12997	+
9281	12998	if (netif_running(netdev))
9282	12999	bnxt_close(netdev);
9283	13000
9284		- pci_disable_device(pdev);
	13001	+ if (pci_is_enabled(pdev))
	13002	+ pci_disable_device(pdev);
	13003	+ bnxt_free_ctx_mem(bp);
	13004	+ kfree(bp->ctx);
	13005	+ bp->ctx = NULL;
9285	13006	rtnl_unlock();
9286	13007
9287	13008	/* Request a slot slot reset. */
..	..	@@ -9299,10 +13020,10 @@
9299	13020	*/
9300	13021	static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
9301	13022	{
	13023	+ pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
9302	13024	struct net_device *netdev = pci_get_drvdata(pdev);
9303	13025	struct bnxt *bp = netdev_priv(netdev);
9304		- int err = 0;
9305		- pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
	13026	+ int err = 0, off;
9306	13027
9307	13028	netdev_info(bp->dev, "PCI Slot Reset\n");
9308	13029
..	..	@@ -9313,33 +13034,29 @@
9313	13034	"Cannot re-enable PCI device after reset.\n");
9314	13035	} else {
9315	13036	pci_set_master(pdev);
	13037	+ /* Upon fatal error, our device internal logic that latches to
	13038	+ * BAR value is getting reset and will restore only upon
	13039	+ * rewritting the BARs.
	13040	+ *
	13041	+ * As pci_restore_state() does not re-write the BARs if the
	13042	+ * value is same as saved value earlier, driver needs to
	13043	+ * write the BARs to 0 to force restore, in case of fatal error.
	13044	+ */
	13045	+ if (test_and_clear_bit(BNXT_STATE_PCI_CHANNEL_IO_FROZEN,
	13046	+ &bp->state)) {
	13047	+ for (off = PCI_BASE_ADDRESS_0;
	13048	+ off <= PCI_BASE_ADDRESS_5; off += 4)
	13049	+ pci_write_config_dword(bp->pdev, off, 0);
	13050	+ }
9316	13051	pci_restore_state(pdev);
9317	13052	pci_save_state(pdev);
9318	13053
9319	13054	err = bnxt_hwrm_func_reset(bp);
9320		- if (!err && netif_running(netdev))
9321		- err = bnxt_open(netdev);
9322		-
9323		- if (!err) {
	13055	+ if (!err)
9324	13056	result = PCI_ERS_RESULT_RECOVERED;
9325		- bnxt_ulp_start(bp);
9326		- }
9327		- }
9328		-
9329		- if (result != PCI_ERS_RESULT_RECOVERED) {
9330		- if (netif_running(netdev))
9331		- dev_close(netdev);
9332		- pci_disable_device(pdev);
9333	13057	}
9334	13058
9335	13059	rtnl_unlock();
9336		-
9337		- err = pci_cleanup_aer_uncorrect_error_status(pdev);
9338		- if (err) {
9339		- dev_err(&pdev->dev,
9340		- "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
9341		- err); /* non-fatal, continue */
9342		- }
9343	13060
9344	13061	return result;
9345	13062	}
..	..	@@ -9354,10 +13071,21 @@
9354	13071	static void bnxt_io_resume(struct pci_dev *pdev)
9355	13072	{
9356	13073	struct net_device *netdev = pci_get_drvdata(pdev);
	13074	+ struct bnxt *bp = netdev_priv(netdev);
	13075	+ int err;
9357	13076
	13077	+ netdev_info(bp->dev, "PCI Slot Resume\n");
9358	13078	rtnl_lock();
9359	13079
9360		- netif_device_attach(netdev);
	13080	+ err = bnxt_hwrm_func_qcaps(bp);
	13081	+ if (!err && netif_running(netdev))
	13082	+ err = bnxt_open(netdev);
	13083	+
	13084	+ bnxt_ulp_start(bp, err);
	13085	+ if (!err) {
	13086	+ bnxt_reenable_sriov(bp);
	13087	+ netif_device_attach(netdev);
	13088	+ }
9361	13089
9362	13090	rtnl_unlock();
9363	13091	}
..	..	@@ -9383,8 +13111,16 @@
9383	13111
9384	13112	static int __init bnxt_init(void)
9385	13113	{
	13114	+ int err;
	13115	+
9386	13116	bnxt_debug_init();
9387		- return pci_register_driver(&bnxt_pci_driver);
	13117	+ err = pci_register_driver(&bnxt_pci_driver);
	13118	+ if (err) {
	13119	+ bnxt_debug_exit();
	13120	+ return err;
	13121	+ }
	13122	+
	13123	+ return 0;
9388	13124	}
9389	13125
9390	13126	static void __exit bnxt_exit(void)