forked from ~ljy/RK356X_SDK_RELEASE

blame | history | patch | commit | commitdiff
hc
2023-12-06 08f87f769b595151be1afeff53e144f543faa614 
 kernel/drivers/net/dsa/mv88e6xxx/chip.h
....@@ -1,17 +1,14 @@
1
+/* SPDX-License-Identifier: GPL-2.0-or-later */
12 /*
23  * Marvell 88E6xxx Ethernet switch single-chip definition
34  *
45  * Copyright (c) 2008 Marvell Semiconductor
5
- *
6
- * This program is free software; you can redistribute it and/or modify
7
- * it under the terms of the GNU General Public License as published by
8
- * the Free Software Foundation; either version 2 of the License, or
9
- * (at your option) any later version.
106  */
117 
128 #ifndef _MV88E6XXX_CHIP_H
139 #define _MV88E6XXX_CHIP_H
1410 
11
+#include <linux/idr.h>
1512 #include <linux/if_vlan.h>
1613 #include <linux/irq.h>
1714 #include <linux/gpio/consumer.h>
....@@ -21,17 +18,7 @@
2118 #include <linux/timecounter.h>
2219 #include <net/dsa.h>
2320 
24
-#define SMI_CMD			0x00
25
-#define SMI_CMD_BUSY		BIT(15)
26
-#define SMI_CMD_CLAUSE_22	BIT(12)
27
-#define SMI_CMD_OP_22_WRITE	((1 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
28
-#define SMI_CMD_OP_22_READ	((2 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
29
-#define SMI_CMD_OP_45_WRITE_ADDR	((0 << 10) | SMI_CMD_BUSY)
30
-#define SMI_CMD_OP_45_WRITE_DATA	((1 << 10) | SMI_CMD_BUSY)
31
-#define SMI_CMD_OP_45_READ_DATA		((2 << 10) | SMI_CMD_BUSY)
32
-#define SMI_CMD_OP_45_READ_DATA_INC	((3 << 10) | SMI_CMD_BUSY)
33
-#define SMI_DATA		0x01
34
-
21
+#define EDSA_HLEN		8
3522 #define MV88E6XXX_N_FID		4096
3623 
3724 /* PVT limits for 4-bit port and 5-bit switch */
....@@ -45,6 +32,11 @@
4532 	MV88E6XXX_EGRESS_MODE_UNTAGGED,
4633 	MV88E6XXX_EGRESS_MODE_TAGGED,
4734 	MV88E6XXX_EGRESS_MODE_ETHERTYPE,
35
+};
36
+
37
+enum mv88e6xxx_egress_direction {
38
+        MV88E6XXX_EGRESS_DIR_INGRESS,
39
+        MV88E6XXX_EGRESS_DIR_EGRESS,
4840 };
4941 
5042 enum mv88e6xxx_frame_mode {
....@@ -72,7 +64,9 @@
7264 	MV88E6190,
7365 	MV88E6190X,
7466 	MV88E6191,
67
+	MV88E6220,
7568 	MV88E6240,
69
+	MV88E6250,
7670 	MV88E6290,
7771 	MV88E6320,
7872 	MV88E6321,
....@@ -91,6 +85,7 @@
9185 	MV88E6XXX_FAMILY_6097,	/* 6046 6085 6096 6097 */
9286 	MV88E6XXX_FAMILY_6165,	/* 6123 6161 6165 */
9387 	MV88E6XXX_FAMILY_6185,	/* 6108 6121 6122 6131 6152 6155 6182 6185 */
88
+	MV88E6XXX_FAMILY_6250,	/* 6220 6250 */
9489 	MV88E6XXX_FAMILY_6320,	/* 6320 6321 */
9590 	MV88E6XXX_FAMILY_6341,	/* 6141 6341 */
9691 	MV88E6XXX_FAMILY_6351,	/* 6171 6175 6350 6351 */
....@@ -105,6 +100,7 @@
105100 	u16 prod_num;
106101 	const char *name;
107102 	unsigned int num_databases;
103
+	unsigned int num_macs;
108104 	unsigned int num_ports;
109105 	unsigned int num_internal_phys;
110106 	unsigned int num_gpio;
....@@ -118,11 +114,22 @@
118114 	unsigned int g2_irqs;
119115 	bool pvt;
120116 
117
+	/* Mark certain ports as invalid. This is required for example for the
118
+	 * MV88E6220 (which is in general a MV88E6250 with 7 ports) but the
119
+	 * ports 2-4 are not routet to pins.
120
+	 */
121
+	unsigned int invalid_port_mask;
121122 	/* Multi-chip Addressing Mode.
122123 	 * Some chips respond to only 2 registers of its own SMI device address
123124 	 * when it is non-zero, and use indirect access to internal registers.
124125 	 */
125126 	bool multi_chip;
127
+	/* Dual-chip Addressing Mode
128
+	 * Some chips respond to only half of the 32 SMI addresses,
129
+	 * allowing two to coexist on the same SMI interface.
130
+	 */
131
+	bool dual_chip;
132
+
126133 	enum dsa_tag_protocol tag_protocol;
127134 
128135 	/* Mask for FromPort and ToPort value of PortVec used in ATU Move
....@@ -161,7 +168,7 @@
161168 	u16 masked;
162169 	struct irq_chip chip;
163170 	struct irq_domain *domain;
164
-	unsigned int nirqs;
171
+	int nirqs;
165172 };
166173 
167174 /* state flags for mv88e6xxx_port_hwtstamp::state */
....@@ -190,6 +197,33 @@
190197 	struct hwtstamp_config tstamp_config;
191198 };
192199 
200
+enum mv88e6xxx_policy_mapping {
201
+	MV88E6XXX_POLICY_MAPPING_DA,
202
+	MV88E6XXX_POLICY_MAPPING_SA,
203
+	MV88E6XXX_POLICY_MAPPING_VTU,
204
+	MV88E6XXX_POLICY_MAPPING_ETYPE,
205
+	MV88E6XXX_POLICY_MAPPING_PPPOE,
206
+	MV88E6XXX_POLICY_MAPPING_VBAS,
207
+	MV88E6XXX_POLICY_MAPPING_OPT82,
208
+	MV88E6XXX_POLICY_MAPPING_UDP,
209
+};
210
+
211
+enum mv88e6xxx_policy_action {
212
+	MV88E6XXX_POLICY_ACTION_NORMAL,
213
+	MV88E6XXX_POLICY_ACTION_MIRROR,
214
+	MV88E6XXX_POLICY_ACTION_TRAP,
215
+	MV88E6XXX_POLICY_ACTION_DISCARD,
216
+};
217
+
218
+struct mv88e6xxx_policy {
219
+	enum mv88e6xxx_policy_mapping mapping;
220
+	enum mv88e6xxx_policy_action action;
221
+	struct ethtool_rx_flow_spec fs;
222
+	u8 addr[ETH_ALEN];
223
+	int port;
224
+	u16 vid;
225
+};
226
+
193227 struct mv88e6xxx_port {
194228 	struct mv88e6xxx_chip *chip;
195229 	int port;
....@@ -199,8 +233,25 @@
199233 	u64 atu_full_violation;
200234 	u64 vtu_member_violation;
201235 	u64 vtu_miss_violation;
236
+	phy_interface_t interface;
202237 	u8 cmode;
203
-	int serdes_irq;
238
+	bool mirror_ingress;
239
+	bool mirror_egress;
240
+	unsigned int serdes_irq;
241
+	char serdes_irq_name[64];
242
+	struct devlink_region *region;
243
+};
244
+
245
+enum mv88e6xxx_region_id {
246
+	MV88E6XXX_REGION_GLOBAL1 = 0,
247
+	MV88E6XXX_REGION_GLOBAL2,
248
+	MV88E6XXX_REGION_ATU,
249
+
250
+	_MV88E6XXX_REGION_MAX,
251
+};
252
+
253
+struct mv88e6xxx_region_priv {
254
+	enum mv88e6xxx_region_id id;
204255 };
205256 
206257 struct mv88e6xxx_chip {
....@@ -248,17 +299,25 @@
248299 	/* List of mdio busses */
249300 	struct list_head mdios;
250301 
302
+	/* Policy Control List IDs and rules */
303
+	struct idr policies;
304
+
251305 	/* There can be two interrupt controllers, which are chained
252306 	 * off a GPIO as interrupt source
253307 	 */
254308 	struct mv88e6xxx_irq g1_irq;
255309 	struct mv88e6xxx_irq g2_irq;
256310 	int irq;
311
+	char irq_name[64];
257312 	int device_irq;
313
+	char device_irq_name[64];
258314 	int watchdog_irq;
315
+	char watchdog_irq_name[64];
259316 
260317 	int atu_prob_irq;
318
+	char atu_prob_irq_name[64];
261319 	int vtu_prob_irq;
320
+	char vtu_prob_irq_name[64];
262321 	struct kthread_worker *kworker;
263322 	struct kthread_delayed_work irq_poll_work;
264323 
....@@ -280,11 +339,18 @@
280339 	u16 evcap_config;
281340 	u16 enable_count;
282341 
342
+	/* Current ingress and egress monitor ports */
343
+	int egress_dest_port;
344
+	int ingress_dest_port;
345
+
283346 	/* Per-port timestamping resources. */
284347 	struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS];
285348 
286349 	/* Array of port structures. */
287350 	struct mv88e6xxx_port ports[DSA_MAX_PORTS];
351
+
352
+	/* devlink regions */
353
+	struct devlink_region *regions[_MV88E6XXX_REGION_MAX];
288354 };
289355 
290356 struct mv88e6xxx_bus_ops {
....@@ -351,15 +417,6 @@
351417 	 */
352418 	int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link);
353419 
354
-#define DUPLEX_UNFORCED		-2
355
-
356
-	/* Port's MAC duplex mode
357
-	 *
358
-	 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex,
359
-	 * or DUPLEX_UNFORCED for normal duplex detection.
360
-	 */
361
-	int (*port_set_duplex)(struct mv88e6xxx_chip *chip, int port, int dup);
362
-
363420 #define PAUSE_ON		1
364421 #define PAUSE_OFF		0
365422 
....@@ -369,15 +426,27 @@
369426 
370427 #define SPEED_MAX		INT_MAX
371428 #define SPEED_UNFORCED		-2
429
+#define DUPLEX_UNFORCED		-2
372430 
373
-	/* Port's MAC speed (in Mbps)
431
+	/* Port's MAC speed (in Mbps) and MAC duplex mode
374432 	 *
375433 	 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid.
376434 	 * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value.
435
+	 *
436
+	 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex,
437
+	 * or DUPLEX_UNFORCED for normal duplex detection.
377438 	 */
378
-	int (*port_set_speed)(struct mv88e6xxx_chip *chip, int port, int speed);
439
+	int (*port_set_speed_duplex)(struct mv88e6xxx_chip *chip, int port,
440
+				     int speed, int duplex);
441
+
442
+	/* What interface mode should be used for maximum speed? */
443
+	phy_interface_t (*port_max_speed_mode)(int port);
379444 
380445 	int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port);
446
+
447
+	int (*port_set_policy)(struct mv88e6xxx_chip *chip, int port,
448
+			       enum mv88e6xxx_policy_mapping mapping,
449
+			       enum mv88e6xxx_policy_action action);
381450 
382451 	int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port,
383452 				   enum mv88e6xxx_frame_mode mode);
....@@ -393,6 +462,7 @@
393462 				u8 out);
394463 	int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port);
395464 	int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port);
465
+	int (*port_setup_message_port)(struct mv88e6xxx_chip *chip, int port);
396466 
397467 	/* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc.
398468 	 * Some chips allow this to be configured on specific ports.
....@@ -406,9 +476,6 @@
406476 	 */
407477 	int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port,
408478 				      int upstream_port);
409
-	/* Return the port link state, as required by phylink */
410
-	int (*port_link_state)(struct mv88e6xxx_chip *chip, int port,
411
-			       struct phylink_link_state *state);
412479 
413480 	/* Snapshot the statistics for a port. The statistics can then
414481 	 * be read back a leisure but still with a consistent view.
....@@ -426,7 +493,9 @@
426493 	int (*stats_get_stats)(struct mv88e6xxx_chip *chip,  int port,
427494 			       uint64_t *data);
428495 	int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port);
429
-	int (*set_egress_port)(struct mv88e6xxx_chip *chip, int port);
496
+	int (*set_egress_port)(struct mv88e6xxx_chip *chip,
497
+			       enum mv88e6xxx_egress_direction direction,
498
+			       int port);
430499 
431500 #define MV88E6XXX_CASCADE_PORT_NONE		0xe
432501 #define MV88E6XXX_CASCADE_PORT_MULTIPLE		0xf
....@@ -438,11 +507,30 @@
438507 	int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip);
439508 
440509 	/* Power on/off a SERDES interface */
441
-	int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, bool on);
510
+	int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, u8 lane,
511
+			    bool up);
512
+
513
+	/* SERDES lane mapping */
514
+	u8 (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port);
515
+
516
+	int (*serdes_pcs_get_state)(struct mv88e6xxx_chip *chip, int port,
517
+				    u8 lane, struct phylink_link_state *state);
518
+	int (*serdes_pcs_config)(struct mv88e6xxx_chip *chip, int port,
519
+				 u8 lane, unsigned int mode,
520
+				 phy_interface_t interface,
521
+				 const unsigned long *advertise);
522
+	int (*serdes_pcs_an_restart)(struct mv88e6xxx_chip *chip, int port,
523
+				     u8 lane);
524
+	int (*serdes_pcs_link_up)(struct mv88e6xxx_chip *chip, int port,
525
+				  u8 lane, int speed, int duplex);
442526 
443527 	/* SERDES interrupt handling */
444
-	int (*serdes_irq_setup)(struct mv88e6xxx_chip *chip, int port);
445
-	void (*serdes_irq_free)(struct mv88e6xxx_chip *chip, int port);
528
+	unsigned int (*serdes_irq_mapping)(struct mv88e6xxx_chip *chip,
529
+					   int port);
530
+	int (*serdes_irq_enable)(struct mv88e6xxx_chip *chip, int port, u8 lane,
531
+				 bool enable);
532
+	irqreturn_t (*serdes_irq_status)(struct mv88e6xxx_chip *chip, int port,
533
+					 u8 lane);
446534 
447535 	/* Statistics from the SERDES interface */
448536 	int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port);
....@@ -450,6 +538,15 @@
450538 				  uint8_t *data);
451539 	int (*serdes_get_stats)(struct mv88e6xxx_chip *chip,  int port,
452540 				uint64_t *data);
541
+
542
+	/* SERDES registers for ethtool */
543
+	int (*serdes_get_regs_len)(struct mv88e6xxx_chip *chip,  int port);
544
+	void (*serdes_get_regs)(struct mv88e6xxx_chip *chip, int port,
545
+				void *_p);
546
+
547
+	/* Address Translation Unit operations */
548
+	int (*atu_get_hash)(struct mv88e6xxx_chip *chip, u8 *hash);
549
+	int (*atu_set_hash)(struct mv88e6xxx_chip *chip, u8 hash);
453550 
454551 	/* VLAN Translation Unit operations */
455552 	int (*vtu_getnext)(struct mv88e6xxx_chip *chip,
....@@ -473,6 +570,9 @@
473570 	void (*phylink_validate)(struct mv88e6xxx_chip *chip, int port,
474571 				 unsigned long *mask,
475572 				 struct phylink_link_state *state);
573
+
574
+	/* Max Frame Size */
575
+	int (*set_max_frame_size)(struct mv88e6xxx_chip *chip, int mtu);
476576 };
477577 
478578 struct mv88e6xxx_irq_ops {
....@@ -536,6 +636,10 @@
536636 	int arr1_sts_reg;
537637 	int dep_sts_reg;
538638 	u32 rx_filters;
639
+	u32 cc_shift;
640
+	u32 cc_mult;
641
+	u32 cc_mult_num;
642
+	u32 cc_mult_dem;
539643 };
540644 
541645 #define STATS_TYPE_PORT		BIT(0)
....@@ -559,6 +663,11 @@
559663 	return chip->info->num_databases;
560664 }
561665 
666
+static inline unsigned int mv88e6xxx_num_macs(struct  mv88e6xxx_chip *chip)
667
+{
668
+	return chip->info->num_macs;
669
+}
670
+
562671 static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip)
563672 {
564673 	return chip->info->num_ports;
....@@ -566,7 +675,7 @@
566675 
567676 static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip)
568677 {
569
-	return GENMASK(mv88e6xxx_num_ports(chip) - 1, 0);
678
+	return GENMASK((s32)mv88e6xxx_num_ports(chip) - 1, 0);
570679 }
571680 
572681 static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip)
....@@ -574,11 +683,29 @@
574683 	return chip->info->num_gpio;
575684 }
576685 
686
+static inline bool mv88e6xxx_is_invalid_port(struct mv88e6xxx_chip *chip, int port)
687
+{
688
+	return (chip->info->invalid_port_mask & BIT(port)) != 0;
689
+}
690
+
577691 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
578692 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
579
-int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg,
580
-		     u16 update);
581
-int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask);
693
+int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
694
+			u16 mask, u16 val);
695
+int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
696
+		       int bit, int val);
582697 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip);
583698 
699
+static inline void mv88e6xxx_reg_lock(struct mv88e6xxx_chip *chip)
700
+{
701
+	mutex_lock(&chip->reg_lock);
702
+}
703
+
704
+static inline void mv88e6xxx_reg_unlock(struct mv88e6xxx_chip *chip)
705
+{
706
+	mutex_unlock(&chip->reg_lock);
707
+}
708
+
709
+int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *bitmap);
710
+
584711 #endif /* _MV88E6XXX_CHIP_H */