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2023-12-06 08f87f769b595151be1afeff53e144f543faa614 
 kernel/drivers/gpu/drm/sun4i/sun8i_mixer.c
....@@ -1,29 +1,25 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
34  *
45  * Based on sun4i_backend.c, which is:
56  *   Copyright (C) 2015 Free Electrons
67  *   Copyright (C) 2015 NextThing Co
7
- *
8
- * This program is free software; you can redistribute it and/or
9
- * modify it under the terms of the GNU General Public License as
10
- * published by the Free Software Foundation; either version 2 of
11
- * the License, or (at your option) any later version.
128  */
13
-
14
-#include <drm/drmP.h>
15
-#include <drm/drm_atomic_helper.h>
16
-#include <drm/drm_crtc.h>
17
-#include <drm/drm_crtc_helper.h>
18
-#include <drm/drm_fb_cma_helper.h>
19
-#include <drm/drm_gem_cma_helper.h>
20
-#include <drm/drm_plane_helper.h>
219 
2210 #include <linux/component.h>
2311 #include <linux/dma-mapping.h>
12
+#include <linux/module.h>
2413 #include <linux/of_device.h>
2514 #include <linux/of_graph.h>
2615 #include <linux/reset.h>
16
+
17
+#include <drm/drm_atomic_helper.h>
18
+#include <drm/drm_crtc.h>
19
+#include <drm/drm_fb_cma_helper.h>
20
+#include <drm/drm_gem_cma_helper.h>
21
+#include <drm/drm_plane_helper.h>
22
+#include <drm/drm_probe_helper.h>
2723 
2824 #include "sun4i_drv.h"
2925 #include "sun8i_mixer.h"
....@@ -31,278 +27,225 @@
3127 #include "sun8i_vi_layer.h"
3228 #include "sunxi_engine.h"
3329 
30
+struct de2_fmt_info {
31
+	u32	drm_fmt;
32
+	u32	de2_fmt;
33
+};
34
+
3435 static const struct de2_fmt_info de2_formats[] = {
3536 	{
3637 		.drm_fmt = DRM_FORMAT_ARGB8888,
3738 		.de2_fmt = SUN8I_MIXER_FBFMT_ARGB8888,
38
-		.rgb = true,
39
-		.csc = SUN8I_CSC_MODE_OFF,
4039 	},
4140 	{
4241 		.drm_fmt = DRM_FORMAT_ABGR8888,
4342 		.de2_fmt = SUN8I_MIXER_FBFMT_ABGR8888,
44
-		.rgb = true,
45
-		.csc = SUN8I_CSC_MODE_OFF,
4643 	},
4744 	{
4845 		.drm_fmt = DRM_FORMAT_RGBA8888,
4946 		.de2_fmt = SUN8I_MIXER_FBFMT_RGBA8888,
50
-		.rgb = true,
51
-		.csc = SUN8I_CSC_MODE_OFF,
5247 	},
5348 	{
5449 		.drm_fmt = DRM_FORMAT_BGRA8888,
5550 		.de2_fmt = SUN8I_MIXER_FBFMT_BGRA8888,
56
-		.rgb = true,
57
-		.csc = SUN8I_CSC_MODE_OFF,
5851 	},
5952 	{
6053 		.drm_fmt = DRM_FORMAT_XRGB8888,
6154 		.de2_fmt = SUN8I_MIXER_FBFMT_XRGB8888,
62
-		.rgb = true,
63
-		.csc = SUN8I_CSC_MODE_OFF,
6455 	},
6556 	{
6657 		.drm_fmt = DRM_FORMAT_XBGR8888,
6758 		.de2_fmt = SUN8I_MIXER_FBFMT_XBGR8888,
68
-		.rgb = true,
69
-		.csc = SUN8I_CSC_MODE_OFF,
7059 	},
7160 	{
7261 		.drm_fmt = DRM_FORMAT_RGBX8888,
7362 		.de2_fmt = SUN8I_MIXER_FBFMT_RGBX8888,
74
-		.rgb = true,
75
-		.csc = SUN8I_CSC_MODE_OFF,
7663 	},
7764 	{
7865 		.drm_fmt = DRM_FORMAT_BGRX8888,
7966 		.de2_fmt = SUN8I_MIXER_FBFMT_BGRX8888,
80
-		.rgb = true,
81
-		.csc = SUN8I_CSC_MODE_OFF,
8267 	},
8368 	{
8469 		.drm_fmt = DRM_FORMAT_RGB888,
8570 		.de2_fmt = SUN8I_MIXER_FBFMT_RGB888,
86
-		.rgb = true,
87
-		.csc = SUN8I_CSC_MODE_OFF,
8871 	},
8972 	{
9073 		.drm_fmt = DRM_FORMAT_BGR888,
9174 		.de2_fmt = SUN8I_MIXER_FBFMT_BGR888,
92
-		.rgb = true,
93
-		.csc = SUN8I_CSC_MODE_OFF,
9475 	},
9576 	{
9677 		.drm_fmt = DRM_FORMAT_RGB565,
9778 		.de2_fmt = SUN8I_MIXER_FBFMT_RGB565,
98
-		.rgb = true,
99
-		.csc = SUN8I_CSC_MODE_OFF,
10079 	},
10180 	{
10281 		.drm_fmt = DRM_FORMAT_BGR565,
10382 		.de2_fmt = SUN8I_MIXER_FBFMT_BGR565,
104
-		.rgb = true,
105
-		.csc = SUN8I_CSC_MODE_OFF,
10683 	},
10784 	{
10885 		.drm_fmt = DRM_FORMAT_ARGB4444,
10986 		.de2_fmt = SUN8I_MIXER_FBFMT_ARGB4444,
110
-		.rgb = true,
111
-		.csc = SUN8I_CSC_MODE_OFF,
11287 	},
11388 	{
11489 		/* for DE2 VI layer which ignores alpha */
11590 		.drm_fmt = DRM_FORMAT_XRGB4444,
11691 		.de2_fmt = SUN8I_MIXER_FBFMT_ARGB4444,
117
-		.rgb = true,
118
-		.csc = SUN8I_CSC_MODE_OFF,
11992 	},
12093 	{
12194 		.drm_fmt = DRM_FORMAT_ABGR4444,
12295 		.de2_fmt = SUN8I_MIXER_FBFMT_ABGR4444,
123
-		.rgb = true,
124
-		.csc = SUN8I_CSC_MODE_OFF,
12596 	},
12697 	{
12798 		/* for DE2 VI layer which ignores alpha */
12899 		.drm_fmt = DRM_FORMAT_XBGR4444,
129100 		.de2_fmt = SUN8I_MIXER_FBFMT_ABGR4444,
130
-		.rgb = true,
131
-		.csc = SUN8I_CSC_MODE_OFF,
132101 	},
133102 	{
134103 		.drm_fmt = DRM_FORMAT_RGBA4444,
135104 		.de2_fmt = SUN8I_MIXER_FBFMT_RGBA4444,
136
-		.rgb = true,
137
-		.csc = SUN8I_CSC_MODE_OFF,
138105 	},
139106 	{
140107 		/* for DE2 VI layer which ignores alpha */
141108 		.drm_fmt = DRM_FORMAT_RGBX4444,
142109 		.de2_fmt = SUN8I_MIXER_FBFMT_RGBA4444,
143
-		.rgb = true,
144
-		.csc = SUN8I_CSC_MODE_OFF,
145110 	},
146111 	{
147112 		.drm_fmt = DRM_FORMAT_BGRA4444,
148113 		.de2_fmt = SUN8I_MIXER_FBFMT_BGRA4444,
149
-		.rgb = true,
150
-		.csc = SUN8I_CSC_MODE_OFF,
151114 	},
152115 	{
153116 		/* for DE2 VI layer which ignores alpha */
154117 		.drm_fmt = DRM_FORMAT_BGRX4444,
155118 		.de2_fmt = SUN8I_MIXER_FBFMT_BGRA4444,
156
-		.rgb = true,
157
-		.csc = SUN8I_CSC_MODE_OFF,
158119 	},
159120 	{
160121 		.drm_fmt = DRM_FORMAT_ARGB1555,
161122 		.de2_fmt = SUN8I_MIXER_FBFMT_ARGB1555,
162
-		.rgb = true,
163
-		.csc = SUN8I_CSC_MODE_OFF,
164123 	},
165124 	{
166125 		/* for DE2 VI layer which ignores alpha */
167126 		.drm_fmt = DRM_FORMAT_XRGB1555,
168127 		.de2_fmt = SUN8I_MIXER_FBFMT_ARGB1555,
169
-		.rgb = true,
170
-		.csc = SUN8I_CSC_MODE_OFF,
171128 	},
172129 	{
173130 		.drm_fmt = DRM_FORMAT_ABGR1555,
174131 		.de2_fmt = SUN8I_MIXER_FBFMT_ABGR1555,
175
-		.rgb = true,
176
-		.csc = SUN8I_CSC_MODE_OFF,
177132 	},
178133 	{
179134 		/* for DE2 VI layer which ignores alpha */
180135 		.drm_fmt = DRM_FORMAT_XBGR1555,
181136 		.de2_fmt = SUN8I_MIXER_FBFMT_ABGR1555,
182
-		.rgb = true,
183
-		.csc = SUN8I_CSC_MODE_OFF,
184137 	},
185138 	{
186139 		.drm_fmt = DRM_FORMAT_RGBA5551,
187140 		.de2_fmt = SUN8I_MIXER_FBFMT_RGBA5551,
188
-		.rgb = true,
189
-		.csc = SUN8I_CSC_MODE_OFF,
190141 	},
191142 	{
192143 		/* for DE2 VI layer which ignores alpha */
193144 		.drm_fmt = DRM_FORMAT_RGBX5551,
194145 		.de2_fmt = SUN8I_MIXER_FBFMT_RGBA5551,
195
-		.rgb = true,
196
-		.csc = SUN8I_CSC_MODE_OFF,
197146 	},
198147 	{
199148 		.drm_fmt = DRM_FORMAT_BGRA5551,
200149 		.de2_fmt = SUN8I_MIXER_FBFMT_BGRA5551,
201
-		.rgb = true,
202
-		.csc = SUN8I_CSC_MODE_OFF,
203150 	},
204151 	{
205152 		/* for DE2 VI layer which ignores alpha */
206153 		.drm_fmt = DRM_FORMAT_BGRX5551,
207154 		.de2_fmt = SUN8I_MIXER_FBFMT_BGRA5551,
208
-		.rgb = true,
209
-		.csc = SUN8I_CSC_MODE_OFF,
155
+	},
156
+	{
157
+		.drm_fmt = DRM_FORMAT_ARGB2101010,
158
+		.de2_fmt = SUN8I_MIXER_FBFMT_ARGB2101010,
159
+	},
160
+	{
161
+		.drm_fmt = DRM_FORMAT_ABGR2101010,
162
+		.de2_fmt = SUN8I_MIXER_FBFMT_ABGR2101010,
163
+	},
164
+	{
165
+		.drm_fmt = DRM_FORMAT_RGBA1010102,
166
+		.de2_fmt = SUN8I_MIXER_FBFMT_RGBA1010102,
167
+	},
168
+	{
169
+		.drm_fmt = DRM_FORMAT_BGRA1010102,
170
+		.de2_fmt = SUN8I_MIXER_FBFMT_BGRA1010102,
210171 	},
211172 	{
212173 		.drm_fmt = DRM_FORMAT_UYVY,
213174 		.de2_fmt = SUN8I_MIXER_FBFMT_UYVY,
214
-		.rgb = false,
215
-		.csc = SUN8I_CSC_MODE_YUV2RGB,
216175 	},
217176 	{
218177 		.drm_fmt = DRM_FORMAT_VYUY,
219178 		.de2_fmt = SUN8I_MIXER_FBFMT_VYUY,
220
-		.rgb = false,
221
-		.csc = SUN8I_CSC_MODE_YUV2RGB,
222179 	},
223180 	{
224181 		.drm_fmt = DRM_FORMAT_YUYV,
225182 		.de2_fmt = SUN8I_MIXER_FBFMT_YUYV,
226
-		.rgb = false,
227
-		.csc = SUN8I_CSC_MODE_YUV2RGB,
228183 	},
229184 	{
230185 		.drm_fmt = DRM_FORMAT_YVYU,
231186 		.de2_fmt = SUN8I_MIXER_FBFMT_YVYU,
232
-		.rgb = false,
233
-		.csc = SUN8I_CSC_MODE_YUV2RGB,
234187 	},
235188 	{
236189 		.drm_fmt = DRM_FORMAT_NV16,
237190 		.de2_fmt = SUN8I_MIXER_FBFMT_NV16,
238
-		.rgb = false,
239
-		.csc = SUN8I_CSC_MODE_YUV2RGB,
240191 	},
241192 	{
242193 		.drm_fmt = DRM_FORMAT_NV61,
243194 		.de2_fmt = SUN8I_MIXER_FBFMT_NV61,
244
-		.rgb = false,
245
-		.csc = SUN8I_CSC_MODE_YUV2RGB,
246195 	},
247196 	{
248197 		.drm_fmt = DRM_FORMAT_NV12,
249198 		.de2_fmt = SUN8I_MIXER_FBFMT_NV12,
250
-		.rgb = false,
251
-		.csc = SUN8I_CSC_MODE_YUV2RGB,
252199 	},
253200 	{
254201 		.drm_fmt = DRM_FORMAT_NV21,
255202 		.de2_fmt = SUN8I_MIXER_FBFMT_NV21,
256
-		.rgb = false,
257
-		.csc = SUN8I_CSC_MODE_YUV2RGB,
258203 	},
259204 	{
260205 		.drm_fmt = DRM_FORMAT_YUV422,
261206 		.de2_fmt = SUN8I_MIXER_FBFMT_YUV422,
262
-		.rgb = false,
263
-		.csc = SUN8I_CSC_MODE_YUV2RGB,
264207 	},
265208 	{
266209 		.drm_fmt = DRM_FORMAT_YUV420,
267210 		.de2_fmt = SUN8I_MIXER_FBFMT_YUV420,
268
-		.rgb = false,
269
-		.csc = SUN8I_CSC_MODE_YUV2RGB,
270211 	},
271212 	{
272213 		.drm_fmt = DRM_FORMAT_YUV411,
273214 		.de2_fmt = SUN8I_MIXER_FBFMT_YUV411,
274
-		.rgb = false,
275
-		.csc = SUN8I_CSC_MODE_YUV2RGB,
276215 	},
277216 	{
278217 		.drm_fmt = DRM_FORMAT_YVU422,
279218 		.de2_fmt = SUN8I_MIXER_FBFMT_YUV422,
280
-		.rgb = false,
281
-		.csc = SUN8I_CSC_MODE_YVU2RGB,
282219 	},
283220 	{
284221 		.drm_fmt = DRM_FORMAT_YVU420,
285222 		.de2_fmt = SUN8I_MIXER_FBFMT_YUV420,
286
-		.rgb = false,
287
-		.csc = SUN8I_CSC_MODE_YVU2RGB,
288223 	},
289224 	{
290225 		.drm_fmt = DRM_FORMAT_YVU411,
291226 		.de2_fmt = SUN8I_MIXER_FBFMT_YUV411,
292
-		.rgb = false,
293
-		.csc = SUN8I_CSC_MODE_YVU2RGB,
227
+	},
228
+	{
229
+		.drm_fmt = DRM_FORMAT_P010,
230
+		.de2_fmt = SUN8I_MIXER_FBFMT_P010_YUV,
231
+	},
232
+	{
233
+		.drm_fmt = DRM_FORMAT_P210,
234
+		.de2_fmt = SUN8I_MIXER_FBFMT_P210_YUV,
294235 	},
295236 };
296237 
297
-const struct de2_fmt_info *sun8i_mixer_format_info(u32 format)
238
+int sun8i_mixer_drm_format_to_hw(u32 format, u32 *hw_format)
298239 {
299240 	unsigned int i;
300241 
301242 	for (i = 0; i < ARRAY_SIZE(de2_formats); ++i)
302
-		if (de2_formats[i].drm_fmt == format)
303
-			return &de2_formats[i];
243
+		if (de2_formats[i].drm_fmt == format) {
244
+			*hw_format = de2_formats[i].de2_fmt;
245
+			return 0;
246
+		}
304247 
305
-	return NULL;
248
+	return -EINVAL;
306249 }
307250 
308251 static void sun8i_mixer_commit(struct sunxi_engine *engine)
....@@ -334,10 +277,10 @@
334277 			dev_err(drm->dev,
335278 				"Couldn't initialize overlay plane\n");
336279 			return ERR_CAST(layer);
337
-		};
280
+		}
338281 
339282 		planes[i] = &layer->plane;
340
-	};
283
+	}
341284 
342285 	for (i = 0; i < mixer->cfg->ui_num; i++) {
343286 		struct sun8i_ui_layer *layer;
....@@ -347,10 +290,10 @@
347290 			dev_err(drm->dev, "Couldn't initialize %s plane\n",
348291 				i ? "overlay" : "primary");
349292 			return ERR_CAST(layer);
350
-		};
293
+		}
351294 
352295 		planes[mixer->cfg->vi_num + i] = &layer->plane;
353
-	};
296
+	}
354297 
355298 	return planes;
356299 }
....@@ -360,7 +303,7 @@
360303 	.layers_init	= sun8i_layers_init,
361304 };
362305 
363
-static struct regmap_config sun8i_mixer_regmap_config = {
306
+static const struct regmap_config sun8i_mixer_regmap_config = {
364307 	.reg_bits	= 32,
365308 	.val_bits	= 32,
366309 	.reg_stride	= 4,
....@@ -369,38 +312,22 @@
369312 
370313 static int sun8i_mixer_of_get_id(struct device_node *node)
371314 {
372
-	struct device_node *port, *ep;
373
-	int ret = -EINVAL;
315
+	struct device_node *ep, *remote;
316
+	struct of_endpoint of_ep;
374317 
375
-	/* output is port 1 */
376
-	port = of_graph_get_port_by_id(node, 1);
377
-	if (!port)
318
+	/* Output port is 1, and we want the first endpoint. */
319
+	ep = of_graph_get_endpoint_by_regs(node, 1, -1);
320
+	if (!ep)
378321 		return -EINVAL;
379322 
380
-	/* try to find downstream endpoint */
381
-	for_each_available_child_of_node(port, ep) {
382
-		struct device_node *remote;
383
-		u32 reg;
323
+	remote = of_graph_get_remote_endpoint(ep);
324
+	of_node_put(ep);
325
+	if (!remote)
326
+		return -EINVAL;
384327 
385
-		remote = of_graph_get_remote_endpoint(ep);
386
-		if (!remote)
387
-			continue;
388
-
389
-		ret = of_property_read_u32(remote, "reg", &reg);
390
-		if (!ret) {
391
-			of_node_put(remote);
392
-			of_node_put(ep);
393
-			of_node_put(port);
394
-
395
-			return reg;
396
-		}
397
-
398
-		of_node_put(remote);
399
-	}
400
-
401
-	of_node_put(port);
402
-
403
-	return ret;
328
+	of_graph_parse_endpoint(remote, &of_ep);
329
+	of_node_put(remote);
330
+	return of_ep.id;
404331 }
405332 
406333 static int sun8i_mixer_bind(struct device *dev, struct device *master,
....@@ -412,6 +339,7 @@
412339 	struct sun8i_mixer *mixer;
413340 	struct resource *res;
414341 	void __iomem *regs;
342
+	unsigned int base;
415343 	int plane_cnt;
416344 	int i, ret;
417345 
....@@ -434,6 +362,19 @@
434362 	dev_set_drvdata(dev, mixer);
435363 	mixer->engine.ops = &sun8i_engine_ops;
436364 	mixer->engine.node = dev->of_node;
365
+
366
+	if (of_find_property(dev->of_node, "iommus", NULL)) {
367
+		/*
368
+		 * This assume we have the same DMA constraints for
369
+		 * all our the mixers in our pipeline. This sounds
370
+		 * bad, but it has always been the case for us, and
371
+		 * DRM doesn't do per-device allocation either, so we
372
+		 * would need to fix DRM first...
373
+		 */
374
+		ret = of_dma_configure(drm->dev, dev->of_node, true);
375
+		if (ret)
376
+			return ret;
377
+	}
437378 
438379 	/*
439380 	 * While this function can fail, we shouldn't do anything
....@@ -500,33 +441,60 @@
500441 
501442 	list_add_tail(&mixer->engine.list, &drv->engine_list);
502443 
503
-	/* Reset the registers */
504
-	for (i = 0x0; i < 0x20000; i += 4)
505
-		regmap_write(mixer->engine.regs, i, 0);
444
+	base = sun8i_blender_base(mixer);
445
+
446
+	/* Reset registers and disable unused sub-engines */
447
+	if (mixer->cfg->is_de3) {
448
+		for (i = 0; i < DE3_MIXER_UNIT_SIZE; i += 4)
449
+			regmap_write(mixer->engine.regs, i, 0);
450
+
451
+		regmap_write(mixer->engine.regs, SUN50I_MIXER_FCE_EN, 0);
452
+		regmap_write(mixer->engine.regs, SUN50I_MIXER_PEAK_EN, 0);
453
+		regmap_write(mixer->engine.regs, SUN50I_MIXER_LCTI_EN, 0);
454
+		regmap_write(mixer->engine.regs, SUN50I_MIXER_BLS_EN, 0);
455
+		regmap_write(mixer->engine.regs, SUN50I_MIXER_FCC_EN, 0);
456
+		regmap_write(mixer->engine.regs, SUN50I_MIXER_DNS_EN, 0);
457
+		regmap_write(mixer->engine.regs, SUN50I_MIXER_DRC_EN, 0);
458
+		regmap_write(mixer->engine.regs, SUN50I_MIXER_FMT_EN, 0);
459
+		regmap_write(mixer->engine.regs, SUN50I_MIXER_CDC0_EN, 0);
460
+		regmap_write(mixer->engine.regs, SUN50I_MIXER_CDC1_EN, 0);
461
+	} else {
462
+		for (i = 0; i < DE2_MIXER_UNIT_SIZE; i += 4)
463
+			regmap_write(mixer->engine.regs, i, 0);
464
+
465
+		regmap_write(mixer->engine.regs, SUN8I_MIXER_FCE_EN, 0);
466
+		regmap_write(mixer->engine.regs, SUN8I_MIXER_BWS_EN, 0);
467
+		regmap_write(mixer->engine.regs, SUN8I_MIXER_LTI_EN, 0);
468
+		regmap_write(mixer->engine.regs, SUN8I_MIXER_PEAK_EN, 0);
469
+		regmap_write(mixer->engine.regs, SUN8I_MIXER_ASE_EN, 0);
470
+		regmap_write(mixer->engine.regs, SUN8I_MIXER_FCC_EN, 0);
471
+		regmap_write(mixer->engine.regs, SUN8I_MIXER_DCSC_EN, 0);
472
+	}
506473 
507474 	/* Enable the mixer */
508475 	regmap_write(mixer->engine.regs, SUN8I_MIXER_GLOBAL_CTL,
509476 		     SUN8I_MIXER_GLOBAL_CTL_RT_EN);
510477 
511478 	/* Set background color to black */
512
-	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_BKCOLOR,
479
+	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_BKCOLOR(base),
513480 		     SUN8I_MIXER_BLEND_COLOR_BLACK);
514481 
515482 	/*
516483 	 * Set fill color of bottom plane to black. Generally not needed
517484 	 * except when VI plane is at bottom (zpos = 0) and enabled.
518485 	 */
519
-	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL,
486
+	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
520487 		     SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0));
521
-	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_ATTR_FCOLOR(0),
488
+	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, 0),
522489 		     SUN8I_MIXER_BLEND_COLOR_BLACK);
523490 
524491 	plane_cnt = mixer->cfg->vi_num + mixer->cfg->ui_num;
525492 	for (i = 0; i < plane_cnt; i++)
526
-		regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_MODE(i),
493
+		regmap_write(mixer->engine.regs,
494
+			     SUN8I_MIXER_BLEND_MODE(base, i),
527495 			     SUN8I_MIXER_BLEND_MODE_DEF);
528496 
529
-	regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL,
497
+	regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
530498 			   SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK, 0);
531499 
532500 	return 0;
....@@ -570,6 +538,7 @@
570538 static const struct sun8i_mixer_cfg sun8i_a83t_mixer0_cfg = {
571539 	.ccsc		= 0,
572540 	.scaler_mask	= 0xf,
541
+	.scanline_yuv	= 2048,
573542 	.ui_num		= 3,
574543 	.vi_num		= 1,
575544 };
....@@ -577,6 +546,7 @@
577546 static const struct sun8i_mixer_cfg sun8i_a83t_mixer1_cfg = {
578547 	.ccsc		= 1,
579548 	.scaler_mask	= 0x3,
549
+	.scanline_yuv	= 2048,
580550 	.ui_num		= 1,
581551 	.vi_num		= 1,
582552 };
....@@ -585,7 +555,26 @@
585555 	.ccsc		= 0,
586556 	.mod_rate	= 432000000,
587557 	.scaler_mask	= 0xf,
558
+	.scanline_yuv	= 2048,
588559 	.ui_num		= 3,
560
+	.vi_num		= 1,
561
+};
562
+
563
+static const struct sun8i_mixer_cfg sun8i_r40_mixer0_cfg = {
564
+	.ccsc		= 0,
565
+	.mod_rate	= 297000000,
566
+	.scaler_mask	= 0xf,
567
+	.scanline_yuv	= 2048,
568
+	.ui_num		= 3,
569
+	.vi_num		= 1,
570
+};
571
+
572
+static const struct sun8i_mixer_cfg sun8i_r40_mixer1_cfg = {
573
+	.ccsc		= 1,
574
+	.mod_rate	= 297000000,
575
+	.scaler_mask	= 0x3,
576
+	.scanline_yuv	= 2048,
577
+	.ui_num		= 1,
589578 	.vi_num		= 1,
590579 };
591580 
....@@ -593,8 +582,37 @@
593582 	.vi_num = 2,
594583 	.ui_num = 1,
595584 	.scaler_mask = 0x3,
585
+	.scanline_yuv = 2048,
596586 	.ccsc = 0,
597587 	.mod_rate = 150000000,
588
+};
589
+
590
+static const struct sun8i_mixer_cfg sun50i_a64_mixer0_cfg = {
591
+	.ccsc		= 0,
592
+	.mod_rate	= 297000000,
593
+	.scaler_mask	= 0xf,
594
+	.scanline_yuv	= 4096,
595
+	.ui_num		= 3,
596
+	.vi_num		= 1,
597
+};
598
+
599
+static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg = {
600
+	.ccsc		= 1,
601
+	.mod_rate	= 297000000,
602
+	.scaler_mask	= 0x3,
603
+	.scanline_yuv	= 2048,
604
+	.ui_num		= 1,
605
+	.vi_num		= 1,
606
+};
607
+
608
+static const struct sun8i_mixer_cfg sun50i_h6_mixer0_cfg = {
609
+	.ccsc		= 0,
610
+	.is_de3		= true,
611
+	.mod_rate	= 600000000,
612
+	.scaler_mask	= 0xf,
613
+	.scanline_yuv	= 4096,
614
+	.ui_num		= 3,
615
+	.vi_num		= 1,
598616 };
599617 
600618 static const struct of_device_id sun8i_mixer_of_table[] = {
....@@ -611,9 +629,29 @@
611629 		.data = &sun8i_h3_mixer0_cfg,
612630 	},
613631 	{
632
+		.compatible = "allwinner,sun8i-r40-de2-mixer-0",
633
+		.data = &sun8i_r40_mixer0_cfg,
634
+	},
635
+	{
636
+		.compatible = "allwinner,sun8i-r40-de2-mixer-1",
637
+		.data = &sun8i_r40_mixer1_cfg,
638
+	},
639
+	{
614640 		.compatible = "allwinner,sun8i-v3s-de2-mixer",
615641 		.data = &sun8i_v3s_mixer_cfg,
616642 	},
643
+	{
644
+		.compatible = "allwinner,sun50i-a64-de2-mixer-0",
645
+		.data = &sun50i_a64_mixer0_cfg,
646
+	},
647
+	{
648
+		.compatible = "allwinner,sun50i-a64-de2-mixer-1",
649
+		.data = &sun50i_a64_mixer1_cfg,
650
+	},
651
+	{
652
+		.compatible = "allwinner,sun50i-h6-de3-mixer-0",
653
+		.data = &sun50i_h6_mixer0_cfg,
654
+	},
617655 	{ }
618656 };
619657 MODULE_DEVICE_TABLE(of, sun8i_mixer_of_table);