~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,47 +1,60 @@
	1	+/* SPDX-License-Identifier: GPL-2.0-only */
1	2	/*
2	3	* Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3	4	* Author:Mark Yao <mark.yao@rock-chips.com>
4		- *
5		- * This software is licensed under the terms of the GNU General Public
6		- * License version 2, as published by the Free Software Foundation, and
7		- * may be copied, distributed, and modified under those terms.
8		- *
9		- * This program is distributed in the hope that it will be useful,
10		- * but WITHOUT ANY WARRANTY; without even the implied warranty of
11		- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12		- * GNU General Public License for more details.
13	5	*/
14	6
15	7	#ifndef _ROCKCHIP_DRM_VOP_H
16	8	#define _ROCKCHIP_DRM_VOP_H
	9	+
	10	+#include <drm/drm_plane.h>
	11	+#include <drm/drm_modes.h>
	12	+
17	13	#include "rockchip_drm_drv.h"
18	14
19	15	/*
20	16	* major: IP major version, used for IP structure
21	17	* minor: big feature change under same structure
	18	+ * build: RTL current SVN number
22	19	*/
23	20	#define VOP_VERSION(major, minor) ((major) << 8 \| (minor))
24	21	#define VOP_MAJOR(version) ((version) >> 8)
25	22	#define VOP_MINOR(version) ((version) & 0xff)
26	23
27		-#define VOP_VERSION_RK3568 VOP_VERSION(0x40, 0x15)
28		-#define VOP_VERSION_RK3588 VOP_VERSION(0x40, 0x17)
	24	+#define VOP2_VERSION(major, minor, build) ((major) << 24 \| (minor) << 16 \| (build))
	25	+#define VOP2_MAJOR(version) (((version) >> 24) & 0xff)
	26	+#define VOP2_MINOR(version) (((version) >> 16) & 0xff)
	27	+#define VOP2_BUILD(version) ((version) & 0xffff)
	28	+
	29	+#define VOP_VERSION_RK3528 VOP2_VERSION(0x50, 0x17, 0x1263)
	30	+#define VOP_VERSION_RK3562 VOP2_VERSION(0x50, 0x17, 0x4350)
	31	+#define VOP_VERSION_RK3568 VOP2_VERSION(0x40, 0x15, 0x8023)
	32	+#define VOP_VERSION_RK3588 VOP2_VERSION(0x40, 0x17, 0x6786)
29	33
30	34	#define ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE BIT(0)
31	35	#define ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE BIT(1)
32	36	#define ROCKCHIP_OUTPUT_DATA_SWAP BIT(2)
	37	+/* MIPI DSI DataStream(cmd) mode on rk3588 */
	38	+#define ROCKCHIP_OUTPUT_MIPI_DS_MODE BIT(3)
33	39
34	40	#define AFBDC_FMT_RGB565 0x0
35	41	#define AFBDC_FMT_U8U8U8U8 0x5
36	42	#define AFBDC_FMT_U8U8U8 0x4
37		-#define VOP_FEATURE_OUTPUT_10BIT BIT(0)
38		-#define VOP_FEATURE_AFBDC BIT(1)
	43	+
	44	+#define VOP_FEATURE_OUTPUT_RGB10 BIT(0)
	45	+#define VOP_FEATURE_INTERNAL_RGB BIT(1)
39	46	#define VOP_FEATURE_ALPHA_SCALE BIT(2)
40	47	#define VOP_FEATURE_HDR10 BIT(3)
41	48	#define VOP_FEATURE_NEXT_HDR BIT(4)
42	49	/* a feature to splice two windows and two vps to support resolution > 4096 */
43	50	#define VOP_FEATURE_SPLICE BIT(5)
44	51	#define VOP_FEATURE_OVERSCAN BIT(6)
	52	+#define VOP_FEATURE_VIVID_HDR BIT(7)
	53	+#define VOP_FEATURE_POST_ACM BIT(8)
	54	+#define VOP_FEATURE_POST_CSC BIT(9)
	55	+
	56	+#define VOP_FEATURE_OUTPUT_10BIT VOP_FEATURE_OUTPUT_RGB10
	57	+
45	58
46	59	#define WIN_FEATURE_HDR2SDR BIT(0)
47	60	#define WIN_FEATURE_SDR2HDR BIT(1)
..	..	@@ -49,6 +62,8 @@
49	62	#define WIN_FEATURE_AFBDC BIT(3)
50	63	#define WIN_FEATURE_CLUSTER_MAIN BIT(4)
51	64	#define WIN_FEATURE_CLUSTER_SUB BIT(5)
	65	+/* Left win in splice mode */
	66	+#define WIN_FEATURE_SPLICE_LEFT BIT(6)
52	67	/* a mirror win can only get fb address
53	68	* from source win:
54	69	* Cluster1---->Cluster0
..	..	@@ -62,6 +77,23 @@
62	77
63	78
64	79	#define VOP2_SOC_VARIANT 4
	80	+
	81	+#define ROCKCHIP_DSC_PPS_SIZE_BYTE 88
	82	+
	83	+enum vop_vp_id {
	84	+ ROCKCHIP_VOP_VP0 = 0,
	85	+ ROCKCHIP_VOP_VP1,
	86	+ ROCKCHIP_VOP_VP2,
	87	+ ROCKCHIP_VOP_VP3,
	88	+};
	89	+
	90	+enum vop_win_phy_id {
	91	+ ROCKCHIP_VOP_WIN0 = 0,
	92	+ ROCKCHIP_VOP_WIN1,
	93	+ ROCKCHIP_VOP_WIN2,
	94	+ ROCKCHIP_VOP_WIN3,
	95	+ ROCKCHIP_VOP_PHY_ID_INVALID = -1,
	96	+};
65	97
66	98	enum bcsh_out_mode {
67	99	BCSH_OUT_MODE_BLACK,
..	..	@@ -84,7 +116,7 @@
84	116	/*
85	117	* the delay number of a window in different mode.
86	118	*/
87		-enum win_dly_mode {
	119	+enum vop2_win_dly_mode {
88	120	VOP2_DLY_MODE_DEFAULT, /*< default mode /
89	121	VOP2_DLY_MODE_HISO_S, /** HDR in SDR out mode, as a SDR window */
90	122	VOP2_DLY_MODE_HIHO_H, /** HDR in HDR out mode, as a HDR window */
..	..	@@ -92,11 +124,44 @@
92	124	};
93	125
94	126	enum vop3_esmart_lb_mode {
95		- VOP3_ESMART_ONE_8K_MODE,
96		- VOP3_ESMART_TWO_4K_MODE,
97		- VOP3_ESMART_ONE_4K_AND_TWO_2K_MODE,
98		- VOP3_ESMART_FOUR_2K_MODE,
	127	+ VOP3_ESMART_8K_MODE,
	128	+ VOP3_ESMART_4K_4K_MODE,
	129	+ VOP3_ESMART_4K_2K_2K_MODE,
	130	+ VOP3_ESMART_2K_2K_2K_2K_MODE,
99	131	};
	132	+
	133	+/*
	134	+ * vop2 dsc id
	135	+ */
	136	+#define ROCKCHIP_VOP2_DSC_8K 0
	137	+#define ROCKCHIP_VOP2_DSC_4K 1
	138	+
	139	+/*
	140	+ * vop2 internal power domain id,
	141	+ * should be all none zero, 0 will be
	142	+ * treat as invalid;
	143	+ */
	144	+#define VOP2_PD_CLUSTER0 BIT(0)
	145	+#define VOP2_PD_CLUSTER1 BIT(1)
	146	+#define VOP2_PD_CLUSTER2 BIT(2)
	147	+#define VOP2_PD_CLUSTER3 BIT(3)
	148	+#define VOP2_PD_DSC_8K BIT(5)
	149	+#define VOP2_PD_DSC_4K BIT(6)
	150	+#define VOP2_PD_ESMART BIT(7)
	151	+
	152	+/*
	153	+ * vop2 submem power gate,
	154	+ * should be all none zero, 0 will be
	155	+ * treat as invalid;
	156	+ */
	157	+#define VOP2_MEM_PG_VP0 BIT(0)
	158	+#define VOP2_MEM_PG_VP1 BIT(1)
	159	+#define VOP2_MEM_PG_VP2 BIT(2)
	160	+#define VOP2_MEM_PG_VP3 BIT(3)
	161	+#define VOP2_MEM_PG_DB0 BIT(4)
	162	+#define VOP2_MEM_PG_DB1 BIT(5)
	163	+#define VOP2_MEM_PG_DB2 BIT(6)
	164	+#define VOP2_MEM_PG_WB BIT(7)
100	165
101	166	#define DSP_BG_SWAP 0x1
102	167	#define DSP_RB_SWAP 0x2
..	..	@@ -135,6 +200,13 @@
135	200	VOP_FMT_YUV420SP = 4,
136	201	VOP_FMT_YUV422SP,
137	202	VOP_FMT_YUV444SP,
	203	+};
	204	+
	205	+enum vop_dsc_interface_mode {
	206	+ VOP_DSC_IF_DISABLE = 0,
	207	+ VOP_DSC_IF_HDMI = 1,
	208	+ VOP_DSC_IF_MIPI_DS_MODE = 2,
	209	+ VOP_DSC_IF_MIPI_VIDEO_MODE = 3,
138	210	};
139	211
140	212	struct vop_reg_data {
..	..	@@ -187,6 +259,7 @@
187	259	struct vop_reg post_scl_factor;
188	260	struct vop_reg post_scl_ctrl;
189	261	struct vop_reg dsp_interlace;
	262	+ struct vop_reg dsp_interlace_pol;
190	263	struct vop_reg global_regdone_en;
191	264	struct vop_reg auto_gate_en;
192	265	struct vop_reg post_lb_mode;
..	..	@@ -232,6 +305,11 @@
232	305	struct vop_reg sw_uv_offset_en;
233	306	struct vop_reg dsp_out_yuv;
234	307	struct vop_reg dsp_data_swap;
	308	+ struct vop_reg dsp_bg_swap;
	309	+ struct vop_reg dsp_rb_swap;
	310	+ struct vop_reg dsp_rg_swap;
	311	+ struct vop_reg dsp_delta_swap;
	312	+ struct vop_reg dsp_dummy_swap;
235	313	struct vop_reg yuv_clip;
236	314	struct vop_reg dsp_ccir656_avg;
237	315	struct vop_reg dsp_black;
..	..	@@ -439,6 +517,135 @@
439	517	const uint32_t *sdr2hdr_st2084oetf_xn;
440	518	};
441	519
	520	+#define RK_HDRVIVID_TONE_SCA_TAB_LENGTH 257
	521	+#define RK_HDRVIVID_GAMMA_CURVE_LENGTH 81
	522	+#define RK_HDRVIVID_GAMMA_MDFVALUE_LENGTH 9
	523	+#define RK_SDR2HDR_INVGAMMA_CURVE_LENGTH 69
	524	+#define RK_SDR2HDR_INVGAMMA_S_IDX_LENGTH 6
	525	+#define RK_SDR2HDR_INVGAMMA_C_IDX_LENGTH 6
	526	+#define RK_SDR2HDR_SMGAIN_LENGTH 64
	527	+#define RK_HDRVIVID_TONE_SCA_AXI_TAB_LENGTH 264
	528	+
	529	+struct hdrvivid_regs {
	530	+ uint32_t sdr2hdr_ctrl;
	531	+ uint32_t sdr2hdr_coe0;
	532	+ uint32_t sdr2hdr_coe1;
	533	+ uint32_t sdr2hdr_csc_coe00_01;
	534	+ uint32_t sdr2hdr_csc_coe02_10;
	535	+ uint32_t sdr2hdr_csc_coe11_12;
	536	+ uint32_t sdr2hdr_csc_coe20_21;
	537	+ uint32_t sdr2hdr_csc_coe22;
	538	+ uint32_t hdrvivid_ctrl;
	539	+ uint32_t hdr_pq_gamma;
	540	+ uint32_t hlg_rfix_scalefac;
	541	+ uint32_t hlg_maxluma;
	542	+ uint32_t hlg_r_tm_lin2non;
	543	+ uint32_t hdr_csc_coe00_01;
	544	+ uint32_t hdr_csc_coe02_10;
	545	+ uint32_t hdr_csc_coe11_12;
	546	+ uint32_t hdr_csc_coe20_21;
	547	+ uint32_t hdr_csc_coe22;
	548	+ uint32_t hdr_tone_sca[RK_HDRVIVID_TONE_SCA_TAB_LENGTH];
	549	+ uint32_t hdrgamma_curve[RK_HDRVIVID_GAMMA_CURVE_LENGTH];
	550	+ uint32_t hdrgamma_mdfvalue[RK_HDRVIVID_GAMMA_MDFVALUE_LENGTH];
	551	+ uint32_t sdrinvgamma_curve[RK_SDR2HDR_INVGAMMA_CURVE_LENGTH];
	552	+ uint32_t sdrinvgamma_startidx[RK_SDR2HDR_INVGAMMA_S_IDX_LENGTH];
	553	+ uint32_t sdrinvgamma_changeidx[RK_SDR2HDR_INVGAMMA_C_IDX_LENGTH];
	554	+ uint32_t sdr_smgain[RK_SDR2HDR_SMGAIN_LENGTH];
	555	+ uint32_t hdr_mode;
	556	+ uint32_t tone_sca_axi_tab[RK_HDRVIVID_TONE_SCA_AXI_TAB_LENGTH];
	557	+};
	558	+
	559	+struct hdr_extend {
	560	+ uint32_t hdr_type;
	561	+ uint32_t length;
	562	+ union {
	563	+ struct hdrvivid_regs hdrvivid_data;
	564	+ };
	565	+};
	566	+
	567	+enum _vop_hdrvivid_mode {
	568	+ PQHDR2HDR_WITH_DYNAMIC = 0,
	569	+ PQHDR2SDR_WITH_DYNAMIC,
	570	+ HLG2PQHDR_WITH_DYNAMIC,
	571	+ HLG2SDR_WITH_DYNAMIC,
	572	+ HLG2PQHDR_WITHOUT_DYNAMIC,
	573	+ HLG2SDR_WITHOUT_DYNAMIC,
	574	+ HDR_BYPASS,
	575	+ HDR102SDR,
	576	+ SDR2HDR10,
	577	+ SDR2HLG,
	578	+ SDR2HDR10_USERSPACE = 100,
	579	+ SDR2HLG_USERSPACE = 101,
	580	+};
	581	+
	582	+enum vop_hdr_format {
	583	+ HDR_NONE = 0,
	584	+ HDR_HDR10 = 1,
	585	+ HDR_HLGSTATIC = 2,
	586	+ RESERVED3 = 3, /* reserved for more future static hdr format */
	587	+ RESERVED4 = 4, /* reserved for more future static hdr format */
	588	+ HDR_HDRVIVID = 5,
	589	+ RESERVED6 = 6, /* reserved for hdr vivid */
	590	+ RESERVED7 = 7, /* reserved for hdr vivid */
	591	+ HDR_HDR10PLUS = 8,
	592	+ RESERVED9 = 9, /* reserved for hdr hdr10+ */
	593	+ RESERVED10 = 10, /* reserved for hdr hdr10+ */
	594	+ HDR_NEXT = 11,
	595	+ RESERVED12 = 12, /* reserved for other dynamic hdr format */
	596	+ RESERVED13 = 13, /* reserved for other dynamic hdr format */
	597	+ HDR_FORMAT_MAX,
	598	+};
	599	+
	600	+#define ACM_GAIN_LUT_HY_LENGTH (9*17)
	601	+#define ACM_GAIN_LUT_HY_TOTAL_LENGTH (ACM_GAIN_LUT_HY_LENGTH * 3)
	602	+#define ACM_GAIN_LUT_HS_LENGTH (13*17)
	603	+#define ACM_GAIN_LUT_HS_TOTAL_LENGTH (ACM_GAIN_LUT_HS_LENGTH * 3)
	604	+#define ACM_DELTA_LUT_H_LENGTH 65
	605	+#define ACM_DELTA_LUT_H_TOTAL_LENGTH (ACM_DELTA_LUT_H_LENGTH * 3)
	606	+
	607	+struct post_acm {
	608	+ s16 delta_lut_h[ACM_DELTA_LUT_H_TOTAL_LENGTH];
	609	+ s16 gain_lut_hy[ACM_GAIN_LUT_HY_TOTAL_LENGTH];
	610	+ s16 gain_lut_hs[ACM_GAIN_LUT_HS_TOTAL_LENGTH];
	611	+ u16 y_gain;
	612	+ u16 h_gain;
	613	+ u16 s_gain;
	614	+ u16 acm_enable;
	615	+};
	616	+
	617	+struct post_csc {
	618	+ u16 hue;
	619	+ u16 saturation;
	620	+ u16 contrast;
	621	+ u16 brightness;
	622	+ u16 r_gain;
	623	+ u16 g_gain;
	624	+ u16 b_gain;
	625	+ u16 r_offset;
	626	+ u16 g_offset;
	627	+ u16 b_offset;
	628	+ u16 csc_enable;
	629	+};
	630	+
	631	+struct post_csc_coef {
	632	+ s32 csc_coef00;
	633	+ s32 csc_coef01;
	634	+ s32 csc_coef02;
	635	+ s32 csc_coef10;
	636	+ s32 csc_coef11;
	637	+ s32 csc_coef12;
	638	+ s32 csc_coef20;
	639	+ s32 csc_coef21;
	640	+ s32 csc_coef22;
	641	+
	642	+ s32 csc_dc0;
	643	+ s32 csc_dc1;
	644	+ s32 csc_dc2;
	645	+
	646	+ u32 range_type;
	647	+};
	648	+
442	649	enum {
443	650	VOP_CSC_Y2R_BT601,
444	651	VOP_CSC_Y2R_BT709,
..	..	@@ -480,6 +687,7 @@
480	687	struct vop_reg gate;
481	688	struct vop_reg enable;
482	689	struct vop_reg format;
	690	+ struct vop_reg interlace_read;
483	691	struct vop_reg fmt_10;
484	692	struct vop_reg fmt_yuyv;
485	693	struct vop_reg csc_mode;
..	..	@@ -505,10 +713,23 @@
505	713	struct vop_reg color_key_en;
506	714	};
507	715
	716	+struct vop_win_data {
	717	+ uint32_t base;
	718	+ enum drm_plane_type type;
	719	+ const struct vop_win_phy *phy;
	720	+ const struct vop_win_phy **area;
	721	+ const uint64_t *format_modifiers;
	722	+ const struct vop_csc *csc;
	723	+ unsigned int area_size;
	724	+ u64 feature;
	725	+};
	726	+
508	727	struct vop2_cluster_regs {
509	728	struct vop_reg enable;
510	729	struct vop_reg afbc_enable;
511	730	struct vop_reg lb_mode;
	731	+ struct vop_reg scl_lb_mode;
	732	+ struct vop_reg frm_reset_en;
512	733
513	734	struct vop_reg src_color_ctrl;
514	735	struct vop_reg dst_color_ctrl;
..	..	@@ -597,7 +818,9 @@
597	818	struct vop_reg pre_scan_htiming;
598	819	struct vop_reg htotal_pw;
599	820	struct vop_reg hact_st_end;
600		- struct vop_reg vtotal_pw;
	821	+ struct vop_reg dsp_vtotal;
	822	+ struct vop_reg sw_dsp_vtotal_imd;
	823	+ struct vop_reg dsp_vs_end;
601	824	struct vop_reg vact_st_end;
602	825	struct vop_reg vact_st_end_f1;
603	826	struct vop_reg vs_st_end_f1;
..	..	@@ -615,8 +838,8 @@
615	838
616	839	struct vop_reg core_dclk_div;
617	840	struct vop_reg p2i_en;
618		- struct vop_reg mipi_dual_en;
619		- struct vop_reg mipi_dual_channel_swap;
	841	+ struct vop_reg dual_channel_en;
	842	+ struct vop_reg dual_channel_swap;
620	843	struct vop_reg dsp_lut_en;
621	844
622	845	struct vop_reg dclk_div2;
..	..	@@ -626,6 +849,13 @@
626	849	struct vop_reg hdr_lut_update_en;
627	850	struct vop_reg hdr_lut_mode;
628	851	struct vop_reg hdr_lut_mst;
	852	+ struct vop_reg hdr_lut_fetch_done;
	853	+ struct vop_reg hdr_vivid_en;
	854	+ struct vop_reg hdr_vivid_bypass_en;
	855	+ struct vop_reg hdr_vivid_path_mode;
	856	+ struct vop_reg hdr_vivid_dstgamut;
	857	+ struct vop_reg sdr2hdr_en;
	858	+ struct vop_reg sdr2hdr_dstmode;
629	859	struct vop_reg sdr2hdr_eotf_en;
630	860	struct vop_reg sdr2hdr_r2r_en;
631	861	struct vop_reg sdr2hdr_r2r_mode;
..	..	@@ -672,11 +902,108 @@
672	902	struct vop_reg cubic_lut_update_en;
673	903	struct vop_reg cubic_lut_mst;
674	904
	905	+ /* cru */
	906	+ struct vop_reg dclk_core_div;
	907	+ struct vop_reg dclk_out_div;
	908	+ struct vop_reg dclk_src_sel;
	909	+
	910	+ struct vop_reg splice_en;
	911	+
675	912	struct vop_reg edpi_wms_hold_en;
676	913	struct vop_reg edpi_te_en;
677	914	struct vop_reg edpi_wms_fs;
678	915	struct vop_reg gamma_update_en;
679	916	struct vop_reg lut_dma_rid;
	917	+
	918	+ /* MCU output */
	919	+ struct vop_reg mcu_pix_total;
	920	+ struct vop_reg mcu_cs_pst;
	921	+ struct vop_reg mcu_cs_pend;
	922	+ struct vop_reg mcu_rw_pst;
	923	+ struct vop_reg mcu_rw_pend;
	924	+ struct vop_reg mcu_clk_sel;
	925	+ struct vop_reg mcu_hold_mode;
	926	+ struct vop_reg mcu_frame_st;
	927	+ struct vop_reg mcu_rs;
	928	+ struct vop_reg mcu_bypass;
	929	+ struct vop_reg mcu_type;
	930	+ struct vop_reg mcu_rw_bypass_port;
	931	+
	932	+ /* for DCF */
	933	+ struct vop_reg line_flag_or_en;
	934	+ struct vop_reg dsp_hold_or_en;
	935	+ struct vop_reg almost_full_or_en;
	936	+
	937	+ /* CSC */
	938	+ struct vop_reg acm_bypass_en;
	939	+ struct vop_reg csc_en;
	940	+ struct vop_reg acm_r2y_en;
	941	+ struct vop_reg csc_mode;
	942	+ struct vop_reg acm_r2y_mode;
	943	+ struct vop_reg csc_coe00;
	944	+ struct vop_reg csc_coe01;
	945	+ struct vop_reg csc_coe02;
	946	+ struct vop_reg csc_coe10;
	947	+ struct vop_reg csc_coe11;
	948	+ struct vop_reg csc_coe12;
	949	+ struct vop_reg csc_coe20;
	950	+ struct vop_reg csc_coe21;
	951	+ struct vop_reg csc_coe22;
	952	+ struct vop_reg csc_offset0;
	953	+ struct vop_reg csc_offset1;
	954	+ struct vop_reg csc_offset2;
	955	+
	956	+ /* color bar */
	957	+ struct vop_reg color_bar_en;
	958	+ struct vop_reg color_bar_mode;
	959	+};
	960	+
	961	+struct vop2_power_domain_regs {
	962	+ struct vop_reg pd;
	963	+ struct vop_reg status;
	964	+ struct vop_reg bisr_en_status;
	965	+ struct vop_reg pmu_status;
	966	+};
	967	+
	968	+struct vop2_dsc_regs {
	969	+ /* DSC SYS CTRL */
	970	+ struct vop_reg dsc_port_sel;
	971	+ struct vop_reg dsc_man_mode;
	972	+ struct vop_reg dsc_interface_mode;
	973	+ struct vop_reg dsc_pixel_num;
	974	+ struct vop_reg dsc_pxl_clk_div;
	975	+ struct vop_reg dsc_cds_clk_div;
	976	+ struct vop_reg dsc_txp_clk_div;
	977	+ struct vop_reg dsc_init_dly_mode;
	978	+ struct vop_reg dsc_scan_en;
	979	+ struct vop_reg dsc_halt_en;
	980	+ struct vop_reg rst_deassert;
	981	+ struct vop_reg dsc_flush;
	982	+ struct vop_reg dsc_cfg_done;
	983	+ struct vop_reg dsc_init_dly_num;
	984	+ struct vop_reg scan_timing_para_imd_en;
	985	+ struct vop_reg dsc_htotal_pw;
	986	+ struct vop_reg dsc_hact_st_end;
	987	+ struct vop_reg dsc_vtotal;
	988	+ struct vop_reg dsc_vs_end;
	989	+ struct vop_reg dsc_vact_st_end;
	990	+ struct vop_reg dsc_error_status;
	991	+
	992	+ /* DSC encoder */
	993	+ struct vop_reg dsc_pps0_3;
	994	+ struct vop_reg dsc_en;
	995	+ struct vop_reg dsc_rbit;
	996	+ struct vop_reg dsc_rbyt;
	997	+ struct vop_reg dsc_flal;
	998	+ struct vop_reg dsc_mer;
	999	+ struct vop_reg dsc_epb;
	1000	+ struct vop_reg dsc_epl;
	1001	+ struct vop_reg dsc_nslc;
	1002	+ struct vop_reg dsc_sbo;
	1003	+ struct vop_reg dsc_ifep;
	1004	+ struct vop_reg dsc_pps_upd;
	1005	+ struct vop_reg dsc_status;
	1006	+ struct vop_reg dsc_ecw;
680	1007	};
681	1008
682	1009	struct vop2_wb_regs {
..	..	@@ -695,23 +1022,42 @@
695	1022	struct vop_reg axi_uv_id;
696	1023	};
697	1024
698		-struct vop_win_data {
699		- uint32_t base;
700		- enum drm_plane_type type;
701		- const struct vop_win_phy *phy;
702		- const struct vop_win_phy **area;
703		- const struct vop_csc *csc;
704		- unsigned int area_size;
705		- u64 feature;
	1025	+struct vop2_power_domain_data {
	1026	+ uint8_t id;
	1027	+ uint8_t parent_id;
	1028	+ /*
	1029	+ * @module_id_mask: module id of which module this power domain is belongs to.
	1030	+ * PD_CLUSTER0,1,2,3 only belongs to CLUSTER0/1/2/3, PD_Esmart0 shared by Esmart1/2/3
	1031	+ */
	1032	+ uint32_t module_id_mask;
	1033	+
	1034	+ const struct vop2_power_domain_regs *regs;
	1035	+};
	1036	+
	1037	+/*
	1038	+ * connector interface(RGB/HDMI/eDP/DP/MIPI) data
	1039	+ */
	1040	+struct vop2_connector_if_data {
	1041	+ u32 id;
	1042	+ const char *clk_src_name;
	1043	+ const char *clk_parent_name;
	1044	+ const char *pixclk_name;
	1045	+ const char *dclk_name;
	1046	+ u32 post_proc_div_shift;
	1047	+ u32 if_div_shift;
	1048	+ u32 if_div_yuv420_shift;
	1049	+ u32 bus_div_shift;
	1050	+ u32 pixel_clk_div_shift;
706	1051	};
707	1052
708	1053	struct vop2_win_data {
709	1054	const char *name;
710	1055	uint8_t phys_id;
	1056	+ uint8_t splice_win_id;
	1057	+ uint8_t pd_id;
711	1058	uint8_t axi_id;
712	1059	uint8_t axi_yrgb_id;
713	1060	uint8_t axi_uv_id;
714		- uint8_t scale_engine_num;
715	1061	uint8_t possible_crtcs;
716	1062
717	1063	uint32_t base;
..	..	@@ -746,6 +1092,24 @@
746	1092	const uint8_t dly[VOP2_DLY_MODE_MAX];
747	1093	};
748	1094
	1095	+struct dsc_error_info {
	1096	+ u32 dsc_error_val;
	1097	+ char dsc_error_info[50];
	1098	+};
	1099	+
	1100	+struct vop2_dsc_data {
	1101	+ uint8_t id;
	1102	+ uint8_t pd_id;
	1103	+ uint8_t max_slice_num;
	1104	+ uint8_t max_linebuf_depth; /* used to generate the bitstream */
	1105	+ uint8_t min_bits_per_pixel; /* bit num after encoder compress */
	1106	+ const char *dsc_txp_clk_src_name;
	1107	+ const char *dsc_txp_clk_name;
	1108	+ const char *dsc_pxl_clk_name;
	1109	+ const char *dsc_cds_clk_name;
	1110	+ const struct vop2_dsc_regs *regs;
	1111	+};
	1112	+
749	1113	struct vop2_wb_data {
750	1114	uint32_t nformats;
751	1115	const uint32_t *formats;
..	..	@@ -768,13 +1132,20 @@
768	1132
769	1133	struct vop2_video_port_data {
770	1134	char id;
	1135	+ uint8_t splice_vp_id;
771	1136	uint16_t lut_dma_rid;
772	1137	uint32_t feature;
773	1138	uint64_t soc_id[VOP2_SOC_VARIANT];
774	1139	uint16_t gamma_lut_len;
775	1140	uint16_t cubic_lut_len;
	1141	+ unsigned long dclk_max;
776	1142	struct vop_rect max_output;
777	1143	const u8 pre_scan_max_dly[4];
	1144	+ const u8 hdrvivid_dly[10];
	1145	+ const u8 sdr2hdr_dly;
	1146	+ const u8 layer_mix_dly;
	1147	+ const u8 hdr_mix_dly;
	1148	+ const u8 win_dly;
778	1149	const struct vop_intr *intr;
779	1150	const struct vop_hdr_table *hdr_table;
780	1151	const struct vop2_video_port_regs *regs;
..	..	@@ -818,6 +1189,14 @@
818	1189	struct vop_reg grf_dclk_inv;
819	1190	struct vop_reg grf_bt1120_clk_inv;
820	1191	struct vop_reg grf_bt656_clk_inv;
	1192	+ struct vop_reg grf_edp0_en;
	1193	+ struct vop_reg grf_edp1_en;
	1194	+ struct vop_reg grf_hdmi0_en;
	1195	+ struct vop_reg grf_hdmi1_en;
	1196	+ struct vop_reg grf_hdmi0_dsc_en;
	1197	+ struct vop_reg grf_hdmi1_dsc_en;
	1198	+ struct vop_reg grf_hdmi0_pin_pol;
	1199	+ struct vop_reg grf_hdmi1_pin_pol;
821	1200	};
822	1201
823	1202	struct vop_data {
..	..	@@ -835,6 +1214,7 @@
835	1214	struct vop_rect max_output;
836	1215	u64 feature;
837	1216	u64 soc_id;
	1217	+ u8 vop_id;
838	1218	};
839	1219
840	1220	struct vop2_ctrl {
..	..	@@ -842,6 +1222,9 @@
842	1222	struct vop_reg wb_cfg_done;
843	1223	struct vop_reg auto_gating_en;
844	1224	struct vop_reg aclk_pre_auto_gating_en;
	1225	+ struct vop_reg dma_finish_mode;
	1226	+ struct vop_reg axi_dma_finish_and_en;
	1227	+ struct vop_reg wb_dma_finish_and_en;
845	1228	struct vop_reg ovl_cfg_done_port;
846	1229	struct vop_reg ovl_port_mux_cfg_done_imd;
847	1230	struct vop_reg ovl_port_mux_cfg;
..	..	@@ -849,6 +1232,7 @@
849	1232	struct vop_reg version;
850	1233	struct vop_reg standby;
851	1234	struct vop_reg dma_stop;
	1235	+ struct vop_reg dsp_vs_t_sel;
852	1236	struct vop_reg lut_dma_en;
853	1237	struct vop_reg axi_outstanding_max_num;
854	1238	struct vop_reg axi_max_outstanding_en;
..	..	@@ -880,9 +1264,12 @@
880	1264	struct vop_reg edp_pin_pol;
881	1265	struct vop_reg mipi_dclk_pol;
882	1266	struct vop_reg mipi_pin_pol;
883		- struct vop_reg dp_dclk_pol;
884		- struct vop_reg dp_pin_pol;
	1267	+ struct vop_reg dp0_dclk_pol;
	1268	+ struct vop_reg dp0_pin_pol;
	1269	+ struct vop_reg dp1_dclk_pol;
	1270	+ struct vop_reg dp1_pin_pol;
885	1271
	1272	+ /* This will be reference by win_phy_id */
886	1273	struct vop_reg win_vp_id[16];
887	1274	struct vop_reg win_dly[16];
888	1275
..	..	@@ -903,10 +1290,25 @@
903	1290	struct vop_reg lvds_dual_mode;
904	1291	struct vop_reg lvds_dual_channel_swap;
905	1292
906		- struct vop_reg cluster0_src_color_ctrl;
907		- struct vop_reg cluster0_dst_color_ctrl;
908		- struct vop_reg cluster0_src_alpha_ctrl;
909		- struct vop_reg cluster0_dst_alpha_ctrl;
	1293	+ struct vop_reg dp_dual_en;
	1294	+ struct vop_reg edp_dual_en;
	1295	+ struct vop_reg hdmi_dual_en;
	1296	+ struct vop_reg mipi_dual_en;
	1297	+
	1298	+ struct vop_reg hdmi0_dclk_div;
	1299	+ struct vop_reg hdmi0_pixclk_div;
	1300	+ struct vop_reg edp0_dclk_div;
	1301	+ struct vop_reg edp0_pixclk_div;
	1302	+
	1303	+ struct vop_reg hdmi1_dclk_div;
	1304	+ struct vop_reg hdmi1_pixclk_div;
	1305	+ struct vop_reg edp1_dclk_div;
	1306	+ struct vop_reg edp1_pixclk_div;
	1307	+
	1308	+ struct vop_reg mipi0_pixclk_div;
	1309	+ struct vop_reg mipi1_pixclk_div;
	1310	+ struct vop_reg mipi0_ds_mode;
	1311	+ struct vop_reg mipi1_ds_mode;
910	1312
911	1313	struct vop_reg src_color_ctrl;
912	1314	struct vop_reg dst_color_ctrl;
..	..	@@ -916,6 +1318,7 @@
916	1318	struct vop_reg bt1120_yc_swap;
917	1319	struct vop_reg bt656_yc_swap;
918	1320	struct vop_reg gamma_port_sel;
	1321	+ struct vop_reg pd_off_imd;
919	1322
920	1323	struct vop_reg otp_en;
921	1324	struct vop_reg esmart_lb_mode;
..	..	@@ -930,6 +1333,12 @@
930	1333	bool enable_state;
931	1334	};
932	1335
	1336	+struct vop2_vp_plane_mask {
	1337	+ u8 primary_plane_id;
	1338	+ u8 attached_layers_nr;
	1339	+ u8 attached_layers[ROCKCHIP_MAX_LAYER];
	1340	+};
	1341	+
933	1342	/**
934	1343	* VOP2 data structe
935	1344	*
..	..	@@ -939,25 +1348,43 @@
939	1348	struct vop2_data {
940	1349	uint32_t version;
941	1350	uint32_t feature;
	1351	+ uint8_t nr_dscs;
	1352	+ uint8_t nr_dsc_ecw;
	1353	+ uint8_t nr_dsc_buffer_flow;
942	1354	uint8_t nr_vps;
943	1355	uint8_t nr_mixers;
944	1356	uint8_t nr_layers;
945	1357	uint8_t nr_axi_intr;
946	1358	uint8_t nr_gammas;
	1359	+ uint8_t nr_conns;
	1360	+ uint8_t nr_pds;
	1361	+ uint8_t nr_mem_pgs;
947	1362	uint8_t esmart_lb_mode;
	1363	+ bool delayed_pd;
948	1364	const struct vop_intr *axi_intr;
949	1365	const struct vop2_ctrl *ctrl;
	1366	+ const struct vop2_dsc_data *dsc;
	1367	+ const struct dsc_error_info *dsc_error_ecw;
	1368	+ const struct dsc_error_info *dsc_error_buffer_flow;
950	1369	const struct vop2_win_data *win;
951	1370	const struct vop2_video_port_data *vp;
	1371	+ const struct vop2_connector_if_data *conn;
952	1372	const struct vop2_wb_data *wb;
953	1373	const struct vop2_layer_data *layer;
	1374	+ const struct vop2_power_domain_data *pd;
	1375	+ const struct vop2_power_domain_data *mem_pg;
954	1376	const struct vop_csc_table *csc_table;
955	1377	const struct vop_hdr_table *hdr_table;
956		- const struct vop_grf_ctrl *grf_ctrl;
	1378	+ const struct vop_grf_ctrl *sys_grf;
	1379	+ const struct vop_grf_ctrl *grf;
	1380	+ const struct vop_grf_ctrl *vo0_grf;
	1381	+ const struct vop_grf_ctrl *vo1_grf;
957	1382	const struct vop_dump_regs *dump_regs;
958	1383	uint32_t dump_regs_size;
959	1384	struct vop_rect max_input;
960	1385	struct vop_rect max_output;
	1386	+ const struct vop2_vp_plane_mask *plane_mask;
	1387	+ uint32_t plane_mask_base;
961	1388
962	1389	unsigned int win_size;
963	1390	};
..	..	@@ -1034,6 +1461,7 @@
1034	1461	#define ROCKCHIP_OUT_MODE_P565 2
1035	1462	#define ROCKCHIP_OUT_MODE_BT656 5
1036	1463	#define ROCKCHIP_OUT_MODE_S888 8
	1464	+#define ROCKCHIP_OUT_MODE_YUV422 9
1037	1465	#define ROCKCHIP_OUT_MODE_S888_DUMMY 12
1038	1466	#define ROCKCHIP_OUT_MODE_YUV420 14
1039	1467	/* for use special outface */
..	..	@@ -1150,6 +1578,7 @@
1150	1578	DCLK_INVERT = 3
1151	1579	};
1152	1580
	1581	+
1153	1582	#define FRAC_16_16(mult, div) (((mult) << 16) / (div))
1154	1583	#define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12
1155	1584	#define SCL_MAX_VSKIPLINES 4
..	..	@@ -1234,7 +1663,6 @@
1234	1663	return y1 + (y2 - y1) * (x - x1) / (x2 - x1);
1235	1664	}
1236	1665
1237		-extern void vop2_standby(struct drm_crtc *crtc, bool standby);
1238	1666	extern const struct component_ops vop_component_ops;
1239	1667	extern const struct component_ops vop2_component_ops;
1240	1668	#endif /* _ROCKCHIP_DRM_VOP_H */