~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,42 +1,48 @@
	1	+/* SPDX-License-Identifier: GPL-2.0-only */
1	2	/*
2	3	* Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3	4	* Author:Mark Yao <mark.yao@rock-chips.com>
4		- *
5		- * This software is licensed under the terms of the GNU General Public
6		- * License version 2, as published by the Free Software Foundation, and
7		- * may be copied, distributed, and modified under those terms.
8		- *
9		- * This program is distributed in the hope that it will be useful,
10		- * but WITHOUT ANY WARRANTY; without even the implied warranty of
11		- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12		- * GNU General Public License for more details.
13	5	*/
14	6
15	7	#ifndef _ROCKCHIP_DRM_VOP_H
16	8	#define _ROCKCHIP_DRM_VOP_H
	9	+
	10	+#include <drm/drm_plane.h>
	11	+#include <drm/drm_modes.h>
	12	+
17	13	#include "rockchip_drm_drv.h"
18	14
19	15	/*
20	16	* major: IP major version, used for IP structure
21	17	* minor: big feature change under same structure
	18	+ * build: RTL current SVN number
22	19	*/
23	20	#define VOP_VERSION(major, minor) ((major) << 8 \| (minor))
24	21	#define VOP_MAJOR(version) ((version) >> 8)
25	22	#define VOP_MINOR(version) ((version) & 0xff)
26	23
27		-#define VOP_VERSION_RK3528 VOP_VERSION(0x50, 0x17)
28		-#define VOP_VERSION_RK3568 VOP_VERSION(0x40, 0x15)
29		-#define VOP_VERSION_RK3588 VOP_VERSION(0x40, 0x17)
	24	+#define VOP2_VERSION(major, minor, build) ((major) << 24 \| (minor) << 16 \| (build))
	25	+#define VOP2_MAJOR(version) (((version) >> 24) & 0xff)
	26	+#define VOP2_MINOR(version) (((version) >> 16) & 0xff)
	27	+#define VOP2_BUILD(version) ((version) & 0xffff)
	28	+
	29	+#define VOP_VERSION_RK3528 VOP2_VERSION(0x50, 0x17, 0x1263)
	30	+#define VOP_VERSION_RK3562 VOP2_VERSION(0x50, 0x17, 0x4350)
	31	+#define VOP_VERSION_RK3568 VOP2_VERSION(0x40, 0x15, 0x8023)
	32	+#define VOP_VERSION_RK3588 VOP2_VERSION(0x40, 0x17, 0x6786)
30	33
31	34	#define ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE BIT(0)
32	35	#define ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE BIT(1)
33	36	#define ROCKCHIP_OUTPUT_DATA_SWAP BIT(2)
	37	+/* MIPI DSI DataStream(cmd) mode on rk3588 */
	38	+#define ROCKCHIP_OUTPUT_MIPI_DS_MODE BIT(3)
34	39
35	40	#define AFBDC_FMT_RGB565 0x0
36	41	#define AFBDC_FMT_U8U8U8U8 0x5
37	42	#define AFBDC_FMT_U8U8U8 0x4
38		-#define VOP_FEATURE_OUTPUT_10BIT BIT(0)
39		-#define VOP_FEATURE_AFBDC BIT(1)
	43	+
	44	+#define VOP_FEATURE_OUTPUT_RGB10 BIT(0)
	45	+#define VOP_FEATURE_INTERNAL_RGB BIT(1)
40	46	#define VOP_FEATURE_ALPHA_SCALE BIT(2)
41	47	#define VOP_FEATURE_HDR10 BIT(3)
42	48	#define VOP_FEATURE_NEXT_HDR BIT(4)
..	..	@@ -47,12 +53,17 @@
47	53	#define VOP_FEATURE_POST_ACM BIT(8)
48	54	#define VOP_FEATURE_POST_CSC BIT(9)
49	55
	56	+#define VOP_FEATURE_OUTPUT_10BIT VOP_FEATURE_OUTPUT_RGB10
	57	+
	58	+
50	59	#define WIN_FEATURE_HDR2SDR BIT(0)
51	60	#define WIN_FEATURE_SDR2HDR BIT(1)
52	61	#define WIN_FEATURE_PRE_OVERLAY BIT(2)
53	62	#define WIN_FEATURE_AFBDC BIT(3)
54	63	#define WIN_FEATURE_CLUSTER_MAIN BIT(4)
55	64	#define WIN_FEATURE_CLUSTER_SUB BIT(5)
	65	+/* Left win in splice mode */
	66	+#define WIN_FEATURE_SPLICE_LEFT BIT(6)
56	67	/* a mirror win can only get fb address
57	68	* from source win:
58	69	* Cluster1---->Cluster0
..	..	@@ -66,6 +77,23 @@
66	77
67	78
68	79	#define VOP2_SOC_VARIANT 4
	80	+
	81	+#define ROCKCHIP_DSC_PPS_SIZE_BYTE 88
	82	+
	83	+enum vop_vp_id {
	84	+ ROCKCHIP_VOP_VP0 = 0,
	85	+ ROCKCHIP_VOP_VP1,
	86	+ ROCKCHIP_VOP_VP2,
	87	+ ROCKCHIP_VOP_VP3,
	88	+};
	89	+
	90	+enum vop_win_phy_id {
	91	+ ROCKCHIP_VOP_WIN0 = 0,
	92	+ ROCKCHIP_VOP_WIN1,
	93	+ ROCKCHIP_VOP_WIN2,
	94	+ ROCKCHIP_VOP_WIN3,
	95	+ ROCKCHIP_VOP_PHY_ID_INVALID = -1,
	96	+};
69	97
70	98	enum bcsh_out_mode {
71	99	BCSH_OUT_MODE_BLACK,
..	..	@@ -88,7 +116,7 @@
88	116	/*
89	117	* the delay number of a window in different mode.
90	118	*/
91		-enum win_dly_mode {
	119	+enum vop2_win_dly_mode {
92	120	VOP2_DLY_MODE_DEFAULT, /*< default mode /
93	121	VOP2_DLY_MODE_HISO_S, /** HDR in SDR out mode, as a SDR window */
94	122	VOP2_DLY_MODE_HIHO_H, /** HDR in HDR out mode, as a HDR window */
..	..	@@ -101,6 +129,39 @@
101	129	VOP3_ESMART_4K_2K_2K_MODE,
102	130	VOP3_ESMART_2K_2K_2K_2K_MODE,
103	131	};
	132	+
	133	+/*
	134	+ * vop2 dsc id
	135	+ */
	136	+#define ROCKCHIP_VOP2_DSC_8K 0
	137	+#define ROCKCHIP_VOP2_DSC_4K 1
	138	+
	139	+/*
	140	+ * vop2 internal power domain id,
	141	+ * should be all none zero, 0 will be
	142	+ * treat as invalid;
	143	+ */
	144	+#define VOP2_PD_CLUSTER0 BIT(0)
	145	+#define VOP2_PD_CLUSTER1 BIT(1)
	146	+#define VOP2_PD_CLUSTER2 BIT(2)
	147	+#define VOP2_PD_CLUSTER3 BIT(3)
	148	+#define VOP2_PD_DSC_8K BIT(5)
	149	+#define VOP2_PD_DSC_4K BIT(6)
	150	+#define VOP2_PD_ESMART BIT(7)
	151	+
	152	+/*
	153	+ * vop2 submem power gate,
	154	+ * should be all none zero, 0 will be
	155	+ * treat as invalid;
	156	+ */
	157	+#define VOP2_MEM_PG_VP0 BIT(0)
	158	+#define VOP2_MEM_PG_VP1 BIT(1)
	159	+#define VOP2_MEM_PG_VP2 BIT(2)
	160	+#define VOP2_MEM_PG_VP3 BIT(3)
	161	+#define VOP2_MEM_PG_DB0 BIT(4)
	162	+#define VOP2_MEM_PG_DB1 BIT(5)
	163	+#define VOP2_MEM_PG_DB2 BIT(6)
	164	+#define VOP2_MEM_PG_WB BIT(7)
104	165
105	166	#define DSP_BG_SWAP 0x1
106	167	#define DSP_RB_SWAP 0x2
..	..	@@ -139,6 +200,13 @@
139	200	VOP_FMT_YUV420SP = 4,
140	201	VOP_FMT_YUV422SP,
141	202	VOP_FMT_YUV444SP,
	203	+};
	204	+
	205	+enum vop_dsc_interface_mode {
	206	+ VOP_DSC_IF_DISABLE = 0,
	207	+ VOP_DSC_IF_HDMI = 1,
	208	+ VOP_DSC_IF_MIPI_DS_MODE = 2,
	209	+ VOP_DSC_IF_MIPI_VIDEO_MODE = 3,
142	210	};
143	211
144	212	struct vop_reg_data {
..	..	@@ -191,6 +259,7 @@
191	259	struct vop_reg post_scl_factor;
192	260	struct vop_reg post_scl_ctrl;
193	261	struct vop_reg dsp_interlace;
	262	+ struct vop_reg dsp_interlace_pol;
194	263	struct vop_reg global_regdone_en;
195	264	struct vop_reg auto_gate_en;
196	265	struct vop_reg post_lb_mode;
..	..	@@ -236,6 +305,11 @@
236	305	struct vop_reg sw_uv_offset_en;
237	306	struct vop_reg dsp_out_yuv;
238	307	struct vop_reg dsp_data_swap;
	308	+ struct vop_reg dsp_bg_swap;
	309	+ struct vop_reg dsp_rb_swap;
	310	+ struct vop_reg dsp_rg_swap;
	311	+ struct vop_reg dsp_delta_swap;
	312	+ struct vop_reg dsp_dummy_swap;
239	313	struct vop_reg yuv_clip;
240	314	struct vop_reg dsp_ccir656_avg;
241	315	struct vop_reg dsp_black;
..	..	@@ -523,6 +597,37 @@
523	597	HDR_FORMAT_MAX,
524	598	};
525	599
	600	+#define ACM_GAIN_LUT_HY_LENGTH (9*17)
	601	+#define ACM_GAIN_LUT_HY_TOTAL_LENGTH (ACM_GAIN_LUT_HY_LENGTH * 3)
	602	+#define ACM_GAIN_LUT_HS_LENGTH (13*17)
	603	+#define ACM_GAIN_LUT_HS_TOTAL_LENGTH (ACM_GAIN_LUT_HS_LENGTH * 3)
	604	+#define ACM_DELTA_LUT_H_LENGTH 65
	605	+#define ACM_DELTA_LUT_H_TOTAL_LENGTH (ACM_DELTA_LUT_H_LENGTH * 3)
	606	+
	607	+struct post_acm {
	608	+ s16 delta_lut_h[ACM_DELTA_LUT_H_TOTAL_LENGTH];
	609	+ s16 gain_lut_hy[ACM_GAIN_LUT_HY_TOTAL_LENGTH];
	610	+ s16 gain_lut_hs[ACM_GAIN_LUT_HS_TOTAL_LENGTH];
	611	+ u16 y_gain;
	612	+ u16 h_gain;
	613	+ u16 s_gain;
	614	+ u16 acm_enable;
	615	+};
	616	+
	617	+struct post_csc {
	618	+ u16 hue;
	619	+ u16 saturation;
	620	+ u16 contrast;
	621	+ u16 brightness;
	622	+ u16 r_gain;
	623	+ u16 g_gain;
	624	+ u16 b_gain;
	625	+ u16 r_offset;
	626	+ u16 g_offset;
	627	+ u16 b_offset;
	628	+ u16 csc_enable;
	629	+};
	630	+
526	631	struct post_csc_coef {
527	632	s32 csc_coef00;
528	633	s32 csc_coef01;
..	..	@@ -582,6 +687,7 @@
582	687	struct vop_reg gate;
583	688	struct vop_reg enable;
584	689	struct vop_reg format;
	690	+ struct vop_reg interlace_read;
585	691	struct vop_reg fmt_10;
586	692	struct vop_reg fmt_yuyv;
587	693	struct vop_reg csc_mode;
..	..	@@ -605,6 +711,17 @@
605	711	struct vop_reg global_alpha_val;
606	712	struct vop_reg color_key;
607	713	struct vop_reg color_key_en;
	714	+};
	715	+
	716	+struct vop_win_data {
	717	+ uint32_t base;
	718	+ enum drm_plane_type type;
	719	+ const struct vop_win_phy *phy;
	720	+ const struct vop_win_phy **area;
	721	+ const uint64_t *format_modifiers;
	722	+ const struct vop_csc *csc;
	723	+ unsigned int area_size;
	724	+ u64 feature;
608	725	};
609	726
610	727	struct vop2_cluster_regs {
..	..	@@ -701,7 +818,9 @@
701	818	struct vop_reg pre_scan_htiming;
702	819	struct vop_reg htotal_pw;
703	820	struct vop_reg hact_st_end;
704		- struct vop_reg vtotal_pw;
	821	+ struct vop_reg dsp_vtotal;
	822	+ struct vop_reg sw_dsp_vtotal_imd;
	823	+ struct vop_reg dsp_vs_end;
705	824	struct vop_reg vact_st_end;
706	825	struct vop_reg vact_st_end_f1;
707	826	struct vop_reg vs_st_end_f1;
..	..	@@ -719,8 +838,8 @@
719	838
720	839	struct vop_reg core_dclk_div;
721	840	struct vop_reg p2i_en;
722		- struct vop_reg mipi_dual_en;
723		- struct vop_reg mipi_dual_channel_swap;
	841	+ struct vop_reg dual_channel_en;
	842	+ struct vop_reg dual_channel_swap;
724	843	struct vop_reg dsp_lut_en;
725	844
726	845	struct vop_reg dclk_div2;
..	..	@@ -783,11 +902,37 @@
783	902	struct vop_reg cubic_lut_update_en;
784	903	struct vop_reg cubic_lut_mst;
785	904
	905	+ /* cru */
	906	+ struct vop_reg dclk_core_div;
	907	+ struct vop_reg dclk_out_div;
	908	+ struct vop_reg dclk_src_sel;
	909	+
	910	+ struct vop_reg splice_en;
	911	+
786	912	struct vop_reg edpi_wms_hold_en;
787	913	struct vop_reg edpi_te_en;
788	914	struct vop_reg edpi_wms_fs;
789	915	struct vop_reg gamma_update_en;
790	916	struct vop_reg lut_dma_rid;
	917	+
	918	+ /* MCU output */
	919	+ struct vop_reg mcu_pix_total;
	920	+ struct vop_reg mcu_cs_pst;
	921	+ struct vop_reg mcu_cs_pend;
	922	+ struct vop_reg mcu_rw_pst;
	923	+ struct vop_reg mcu_rw_pend;
	924	+ struct vop_reg mcu_clk_sel;
	925	+ struct vop_reg mcu_hold_mode;
	926	+ struct vop_reg mcu_frame_st;
	927	+ struct vop_reg mcu_rs;
	928	+ struct vop_reg mcu_bypass;
	929	+ struct vop_reg mcu_type;
	930	+ struct vop_reg mcu_rw_bypass_port;
	931	+
	932	+ /* for DCF */
	933	+ struct vop_reg line_flag_or_en;
	934	+ struct vop_reg dsp_hold_or_en;
	935	+ struct vop_reg almost_full_or_en;
791	936
792	937	/* CSC */
793	938	struct vop_reg acm_bypass_en;
..	..	@@ -807,6 +952,58 @@
807	952	struct vop_reg csc_offset0;
808	953	struct vop_reg csc_offset1;
809	954	struct vop_reg csc_offset2;
	955	+
	956	+ /* color bar */
	957	+ struct vop_reg color_bar_en;
	958	+ struct vop_reg color_bar_mode;
	959	+};
	960	+
	961	+struct vop2_power_domain_regs {
	962	+ struct vop_reg pd;
	963	+ struct vop_reg status;
	964	+ struct vop_reg bisr_en_status;
	965	+ struct vop_reg pmu_status;
	966	+};
	967	+
	968	+struct vop2_dsc_regs {
	969	+ /* DSC SYS CTRL */
	970	+ struct vop_reg dsc_port_sel;
	971	+ struct vop_reg dsc_man_mode;
	972	+ struct vop_reg dsc_interface_mode;
	973	+ struct vop_reg dsc_pixel_num;
	974	+ struct vop_reg dsc_pxl_clk_div;
	975	+ struct vop_reg dsc_cds_clk_div;
	976	+ struct vop_reg dsc_txp_clk_div;
	977	+ struct vop_reg dsc_init_dly_mode;
	978	+ struct vop_reg dsc_scan_en;
	979	+ struct vop_reg dsc_halt_en;
	980	+ struct vop_reg rst_deassert;
	981	+ struct vop_reg dsc_flush;
	982	+ struct vop_reg dsc_cfg_done;
	983	+ struct vop_reg dsc_init_dly_num;
	984	+ struct vop_reg scan_timing_para_imd_en;
	985	+ struct vop_reg dsc_htotal_pw;
	986	+ struct vop_reg dsc_hact_st_end;
	987	+ struct vop_reg dsc_vtotal;
	988	+ struct vop_reg dsc_vs_end;
	989	+ struct vop_reg dsc_vact_st_end;
	990	+ struct vop_reg dsc_error_status;
	991	+
	992	+ /* DSC encoder */
	993	+ struct vop_reg dsc_pps0_3;
	994	+ struct vop_reg dsc_en;
	995	+ struct vop_reg dsc_rbit;
	996	+ struct vop_reg dsc_rbyt;
	997	+ struct vop_reg dsc_flal;
	998	+ struct vop_reg dsc_mer;
	999	+ struct vop_reg dsc_epb;
	1000	+ struct vop_reg dsc_epl;
	1001	+ struct vop_reg dsc_nslc;
	1002	+ struct vop_reg dsc_sbo;
	1003	+ struct vop_reg dsc_ifep;
	1004	+ struct vop_reg dsc_pps_upd;
	1005	+ struct vop_reg dsc_status;
	1006	+ struct vop_reg dsc_ecw;
810	1007	};
811	1008
812	1009	struct vop2_wb_regs {
..	..	@@ -825,19 +1022,39 @@
825	1022	struct vop_reg axi_uv_id;
826	1023	};
827	1024
828		-struct vop_win_data {
829		- uint32_t base;
830		- enum drm_plane_type type;
831		- const struct vop_win_phy *phy;
832		- const struct vop_win_phy **area;
833		- const struct vop_csc *csc;
834		- unsigned int area_size;
835		- u64 feature;
	1025	+struct vop2_power_domain_data {
	1026	+ uint8_t id;
	1027	+ uint8_t parent_id;
	1028	+ /*
	1029	+ * @module_id_mask: module id of which module this power domain is belongs to.
	1030	+ * PD_CLUSTER0,1,2,3 only belongs to CLUSTER0/1/2/3, PD_Esmart0 shared by Esmart1/2/3
	1031	+ */
	1032	+ uint32_t module_id_mask;
	1033	+
	1034	+ const struct vop2_power_domain_regs *regs;
	1035	+};
	1036	+
	1037	+/*
	1038	+ * connector interface(RGB/HDMI/eDP/DP/MIPI) data
	1039	+ */
	1040	+struct vop2_connector_if_data {
	1041	+ u32 id;
	1042	+ const char *clk_src_name;
	1043	+ const char *clk_parent_name;
	1044	+ const char *pixclk_name;
	1045	+ const char *dclk_name;
	1046	+ u32 post_proc_div_shift;
	1047	+ u32 if_div_shift;
	1048	+ u32 if_div_yuv420_shift;
	1049	+ u32 bus_div_shift;
	1050	+ u32 pixel_clk_div_shift;
836	1051	};
837	1052
838	1053	struct vop2_win_data {
839	1054	const char *name;
840	1055	uint8_t phys_id;
	1056	+ uint8_t splice_win_id;
	1057	+ uint8_t pd_id;
841	1058	uint8_t axi_id;
842	1059	uint8_t axi_yrgb_id;
843	1060	uint8_t axi_uv_id;
..	..	@@ -875,6 +1092,24 @@
875	1092	const uint8_t dly[VOP2_DLY_MODE_MAX];
876	1093	};
877	1094
	1095	+struct dsc_error_info {
	1096	+ u32 dsc_error_val;
	1097	+ char dsc_error_info[50];
	1098	+};
	1099	+
	1100	+struct vop2_dsc_data {
	1101	+ uint8_t id;
	1102	+ uint8_t pd_id;
	1103	+ uint8_t max_slice_num;
	1104	+ uint8_t max_linebuf_depth; /* used to generate the bitstream */
	1105	+ uint8_t min_bits_per_pixel; /* bit num after encoder compress */
	1106	+ const char *dsc_txp_clk_src_name;
	1107	+ const char *dsc_txp_clk_name;
	1108	+ const char *dsc_pxl_clk_name;
	1109	+ const char *dsc_cds_clk_name;
	1110	+ const struct vop2_dsc_regs *regs;
	1111	+};
	1112	+
878	1113	struct vop2_wb_data {
879	1114	uint32_t nformats;
880	1115	const uint32_t *formats;
..	..	@@ -897,11 +1132,13 @@
897	1132
898	1133	struct vop2_video_port_data {
899	1134	char id;
	1135	+ uint8_t splice_vp_id;
900	1136	uint16_t lut_dma_rid;
901	1137	uint32_t feature;
902	1138	uint64_t soc_id[VOP2_SOC_VARIANT];
903	1139	uint16_t gamma_lut_len;
904	1140	uint16_t cubic_lut_len;
	1141	+ unsigned long dclk_max;
905	1142	struct vop_rect max_output;
906	1143	const u8 pre_scan_max_dly[4];
907	1144	const u8 hdrvivid_dly[10];
..	..	@@ -952,6 +1189,14 @@
952	1189	struct vop_reg grf_dclk_inv;
953	1190	struct vop_reg grf_bt1120_clk_inv;
954	1191	struct vop_reg grf_bt656_clk_inv;
	1192	+ struct vop_reg grf_edp0_en;
	1193	+ struct vop_reg grf_edp1_en;
	1194	+ struct vop_reg grf_hdmi0_en;
	1195	+ struct vop_reg grf_hdmi1_en;
	1196	+ struct vop_reg grf_hdmi0_dsc_en;
	1197	+ struct vop_reg grf_hdmi1_dsc_en;
	1198	+ struct vop_reg grf_hdmi0_pin_pol;
	1199	+ struct vop_reg grf_hdmi1_pin_pol;
955	1200	};
956	1201
957	1202	struct vop_data {
..	..	@@ -969,6 +1214,7 @@
969	1214	struct vop_rect max_output;
970	1215	u64 feature;
971	1216	u64 soc_id;
	1217	+ u8 vop_id;
972	1218	};
973	1219
974	1220	struct vop2_ctrl {
..	..	@@ -976,6 +1222,9 @@
976	1222	struct vop_reg wb_cfg_done;
977	1223	struct vop_reg auto_gating_en;
978	1224	struct vop_reg aclk_pre_auto_gating_en;
	1225	+ struct vop_reg dma_finish_mode;
	1226	+ struct vop_reg axi_dma_finish_and_en;
	1227	+ struct vop_reg wb_dma_finish_and_en;
979	1228	struct vop_reg ovl_cfg_done_port;
980	1229	struct vop_reg ovl_port_mux_cfg_done_imd;
981	1230	struct vop_reg ovl_port_mux_cfg;
..	..	@@ -1015,9 +1264,12 @@
1015	1264	struct vop_reg edp_pin_pol;
1016	1265	struct vop_reg mipi_dclk_pol;
1017	1266	struct vop_reg mipi_pin_pol;
1018		- struct vop_reg dp_dclk_pol;
1019		- struct vop_reg dp_pin_pol;
	1267	+ struct vop_reg dp0_dclk_pol;
	1268	+ struct vop_reg dp0_pin_pol;
	1269	+ struct vop_reg dp1_dclk_pol;
	1270	+ struct vop_reg dp1_pin_pol;
1020	1271
	1272	+ /* This will be reference by win_phy_id */
1021	1273	struct vop_reg win_vp_id[16];
1022	1274	struct vop_reg win_dly[16];
1023	1275
..	..	@@ -1038,10 +1290,25 @@
1038	1290	struct vop_reg lvds_dual_mode;
1039	1291	struct vop_reg lvds_dual_channel_swap;
1040	1292
1041		- struct vop_reg cluster0_src_color_ctrl;
1042		- struct vop_reg cluster0_dst_color_ctrl;
1043		- struct vop_reg cluster0_src_alpha_ctrl;
1044		- struct vop_reg cluster0_dst_alpha_ctrl;
	1293	+ struct vop_reg dp_dual_en;
	1294	+ struct vop_reg edp_dual_en;
	1295	+ struct vop_reg hdmi_dual_en;
	1296	+ struct vop_reg mipi_dual_en;
	1297	+
	1298	+ struct vop_reg hdmi0_dclk_div;
	1299	+ struct vop_reg hdmi0_pixclk_div;
	1300	+ struct vop_reg edp0_dclk_div;
	1301	+ struct vop_reg edp0_pixclk_div;
	1302	+
	1303	+ struct vop_reg hdmi1_dclk_div;
	1304	+ struct vop_reg hdmi1_pixclk_div;
	1305	+ struct vop_reg edp1_dclk_div;
	1306	+ struct vop_reg edp1_pixclk_div;
	1307	+
	1308	+ struct vop_reg mipi0_pixclk_div;
	1309	+ struct vop_reg mipi1_pixclk_div;
	1310	+ struct vop_reg mipi0_ds_mode;
	1311	+ struct vop_reg mipi1_ds_mode;
1045	1312
1046	1313	struct vop_reg src_color_ctrl;
1047	1314	struct vop_reg dst_color_ctrl;
..	..	@@ -1051,6 +1318,7 @@
1051	1318	struct vop_reg bt1120_yc_swap;
1052	1319	struct vop_reg bt656_yc_swap;
1053	1320	struct vop_reg gamma_port_sel;
	1321	+ struct vop_reg pd_off_imd;
1054	1322
1055	1323	struct vop_reg otp_en;
1056	1324	struct vop_reg esmart_lb_mode;
..	..	@@ -1065,6 +1333,12 @@
1065	1333	bool enable_state;
1066	1334	};
1067	1335
	1336	+struct vop2_vp_plane_mask {
	1337	+ u8 primary_plane_id;
	1338	+ u8 attached_layers_nr;
	1339	+ u8 attached_layers[ROCKCHIP_MAX_LAYER];
	1340	+};
	1341	+
1068	1342	/**
1069	1343	* VOP2 data structe
1070	1344	*
..	..	@@ -1074,25 +1348,43 @@
1074	1348	struct vop2_data {
1075	1349	uint32_t version;
1076	1350	uint32_t feature;
	1351	+ uint8_t nr_dscs;
	1352	+ uint8_t nr_dsc_ecw;
	1353	+ uint8_t nr_dsc_buffer_flow;
1077	1354	uint8_t nr_vps;
1078	1355	uint8_t nr_mixers;
1079	1356	uint8_t nr_layers;
1080	1357	uint8_t nr_axi_intr;
1081	1358	uint8_t nr_gammas;
	1359	+ uint8_t nr_conns;
	1360	+ uint8_t nr_pds;
	1361	+ uint8_t nr_mem_pgs;
1082	1362	uint8_t esmart_lb_mode;
	1363	+ bool delayed_pd;
1083	1364	const struct vop_intr *axi_intr;
1084	1365	const struct vop2_ctrl *ctrl;
	1366	+ const struct vop2_dsc_data *dsc;
	1367	+ const struct dsc_error_info *dsc_error_ecw;
	1368	+ const struct dsc_error_info *dsc_error_buffer_flow;
1085	1369	const struct vop2_win_data *win;
1086	1370	const struct vop2_video_port_data *vp;
	1371	+ const struct vop2_connector_if_data *conn;
1087	1372	const struct vop2_wb_data *wb;
1088	1373	const struct vop2_layer_data *layer;
	1374	+ const struct vop2_power_domain_data *pd;
	1375	+ const struct vop2_power_domain_data *mem_pg;
1089	1376	const struct vop_csc_table *csc_table;
1090	1377	const struct vop_hdr_table *hdr_table;
1091		- const struct vop_grf_ctrl *grf_ctrl;
	1378	+ const struct vop_grf_ctrl *sys_grf;
	1379	+ const struct vop_grf_ctrl *grf;
	1380	+ const struct vop_grf_ctrl *vo0_grf;
	1381	+ const struct vop_grf_ctrl *vo1_grf;
1092	1382	const struct vop_dump_regs *dump_regs;
1093	1383	uint32_t dump_regs_size;
1094	1384	struct vop_rect max_input;
1095	1385	struct vop_rect max_output;
	1386	+ const struct vop2_vp_plane_mask *plane_mask;
	1387	+ uint32_t plane_mask_base;
1096	1388
1097	1389	unsigned int win_size;
1098	1390	};
..	..	@@ -1169,6 +1461,7 @@
1169	1461	#define ROCKCHIP_OUT_MODE_P565 2
1170	1462	#define ROCKCHIP_OUT_MODE_BT656 5
1171	1463	#define ROCKCHIP_OUT_MODE_S888 8
	1464	+#define ROCKCHIP_OUT_MODE_YUV422 9
1172	1465	#define ROCKCHIP_OUT_MODE_S888_DUMMY 12
1173	1466	#define ROCKCHIP_OUT_MODE_YUV420 14
1174	1467	/* for use special outface */
..	..	@@ -1285,6 +1578,7 @@
1285	1578	DCLK_INVERT = 3
1286	1579	};
1287	1580
	1581	+
1288	1582	#define FRAC_16_16(mult, div) (((mult) << 16) / (div))
1289	1583	#define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12
1290	1584	#define SCL_MAX_VSKIPLINES 4
..	..	@@ -1369,7 +1663,6 @@
1369	1663	return y1 + (y2 - y1) * (x - x1) / (x2 - x1);
1370	1664	}
1371	1665
1372		-extern void vop2_standby(struct drm_crtc *crtc, bool standby);
1373	1666	extern const struct component_ops vop_component_ops;
1374	1667	extern const struct component_ops vop2_component_ops;
1375	1668	#endif /* _ROCKCHIP_DRM_VOP_H */