add dts config

hc

2023-12-06 08f87f769b595151be1afeff53e144f543faa614

 kernel/drivers/gpu/drm/nouveau/dispnv50/ovly907e.c
..
..
@@ -22,49 +22,75 @@
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 #include "ovly.h"
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 #include "atom.h"
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24
 
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-static void
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+#include <nvif/push507c.h>
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+
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+#include <nvhw/class/cl907e.h>
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+
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+static int
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 ovly907e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
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 {
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-	u32 *push;
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-	if ((push = evo_wait(&wndw->wndw, 12))) {
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-		evo_mthd(push, 0x0084, 1);
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-		evo_data(push, asyw->image.interval << 4);
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-		evo_mthd(push, 0x00c0, 1);
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-		evo_data(push, asyw->image.handle[0]);
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-		evo_mthd(push, 0x0100, 1);
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-		evo_data(push, 0x00000002);
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-		evo_mthd(push, 0x0400, 1);
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-		evo_data(push, asyw->image.offset[0] >> 8);
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-		evo_mthd(push, 0x0408, 3);
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-		evo_data(push, asyw->image.h << 16 | asyw->image.w);
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-		evo_data(push, asyw->image.layout << 24 |
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-			       (asyw->image.pitch[0] >> 8) << 8 |
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-			       asyw->image.blocks[0] << 8 |
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-			       asyw->image.blockh);
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-		evo_data(push, asyw->image.format << 8 |
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-			       asyw->image.colorspace);
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-		evo_kick(push, &wndw->wndw);
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-	}
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+	struct nvif_push *push = wndw->wndw.push;
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+	int ret;
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+
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+	if ((ret = PUSH_WAIT(push, 12)))
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+		return ret;
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+
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+	PUSH_MTHD(push, NV907E, SET_PRESENT_CONTROL,
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+		  NVDEF(NV907E, SET_PRESENT_CONTROL, BEGIN_MODE, ASAP) |
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+		  NVVAL(NV907E, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, asyw->image.interval));
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+
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+	PUSH_MTHD(push, NV907E, SET_CONTEXT_DMA_ISO, asyw->image.handle[0]);
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+
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+	PUSH_MTHD(push, NV907E, SET_COMPOSITION_CONTROL,
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+		  NVDEF(NV907E, SET_COMPOSITION_CONTROL, MODE, OPAQUE));
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+
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+	PUSH_MTHD(push, NV907E, SURFACE_SET_OFFSET, asyw->image.offset[0] >> 8);
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+
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+	PUSH_MTHD(push, NV907E, SURFACE_SET_SIZE,
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+		  NVVAL(NV907E, SURFACE_SET_SIZE, WIDTH, asyw->image.w) |
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+		  NVVAL(NV907E, SURFACE_SET_SIZE, HEIGHT, asyw->image.h),
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+
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+				SURFACE_SET_STORAGE,
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+		  NVVAL(NV907E, SURFACE_SET_STORAGE, BLOCK_HEIGHT, asyw->image.blockh) |
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+		  NVVAL(NV907E, SURFACE_SET_STORAGE, PITCH, (asyw->image.pitch[0] >> 8)) |
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+		  NVVAL(NV907E, SURFACE_SET_STORAGE, PITCH, asyw->image.blocks[0]) |
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+		  NVVAL(NV907E, SURFACE_SET_STORAGE, MEMORY_LAYOUT, asyw->image.layout),
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+
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+				SURFACE_SET_PARAMS,
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+		  NVVAL(NV907E, SURFACE_SET_PARAMS, FORMAT, asyw->image.format) |
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+		  NVVAL(NV907E, SURFACE_SET_PARAMS, COLOR_SPACE, asyw->image.colorspace));
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+	return 0;
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 }
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64
 
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 const struct nv50_wndw_func
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 ovly907e = {
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 	.acquire = ovly507e_acquire,
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 	.release = ovly507e_release,
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-	.ntfy_set = ovly507e_ntfy_set,
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-	.ntfy_clr = ovly507e_ntfy_clr,
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+	.ntfy_set = base507c_ntfy_set,
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+	.ntfy_clr = base507c_ntfy_clr,
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 	.ntfy_reset = ovly827e_ntfy_reset,
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 	.ntfy_wait_begun = ovly827e_ntfy_wait_begun,
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 	.image_set = ovly907e_image_set,
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-	.image_clr = ovly507e_image_clr,
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+	.image_clr = base507c_image_clr,
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 	.scale_set = ovly507e_scale_set,
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-	.update = ovly507e_update,
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+	.update = base507c_update,
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+};
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+
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+static const u32
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+ovly907e_format[] = {
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+	DRM_FORMAT_YUYV,
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+	DRM_FORMAT_UYVY,
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+	DRM_FORMAT_XRGB8888,
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+	DRM_FORMAT_XRGB1555,
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+	DRM_FORMAT_XBGR2101010,
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+	DRM_FORMAT_XBGR16161616F,
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+	0
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 };
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 int
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 ovly907e_new(struct nouveau_drm *drm, int head, s32 oclass,
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 	     struct nv50_wndw **pwndw)
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 {
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-	return ovly507e_new_(&ovly907e, ovly827e_format, drm, head, oclass,
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+	return ovly507e_new_(&ovly907e, ovly907e_format, drm, head, oclass,
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 			     0x00000004 << (head * 4), pwndw);
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 }