add dts config

hc

2023-12-06 08f87f769b595151be1afeff53e144f543faa614

 kernel/drivers/gpu/drm/nouveau/dispnv50/head907d.c
..
..
@@ -19,247 +19,396 @@
19
19
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
20
  * OTHER DEALINGS IN THE SOFTWARE.
21
21
  */
22
+#include <drm/drm_connector.h>
23
+#include <drm/drm_mode_config.h>
24
+#include <drm/drm_vblank.h>
25
+#include "nouveau_drv.h"
26
+#include "nouveau_bios.h"
27
+#include "nouveau_connector.h"
22
28
 #include "head.h"
23
29
 #include "core.h"
30
+#include "crc.h"
24
31
 
25
-void
32
+#include <nvif/push507c.h>
33
+
34
+#include <nvhw/class/cl907d.h>
35
+
36
+int
26
37
 head907d_or(struct nv50_head *head, struct nv50_head_atom *asyh)
27
38
 {
28
-	struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan;
29
-	u32 *push;
30
-	if ((push = evo_wait(core, 3))) {
31
-		evo_mthd(push, 0x0404 + (head->base.index * 0x300), 2);
32
-		evo_data(push, 0x00000001 | asyh->or.depth  << 6 |
33
-					    asyh->or.nvsync << 4 |
34
-					    asyh->or.nhsync << 3);
35
-		evo_data(push, 0x31ec6000 | head->base.index << 25 |
36
-					    asyh->mode.interlace);
37
-		evo_kick(push, core);
38
-	}
39
+	struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
40
+	const int i = head->base.index;
41
+	int ret;
42
+
43
+	if ((ret = PUSH_WAIT(push, 3)))
44
+		return ret;
45
+
46
+	PUSH_MTHD(push, NV907D, HEAD_SET_CONTROL_OUTPUT_RESOURCE(i),
47
+		  NVVAL(NV907D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, CRC_MODE, asyh->or.crc_raster) |
48
+		  NVVAL(NV907D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, HSYNC_POLARITY, asyh->or.nhsync) |
49
+		  NVVAL(NV907D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, VSYNC_POLARITY, asyh->or.nvsync) |
50
+		  NVVAL(NV907D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, PIXEL_DEPTH, asyh->or.depth),
51
+
52
+				HEAD_SET_CONTROL(i), 0x31ec6000 | head->base.index << 25 |
53
+		  NVVAL(NV907D, HEAD_SET_CONTROL, STRUCTURE, asyh->mode.interlace));
54
+	return 0;
39
55
 }
40
56
 
41
-void
57
+int
42
58
 head907d_procamp(struct nv50_head *head, struct nv50_head_atom *asyh)
43
59
 {
44
-	struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan;
45
-	u32 *push;
46
-	if ((push = evo_wait(core, 2))) {
47
-		evo_mthd(push, 0x0498 + (head->base.index * 0x300), 1);
48
-		evo_data(push, asyh->procamp.sat.sin << 20 |
49
-			       asyh->procamp.sat.cos << 8);
50
-		evo_kick(push, core);
51
-	}
60
+	struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
61
+	const int i = head->base.index;
62
+	int ret;
63
+
64
+	if ((ret = PUSH_WAIT(push, 2)))
65
+		return ret;
66
+
67
+	PUSH_MTHD(push, NV907D, HEAD_SET_PROCAMP(i),
68
+		  NVDEF(NV907D, HEAD_SET_PROCAMP, COLOR_SPACE, RGB) |
69
+		  NVDEF(NV907D, HEAD_SET_PROCAMP, CHROMA_LPF, AUTO) |
70
+		  NVVAL(NV907D, HEAD_SET_PROCAMP, SAT_COS, asyh->procamp.sat.cos) |
71
+		  NVVAL(NV907D, HEAD_SET_PROCAMP, SAT_SINE, asyh->procamp.sat.sin) |
72
+		  NVDEF(NV907D, HEAD_SET_PROCAMP, DYNAMIC_RANGE, VESA) |
73
+		  NVDEF(NV907D, HEAD_SET_PROCAMP, RANGE_COMPRESSION, DISABLE));
74
+	return 0;
52
75
 }
53
76
 
54
-static void
77
+static int
55
78
 head907d_dither(struct nv50_head *head, struct nv50_head_atom *asyh)
56
79
 {
57
-	struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan;
58
-	u32 *push;
59
-	if ((push = evo_wait(core, 2))) {
60
-		evo_mthd(push, 0x0490 + (head->base.index * 0x0300), 1);
61
-		evo_data(push, asyh->dither.mode << 3 |
62
-			       asyh->dither.bits << 1 |
63
-			       asyh->dither.enable);
64
-		evo_kick(push, core);
65
-	}
80
+	struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
81
+	const int i = head->base.index;
82
+	int ret;
83
+
84
+	if ((ret = PUSH_WAIT(push, 2)))
85
+		return ret;
86
+
87
+	PUSH_MTHD(push, NV907D, HEAD_SET_DITHER_CONTROL(i),
88
+		  NVVAL(NV907D, HEAD_SET_DITHER_CONTROL, ENABLE, asyh->dither.enable) |
89
+		  NVVAL(NV907D, HEAD_SET_DITHER_CONTROL, BITS, asyh->dither.bits) |
90
+		  NVVAL(NV907D, HEAD_SET_DITHER_CONTROL, MODE, asyh->dither.mode) |
91
+		  NVVAL(NV907D, HEAD_SET_DITHER_CONTROL, PHASE, 0));
92
+	return 0;
66
93
 }
67
94
 
68
-void
95
+int
69
96
 head907d_ovly(struct nv50_head *head, struct nv50_head_atom *asyh)
70
97
 {
71
-	struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan;
98
+	struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
99
+	const int i = head->base.index;
72
100
 	u32 bounds = 0;
73
-	u32 *push;
101
+	int ret;
74
102
 
75
103
 	if (asyh->ovly.cpp) {
76
104
 		switch (asyh->ovly.cpp) {
77
-		case 8: bounds |= 0x00000500; break;
78
-		case 4: bounds |= 0x00000300; break;
79
-		case 2: bounds |= 0x00000100; break;
105
+		case 8: bounds |= NVDEF(NV907D, HEAD_SET_OVERLAY_USAGE_BOUNDS, PIXEL_DEPTH, BPP_64); break;
106
+		case 4: bounds |= NVDEF(NV907D, HEAD_SET_OVERLAY_USAGE_BOUNDS, PIXEL_DEPTH, BPP_32); break;
107
+		case 2: bounds |= NVDEF(NV907D, HEAD_SET_OVERLAY_USAGE_BOUNDS, PIXEL_DEPTH, BPP_16); break;
80
108
 		default:
81
109
 			WARN_ON(1);
82
110
 			break;
83
111
 		}
84
-		bounds |= 0x00000001;
112
+		bounds |= NVDEF(NV907D, HEAD_SET_OVERLAY_USAGE_BOUNDS, USABLE, TRUE);
85
113
 	} else {
86
-		bounds |= 0x00000100;
114
+		bounds |= NVDEF(NV907D, HEAD_SET_OVERLAY_USAGE_BOUNDS, PIXEL_DEPTH, BPP_16);
87
115
 	}
88
116
 
89
-	if ((push = evo_wait(core, 2))) {
90
-		evo_mthd(push, 0x04d4 + head->base.index * 0x300, 1);
91
-		evo_data(push, bounds);
92
-		evo_kick(push, core);
93
-	}
117
+	if ((ret = PUSH_WAIT(push, 2)))
118
+		return ret;
119
+
120
+	PUSH_MTHD(push, NV907D, HEAD_SET_OVERLAY_USAGE_BOUNDS(i), bounds);
121
+	return 0;
94
122
 }
95
123
 
96
-static void
124
+static int
97
125
 head907d_base(struct nv50_head *head, struct nv50_head_atom *asyh)
98
126
 {
99
-	struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan;
127
+	struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
128
+	const int i = head->base.index;
100
129
 	u32 bounds = 0;
101
-	u32 *push;
130
+	int ret;
102
131
 
103
132
 	if (asyh->base.cpp) {
104
133
 		switch (asyh->base.cpp) {
105
-		case 8: bounds |= 0x00000500; break;
106
-		case 4: bounds |= 0x00000300; break;
107
-		case 2: bounds |= 0x00000100; break;
108
-		case 1: bounds |= 0x00000000; break;
134
+		case 8: bounds |= NVDEF(NV907D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_64); break;
135
+		case 4: bounds |= NVDEF(NV907D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_32); break;
136
+		case 2: bounds |= NVDEF(NV907D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_16); break;
137
+		case 1: bounds |= NVDEF(NV907D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_8); break;
109
138
 		default:
110
139
 			WARN_ON(1);
111
140
 			break;
112
141
 		}
113
-		bounds |= 0x00000001;
142
+		bounds |= NVDEF(NV907D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, USABLE, TRUE);
114
143
 	}
115
144
 
116
-	if ((push = evo_wait(core, 2))) {
117
-		evo_mthd(push, 0x04d0 + head->base.index * 0x300, 1);
118
-		evo_data(push, bounds);
119
-		evo_kick(push, core);
120
-	}
145
+	if ((ret = PUSH_WAIT(push, 2)))
146
+		return ret;
147
+
148
+	PUSH_MTHD(push, NV907D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(i), bounds);
149
+	return 0;
121
150
 }
122
151
 
123
-void
152
+int
124
153
 head907d_curs_clr(struct nv50_head *head)
125
154
 {
126
-	struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan;
127
-	u32 *push;
128
-	if ((push = evo_wait(core, 4))) {
129
-		evo_mthd(push, 0x0480 + head->base.index * 0x300, 1);
130
-		evo_data(push, 0x05000000);
131
-		evo_mthd(push, 0x048c + head->base.index * 0x300, 1);
132
-		evo_data(push, 0x00000000);
133
-		evo_kick(push, core);
134
-	}
155
+	struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
156
+	const int i = head->base.index;
157
+	int ret;
158
+
159
+	if ((ret = PUSH_WAIT(push, 4)))
160
+		return ret;
161
+
162
+	PUSH_MTHD(push, NV907D, HEAD_SET_CONTROL_CURSOR(i),
163
+		  NVDEF(NV907D, HEAD_SET_CONTROL_CURSOR, ENABLE, DISABLE) |
164
+		  NVDEF(NV907D, HEAD_SET_CONTROL_CURSOR, FORMAT, A8R8G8B8) |
165
+		  NVDEF(NV907D, HEAD_SET_CONTROL_CURSOR, SIZE, W64_H64));
166
+
167
+	PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CURSOR(i), 0x00000000);
168
+	return 0;
135
169
 }
136
170
 
137
-void
171
+int
138
172
 head907d_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh)
139
173
 {
140
-	struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan;
141
-	u32 *push;
142
-	if ((push = evo_wait(core, 5))) {
143
-		evo_mthd(push, 0x0480 + head->base.index * 0x300, 2);
144
-		evo_data(push, 0x80000000 | asyh->curs.layout << 26 |
145
-					    asyh->curs.format << 24);
146
-		evo_data(push, asyh->curs.offset >> 8);
147
-		evo_mthd(push, 0x048c + head->base.index * 0x300, 1);
148
-		evo_data(push, asyh->curs.handle);
149
-		evo_kick(push, core);
150
-	}
174
+	struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
175
+	const int i = head->base.index;
176
+	int ret;
177
+
178
+	if ((ret = PUSH_WAIT(push, 5)))
179
+		return ret;
180
+
181
+	PUSH_MTHD(push, NV907D, HEAD_SET_CONTROL_CURSOR(i),
182
+		  NVDEF(NV907D, HEAD_SET_CONTROL_CURSOR, ENABLE, ENABLE) |
183
+		  NVVAL(NV907D, HEAD_SET_CONTROL_CURSOR, FORMAT, asyh->curs.format) |
184
+		  NVVAL(NV907D, HEAD_SET_CONTROL_CURSOR, SIZE, asyh->curs.layout) |
185
+		  NVVAL(NV907D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_X, 0) |
186
+		  NVVAL(NV907D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_Y, 0) |
187
+		  NVDEF(NV907D, HEAD_SET_CONTROL_CURSOR, COMPOSITION, ALPHA_BLEND),
188
+
189
+				HEAD_SET_OFFSET_CURSOR(i), asyh->curs.offset >> 8);
190
+
191
+	PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CURSOR(i), asyh->curs.handle);
192
+	return 0;
151
193
 }
152
194
 
153
-void
195
+int
154
196
 head907d_core_clr(struct nv50_head *head)
155
197
 {
156
-	struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan;
157
-	u32 *push;
158
-	if ((push = evo_wait(core, 2))) {
159
-		evo_mthd(push, 0x0474 + head->base.index * 0x300, 1);
160
-		evo_data(push, 0x00000000);
161
-		evo_kick(push, core);
162
-	}
198
+	struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
199
+	const int i = head->base.index;
200
+	int ret;
201
+
202
+	if ((ret = PUSH_WAIT(push, 2)))
203
+		return ret;
204
+
205
+	PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMAS_ISO(i), 0x00000000);
206
+	return 0;
163
207
 }
164
208
 
165
-void
209
+int
166
210
 head907d_core_set(struct nv50_head *head, struct nv50_head_atom *asyh)
167
211
 {
168
-	struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan;
169
-	u32 *push;
170
-	if ((push = evo_wait(core, 9))) {
171
-		evo_mthd(push, 0x0460 + head->base.index * 0x300, 1);
172
-		evo_data(push, asyh->core.offset >> 8);
173
-		evo_mthd(push, 0x0468 + head->base.index * 0x300, 4);
174
-		evo_data(push, asyh->core.h << 16 | asyh->core.w);
175
-		evo_data(push, asyh->core.layout << 24 |
176
-			       (asyh->core.pitch >> 8) << 8 |
177
-			       asyh->core.blocks << 8 |
178
-			       asyh->core.blockh);
179
-		evo_data(push, asyh->core.format << 8);
180
-		evo_data(push, asyh->core.handle);
181
-		evo_mthd(push, 0x04b0 + head->base.index * 0x300, 1);
182
-		evo_data(push, asyh->core.y << 16 | asyh->core.x);
183
-		evo_kick(push, core);
184
-	}
212
+	struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
213
+	const int i = head->base.index;
214
+	int ret;
215
+
216
+	if ((ret = PUSH_WAIT(push, 9)))
217
+		return ret;
218
+
219
+	PUSH_MTHD(push, NV907D, HEAD_SET_OFFSET(i),
220
+		  NVVAL(NV907D, HEAD_SET_OFFSET, ORIGIN, asyh->core.offset >> 8));
221
+
222
+	PUSH_MTHD(push, NV907D, HEAD_SET_SIZE(i),
223
+		  NVVAL(NV907D, HEAD_SET_SIZE, WIDTH, asyh->core.w) |
224
+		  NVVAL(NV907D, HEAD_SET_SIZE, HEIGHT, asyh->core.h),
225
+
226
+				HEAD_SET_STORAGE(i),
227
+		  NVVAL(NV907D, HEAD_SET_STORAGE, BLOCK_HEIGHT, asyh->core.blockh) |
228
+		  NVVAL(NV907D, HEAD_SET_STORAGE, PITCH, asyh->core.pitch >> 8) |
229
+		  NVVAL(NV907D, HEAD_SET_STORAGE, PITCH, asyh->core.blocks) |
230
+		  NVVAL(NV907D, HEAD_SET_STORAGE, MEMORY_LAYOUT, asyh->core.layout),
231
+
232
+				HEAD_SET_PARAMS(i),
233
+		  NVVAL(NV907D, HEAD_SET_PARAMS, FORMAT, asyh->core.format) |
234
+		  NVDEF(NV907D, HEAD_SET_PARAMS, SUPER_SAMPLE, X1_AA) |
235
+		  NVDEF(NV907D, HEAD_SET_PARAMS, GAMMA, LINEAR),
236
+
237
+				HEAD_SET_CONTEXT_DMAS_ISO(i),
238
+		  NVVAL(NV907D, HEAD_SET_CONTEXT_DMAS_ISO, HANDLE, asyh->core.handle));
239
+
240
+	PUSH_MTHD(push, NV907D, HEAD_SET_VIEWPORT_POINT_IN(i),
241
+		  NVVAL(NV907D, HEAD_SET_VIEWPORT_POINT_IN, X, asyh->core.x) |
242
+		  NVVAL(NV907D, HEAD_SET_VIEWPORT_POINT_IN, Y, asyh->core.y));
243
+	return 0;
185
244
 }
186
245
 
187
-void
246
+int
188
247
 head907d_olut_clr(struct nv50_head *head)
189
248
 {
190
-	struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan;
191
-	u32 *push;
192
-	if ((push = evo_wait(core, 4))) {
193
-		evo_mthd(push, 0x0448 + (head->base.index * 0x300), 1);
194
-		evo_data(push, 0x00000000);
195
-		evo_mthd(push, 0x045c + (head->base.index * 0x300), 1);
196
-		evo_data(push, 0x00000000);
197
-		evo_kick(push, core);
198
-	}
249
+	struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
250
+	const int i = head->base.index;
251
+	int ret;
252
+
253
+	if ((ret = PUSH_WAIT(push, 4)))
254
+		return ret;
255
+
256
+	PUSH_MTHD(push, NV907D, HEAD_SET_OUTPUT_LUT_LO(i),
257
+		  NVDEF(NV907D, HEAD_SET_OUTPUT_LUT_LO, ENABLE, DISABLE));
258
+
259
+	PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_LUT(i), 0x00000000);
260
+	return 0;
199
261
 }
200
262
 
201
-void
263
+int
202
264
 head907d_olut_set(struct nv50_head *head, struct nv50_head_atom *asyh)
203
265
 {
204
-	struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan;
205
-	u32 *push;
206
-	if ((push = evo_wait(core, 5))) {
207
-		evo_mthd(push, 0x0448 + (head->base.index * 0x300), 2);
208
-		evo_data(push, 0x80000000 | asyh->olut.mode << 24);
209
-		evo_data(push, asyh->olut.offset >> 8);
210
-		evo_mthd(push, 0x045c + (head->base.index * 0x300), 1);
211
-		evo_data(push, asyh->olut.handle);
212
-		evo_kick(push, core);
213
-	}
266
+	struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
267
+	const int i = head->base.index;
268
+	int ret;
269
+
270
+	if ((ret = PUSH_WAIT(push, 5)))
271
+		return ret;
272
+
273
+	PUSH_MTHD(push, NV907D, HEAD_SET_OUTPUT_LUT_LO(i),
274
+		  NVDEF(NV907D, HEAD_SET_OUTPUT_LUT_LO, ENABLE, ENABLE) |
275
+		  NVVAL(NV907D, HEAD_SET_OUTPUT_LUT_LO, MODE, asyh->olut.mode) |
276
+		  NVDEF(NV907D, HEAD_SET_OUTPUT_LUT_LO, NEVER_YIELD_TO_BASE, DISABLE),
277
+
278
+				HEAD_SET_OUTPUT_LUT_HI(i),
279
+		  NVVAL(NV907D, HEAD_SET_OUTPUT_LUT_HI, ORIGIN, asyh->olut.offset >> 8));
280
+
281
+	PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_LUT(i), asyh->olut.handle);
282
+	return 0;
214
283
 }
215
284
 
216
285
 void
217
-head907d_olut(struct nv50_head *head, struct nv50_head_atom *asyh)
286
+head907d_olut_load(struct drm_color_lut *in, int size, void __iomem *mem)
218
287
 {
219
-	asyh->olut.mode = 7;
288
+	for (; size--; in++, mem += 8) {
289
+		writew(drm_color_lut_extract(in->  red, 14) + 0x6000, mem + 0);
290
+		writew(drm_color_lut_extract(in->green, 14) + 0x6000, mem + 2);
291
+		writew(drm_color_lut_extract(in-> blue, 14) + 0x6000, mem + 4);
292
+	}
293
+
294
+	/* INTERPOLATE modes require a "next" entry to interpolate with,
295
+	 * so we replicate the last entry to deal with this for now.
296
+	 */
297
+	writew(readw(mem - 8), mem + 0);
298
+	writew(readw(mem - 6), mem + 2);
299
+	writew(readw(mem - 4), mem + 4);
220
300
 }
221
301
 
222
-void
302
+bool
303
+head907d_olut(struct nv50_head *head, struct nv50_head_atom *asyh, int size)
304
+{
305
+	if (size != 256 && size != 1024)
306
+		return false;
307
+
308
+	if (size == 1024)
309
+		asyh->olut.mode = NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE;
310
+	else
311
+		asyh->olut.mode = NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE;
312
+
313
+	asyh->olut.load = head907d_olut_load;
314
+	return true;
315
+}
316
+
317
+int
223
318
 head907d_mode(struct nv50_head *head, struct nv50_head_atom *asyh)
224
319
 {
225
-	struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan;
320
+	struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
226
321
 	struct nv50_head_mode *m = &asyh->mode;
227
-	u32 *push;
228
-	if ((push = evo_wait(core, 14))) {
229
-		evo_mthd(push, 0x0410 + (head->base.index * 0x300), 6);
230
-		evo_data(push, 0x00000000);
231
-		evo_data(push, m->v.active  << 16 | m->h.active );
232
-		evo_data(push, m->v.synce   << 16 | m->h.synce  );
233
-		evo_data(push, m->v.blanke  << 16 | m->h.blanke );
234
-		evo_data(push, m->v.blanks  << 16 | m->h.blanks );
235
-		evo_data(push, m->v.blank2e << 16 | m->v.blank2s);
236
-		evo_mthd(push, 0x042c + (head->base.index * 0x300), 2);
237
-		evo_data(push, 0x00000000); /* ??? */
238
-		evo_data(push, 0xffffff00);
239
-		evo_mthd(push, 0x0450 + (head->base.index * 0x300), 3);
240
-		evo_data(push, m->clock * 1000);
241
-		evo_data(push, 0x00200000); /* ??? */
242
-		evo_data(push, m->clock * 1000);
243
-		evo_kick(push, core);
244
-	}
322
+	const int i = head->base.index;
323
+	int ret;
324
+
325
+	if ((ret = PUSH_WAIT(push, 14)))
326
+		return ret;
327
+
328
+	PUSH_MTHD(push, NV907D, HEAD_SET_OVERSCAN_COLOR(i),
329
+		  NVVAL(NV907D, HEAD_SET_OVERSCAN_COLOR, RED, 0) |
330
+		  NVVAL(NV907D, HEAD_SET_OVERSCAN_COLOR, GRN, 0) |
331
+		  NVVAL(NV907D, HEAD_SET_OVERSCAN_COLOR, BLU, 0),
332
+
333
+				HEAD_SET_RASTER_SIZE(i),
334
+		  NVVAL(NV907D, HEAD_SET_RASTER_SIZE, WIDTH, m->h.active) |
335
+		  NVVAL(NV907D, HEAD_SET_RASTER_SIZE, HEIGHT, m->v.active),
336
+
337
+				HEAD_SET_RASTER_SYNC_END(i),
338
+		  NVVAL(NV907D, HEAD_SET_RASTER_SYNC_END, X, m->h.synce) |
339
+		  NVVAL(NV907D, HEAD_SET_RASTER_SYNC_END, Y, m->v.synce),
340
+
341
+				HEAD_SET_RASTER_BLANK_END(i),
342
+		  NVVAL(NV907D, HEAD_SET_RASTER_BLANK_END, X, m->h.blanke) |
343
+		  NVVAL(NV907D, HEAD_SET_RASTER_BLANK_END, Y, m->v.blanke),
344
+
345
+				HEAD_SET_RASTER_BLANK_START(i),
346
+		  NVVAL(NV907D, HEAD_SET_RASTER_BLANK_START, X, m->h.blanks) |
347
+		  NVVAL(NV907D, HEAD_SET_RASTER_BLANK_START, Y, m->v.blanks),
348
+
349
+				HEAD_SET_RASTER_VERT_BLANK2(i),
350
+		  NVVAL(NV907D, HEAD_SET_RASTER_VERT_BLANK2, YSTART, m->v.blank2s) |
351
+		  NVVAL(NV907D, HEAD_SET_RASTER_VERT_BLANK2, YEND, m->v.blank2e));
352
+
353
+	PUSH_MTHD(push, NV907D, HEAD_SET_DEFAULT_BASE_COLOR(i),
354
+		  NVVAL(NV907D, HEAD_SET_DEFAULT_BASE_COLOR, RED, 0) |
355
+		  NVVAL(NV907D, HEAD_SET_DEFAULT_BASE_COLOR, GREEN, 0) |
356
+		  NVVAL(NV907D, HEAD_SET_DEFAULT_BASE_COLOR, BLUE, 0),
357
+
358
+				HEAD_SET_CRC_CONTROL(i),
359
+		  NVDEF(NV907D, HEAD_SET_CRC_CONTROL, CONTROLLING_CHANNEL, CORE) |
360
+		  NVDEF(NV907D, HEAD_SET_CRC_CONTROL, EXPECT_BUFFER_COLLAPSE, FALSE) |
361
+		  NVDEF(NV907D, HEAD_SET_CRC_CONTROL, TIMESTAMP_MODE, FALSE) |
362
+		  NVDEF(NV907D, HEAD_SET_CRC_CONTROL, PRIMARY_OUTPUT, NONE) |
363
+		  NVDEF(NV907D, HEAD_SET_CRC_CONTROL, SECONDARY_OUTPUT, NONE));
364
+
365
+	PUSH_MTHD(push, NV907D, HEAD_SET_PIXEL_CLOCK_FREQUENCY(i),
366
+		  NVVAL(NV907D, HEAD_SET_PIXEL_CLOCK_FREQUENCY, HERTZ, m->clock * 1000) |
367
+		  NVDEF(NV907D, HEAD_SET_PIXEL_CLOCK_FREQUENCY, ADJ1000DIV1001, FALSE),
368
+
369
+				HEAD_SET_PIXEL_CLOCK_CONFIGURATION(i),
370
+		  NVDEF(NV907D, HEAD_SET_PIXEL_CLOCK_CONFIGURATION, MODE, CLK_CUSTOM) |
371
+		  NVDEF(NV907D, HEAD_SET_PIXEL_CLOCK_CONFIGURATION, NOT_DRIVER, FALSE) |
372
+		  NVDEF(NV907D, HEAD_SET_PIXEL_CLOCK_CONFIGURATION, ENABLE_HOPPING, FALSE),
373
+
374
+				HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(i),
375
+		  NVVAL(NV907D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX, HERTZ, m->clock * 1000) |
376
+		  NVDEF(NV907D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX, ADJ1000DIV1001, FALSE));
377
+	return 0;
245
378
 }
246
379
 
247
-void
380
+int
248
381
 head907d_view(struct nv50_head *head, struct nv50_head_atom *asyh)
249
382
 {
250
-	struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan;
251
-	u32 *push;
252
-	if ((push = evo_wait(core, 8))) {
253
-		evo_mthd(push, 0x0494 + (head->base.index * 0x300), 1);
254
-		evo_data(push, 0x00000000);
255
-		evo_mthd(push, 0x04b8 + (head->base.index * 0x300), 1);
256
-		evo_data(push, asyh->view.iH << 16 | asyh->view.iW);
257
-		evo_mthd(push, 0x04c0 + (head->base.index * 0x300), 3);
258
-		evo_data(push, asyh->view.oH << 16 | asyh->view.oW);
259
-		evo_data(push, asyh->view.oH << 16 | asyh->view.oW);
260
-		evo_data(push, asyh->view.oH << 16 | asyh->view.oW);
261
-		evo_kick(push, core);
262
-	}
383
+	struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
384
+	const int i = head->base.index;
385
+	int ret;
386
+
387
+	if ((ret = PUSH_WAIT(push, 8)))
388
+		return ret;
389
+
390
+	PUSH_MTHD(push, NV907D, HEAD_SET_CONTROL_OUTPUT_SCALER(i),
391
+		  NVDEF(NV907D, HEAD_SET_CONTROL_OUTPUT_SCALER, VERTICAL_TAPS, TAPS_1) |
392
+		  NVDEF(NV907D, HEAD_SET_CONTROL_OUTPUT_SCALER, HORIZONTAL_TAPS, TAPS_1) |
393
+		  NVVAL(NV907D, HEAD_SET_CONTROL_OUTPUT_SCALER, HRESPONSE_BIAS, 0) |
394
+		  NVVAL(NV907D, HEAD_SET_CONTROL_OUTPUT_SCALER, VRESPONSE_BIAS, 0));
395
+
396
+	PUSH_MTHD(push, NV907D, HEAD_SET_VIEWPORT_SIZE_IN(i),
397
+		  NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_IN, WIDTH, asyh->view.iW) |
398
+		  NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_IN, HEIGHT, asyh->view.iH));
399
+
400
+	PUSH_MTHD(push, NV907D, HEAD_SET_VIEWPORT_SIZE_OUT(i),
401
+		  NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_OUT, WIDTH, asyh->view.oW) |
402
+		  NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_OUT, HEIGHT, asyh->view.oH),
403
+
404
+				HEAD_SET_VIEWPORT_SIZE_OUT_MIN(i),
405
+		  NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_OUT_MIN, WIDTH, asyh->view.oW) |
406
+		  NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_OUT_MIN, HEIGHT, asyh->view.oH),
407
+
408
+				HEAD_SET_VIEWPORT_SIZE_OUT_MAX(i),
409
+		  NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_OUT_MAX, WIDTH, asyh->view.oW) |
410
+		  NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_OUT_MAX, HEIGHT, asyh->view.oH));
411
+	return 0;
263
412
 }
264
413
 
265
414
 const struct nv50_head_func
..
..
@@ -267,6 +416,7 @@
267
416
 	.view = head907d_view,
268
417
 	.mode = head907d_mode,
269
418
 	.olut = head907d_olut,
419
+	.olut_size = 1024,
270
420
 	.olut_set = head907d_olut_set,
271
421
 	.olut_clr = head907d_olut_clr,
272
422
 	.core_calc = head507d_core_calc,