add dts config

hc

2023-12-06 08f87f769b595151be1afeff53e144f543faa614

 kernel/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
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@@ -1,13 +1,5 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 and
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- * only version 2 as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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  */
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 #ifndef _DPU_HW_MDSS_H
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@@ -100,10 +92,10 @@
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 	DPU_HW_BLK_SSPP,
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 	DPU_HW_BLK_LM,
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 	DPU_HW_BLK_CTL,
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-	DPU_HW_BLK_CDM,
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 	DPU_HW_BLK_PINGPONG,
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 	DPU_HW_BLK_INTF,
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 	DPU_HW_BLK_WB,
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+	DPU_HW_BLK_DSPP,
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 	DPU_HW_BLK_MAX,
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 };
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@@ -173,26 +165,14 @@
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 	DSPP_MAX
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 };
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-enum dpu_ds {
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-	DS_TOP,
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-	DS_0,
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-	DS_1,
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-	DS_MAX
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-};
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-
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 enum dpu_ctl {
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 	CTL_0 = 1,
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 	CTL_1,
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 	CTL_2,
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 	CTL_3,
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 	CTL_4,
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+	CTL_5,
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 	CTL_MAX
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-};
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-
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-enum dpu_cdm {
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-	CDM_0 = 1,
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-	CDM_1,
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-	CDM_MAX
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 };
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 enum dpu_pingpong {
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@@ -201,6 +181,7 @@
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 	PINGPONG_2,
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 	PINGPONG_3,
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 	PINGPONG_4,
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+	PINGPONG_5,
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 	PINGPONG_S0,
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 	PINGPONG_MAX
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 };
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@@ -246,12 +227,6 @@
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 	WB_MAX
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 };
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-enum dpu_ad {
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-	AD_0 = 0x1,
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-	AD_1,
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-	AD_MAX
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-};
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-
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 enum dpu_cwb {
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 	CWB_0 = 0x1,
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 	CWB_1,
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@@ -276,12 +251,6 @@
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 	VBIF_MAX,
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 	VBIF_RT = VBIF_0,
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 	VBIF_NRT = VBIF_1
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-};
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-
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-enum dpu_iommu_domain {
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-	DPU_IOMMU_DOMAIN_UNSECURE,
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-	DPU_IOMMU_DOMAIN_SECURE,
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-	DPU_IOMMU_DOMAIN_MAX
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 };
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 /**
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@@ -378,7 +347,6 @@
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  * @alpha_enable: whether the format has an alpha channel
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  * @num_planes: number of planes (including meta data planes)
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  * @fetch_mode: linear, tiled, or ubwc hw fetch behavior
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- * @is_yuv: is format a yuv variant
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  * @flag: usage bit flags
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  * @tile_width: format tile width
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  * @tile_height: format tile height
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@@ -451,15 +419,15 @@
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  * Define bit masks for h/w logging.
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  */
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 #define DPU_DBG_MASK_NONE     (1 << 0)
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-#define DPU_DBG_MASK_CDM      (1 << 1)
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-#define DPU_DBG_MASK_INTF     (1 << 2)
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-#define DPU_DBG_MASK_LM       (1 << 3)
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-#define DPU_DBG_MASK_CTL      (1 << 4)
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-#define DPU_DBG_MASK_PINGPONG (1 << 5)
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-#define DPU_DBG_MASK_SSPP     (1 << 6)
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-#define DPU_DBG_MASK_WB       (1 << 7)
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-#define DPU_DBG_MASK_TOP      (1 << 8)
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-#define DPU_DBG_MASK_VBIF     (1 << 9)
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-#define DPU_DBG_MASK_ROT      (1 << 10)
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+#define DPU_DBG_MASK_INTF     (1 << 1)
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+#define DPU_DBG_MASK_LM       (1 << 2)
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+#define DPU_DBG_MASK_CTL      (1 << 3)
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+#define DPU_DBG_MASK_PINGPONG (1 << 4)
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+#define DPU_DBG_MASK_SSPP     (1 << 5)
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+#define DPU_DBG_MASK_WB       (1 << 6)
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+#define DPU_DBG_MASK_TOP      (1 << 7)
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+#define DPU_DBG_MASK_VBIF     (1 << 8)
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+#define DPU_DBG_MASK_ROT      (1 << 9)
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+#define DPU_DBG_MASK_DSPP     (1 << 10)
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 #endif  /* _DPU_HW_MDSS_H */