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2023-12-06 08f87f769b595151be1afeff53e144f543faa614 
 kernel/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
....@@ -1,19 +1,10 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
2
- *
3
- * This program is free software; you can redistribute it and/or modify
4
- * it under the terms of the GNU General Public License version 2 and
5
- * only version 2 as published by the Free Software Foundation.
6
- *
7
- * This program is distributed in the hope that it will be useful,
8
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
9
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
10
- * GNU General Public License for more details.
113  */
124 
135 #include "dpu_hwio.h"
146 #include "dpu_hw_catalog.h"
157 #include "dpu_hw_intf.h"
16
-#include "dpu_dbg.h"
178 #include "dpu_kms.h"
189 
1910 #define INTF_TIMING_ENGINE_EN           0x000
....@@ -65,11 +56,10 @@
6556 #define   INTF_FRAME_COUNT              0x0AC
6657 #define   INTF_LINE_COUNT               0x0B0
6758 
68
-#define INTF_MISR_CTRL			0x180
69
-#define INTF_MISR_SIGNATURE		0x184
59
+#define   INTF_MUX                      0x25C
7060 
71
-static struct dpu_intf_cfg *_intf_offset(enum dpu_intf intf,
72
-		struct dpu_mdss_cfg *m,
61
+static const struct dpu_intf_cfg *_intf_offset(enum dpu_intf intf,
62
+		const struct dpu_mdss_cfg *m,
7363 		void __iomem *addr,
7464 		struct dpu_hw_blk_reg_map *b)
7565 {
....@@ -117,11 +107,6 @@
117107 	display_v_end = ((vsync_period - p->v_front_porch) * hsync_period) +
118108 	p->hsync_skew - 1;
119109 
120
-	if (ctx->cap->type == INTF_EDP || ctx->cap->type == INTF_DP) {
121
-		display_v_start += p->hsync_pulse_width + p->h_back_porch;
122
-		display_v_end -= p->h_front_porch;
123
-	}
124
-
125110 	hsync_start_x = p->h_back_porch + p->hsync_pulse_width;
126111 	hsync_end_x = hsync_period - p->h_front_porch - 1;
127112 
....@@ -154,10 +139,26 @@
154139 	hsync_ctl = (hsync_period << 16) | p->hsync_pulse_width;
155140 	display_hctl = (hsync_end_x << 16) | hsync_start_x;
156141 
142
+	if (ctx->cap->type == INTF_EDP || ctx->cap->type == INTF_DP) {
143
+		active_h_start = hsync_start_x;
144
+		active_h_end = active_h_start + p->xres - 1;
145
+		active_v_start = display_v_start;
146
+		active_v_end = active_v_start + (p->yres * hsync_period) - 1;
147
+
148
+		display_v_start += p->hsync_pulse_width + p->h_back_porch;
149
+		display_v_end   -= p->h_front_porch; 
150
+
151
+		active_hctl = (active_h_end << 16) | active_h_start;
152
+		display_hctl = active_hctl;
153
+	}
154
+
157155 	den_polarity = 0;
158156 	if (ctx->cap->type == INTF_HDMI) {
159157 		hsync_polarity = p->yres >= 720 ? 0 : 1;
160158 		vsync_polarity = p->yres >= 720 ? 0 : 1;
159
+	} else if (ctx->cap->type == INTF_DP) {
160
+		hsync_polarity = p->hsync_polarity;
161
+		vsync_polarity = p->vsync_polarity;
161162 	} else {
162163 		hsync_polarity = 0;
163164 		vsync_polarity = 0;
....@@ -230,6 +231,25 @@
230231 	DPU_REG_WRITE(c, INTF_CONFIG, fetch_enable);
231232 }
232233 
234
+static void dpu_hw_intf_bind_pingpong_blk(
235
+		struct dpu_hw_intf *intf,
236
+		bool enable,
237
+		const enum dpu_pingpong pp)
238
+{
239
+	struct dpu_hw_blk_reg_map *c = &intf->hw;
240
+	u32 mux_cfg;
241
+
242
+	mux_cfg = DPU_REG_READ(c, INTF_MUX);
243
+	mux_cfg &= ~0xf;
244
+
245
+	if (enable)
246
+		mux_cfg |= (pp - PINGPONG_0) & 0x7;
247
+	else
248
+		mux_cfg |= 0xf;
249
+
250
+	DPU_REG_WRITE(c, INTF_MUX, mux_cfg);
251
+}
252
+
233253 static void dpu_hw_intf_get_status(
234254 		struct dpu_hw_intf *intf,
235255 		struct intf_status *s)
....@@ -244,30 +264,6 @@
244264 		s->line_count = 0;
245265 		s->frame_count = 0;
246266 	}
247
-}
248
-
249
-static void dpu_hw_intf_setup_misr(struct dpu_hw_intf *intf,
250
-						bool enable, u32 frame_count)
251
-{
252
-	struct dpu_hw_blk_reg_map *c = &intf->hw;
253
-	u32 config = 0;
254
-
255
-	DPU_REG_WRITE(c, INTF_MISR_CTRL, MISR_CTRL_STATUS_CLEAR);
256
-	/* clear misr data */
257
-	wmb();
258
-
259
-	if (enable)
260
-		config = (frame_count & MISR_FRAME_COUNT_MASK) |
261
-			MISR_CTRL_ENABLE | INTF_MISR_CTRL_FREE_RUN_MASK;
262
-
263
-	DPU_REG_WRITE(c, INTF_MISR_CTRL, config);
264
-}
265
-
266
-static u32 dpu_hw_intf_collect_misr(struct dpu_hw_intf *intf)
267
-{
268
-	struct dpu_hw_blk_reg_map *c = &intf->hw;
269
-
270
-	return DPU_REG_READ(c, INTF_MISR_SIGNATURE);
271267 }
272268 
273269 static u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf)
....@@ -289,23 +285,19 @@
289285 	ops->setup_prg_fetch  = dpu_hw_intf_setup_prg_fetch;
290286 	ops->get_status = dpu_hw_intf_get_status;
291287 	ops->enable_timing = dpu_hw_intf_enable_timing_engine;
292
-	ops->setup_misr = dpu_hw_intf_setup_misr;
293
-	ops->collect_misr = dpu_hw_intf_collect_misr;
294288 	ops->get_line_count = dpu_hw_intf_get_line_count;
289
+	if (cap & BIT(DPU_INTF_INPUT_CTRL))
290
+		ops->bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk;
295291 }
296292 
297
-static struct dpu_hw_blk_ops dpu_hw_ops = {
298
-	.start = NULL,
299
-	.stop = NULL,
300
-};
293
+static struct dpu_hw_blk_ops dpu_hw_ops;
301294 
302295 struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx,
303296 		void __iomem *addr,
304
-		struct dpu_mdss_cfg *m)
297
+		const struct dpu_mdss_cfg *m)
305298 {
306299 	struct dpu_hw_intf *c;
307
-	struct dpu_intf_cfg *cfg;
308
-	int rc;
300
+	const struct dpu_intf_cfg *cfg;
309301 
310302 	c = kzalloc(sizeof(*c), GFP_KERNEL);
311303 	if (!c)
....@@ -326,18 +318,9 @@
326318 	c->mdss = m;
327319 	_setup_intf_ops(&c->ops, c->cap->features);
328320 
329
-	rc = dpu_hw_blk_init(&c->base, DPU_HW_BLK_INTF, idx, &dpu_hw_ops);
330
-	if (rc) {
331
-		DPU_ERROR("failed to init hw blk %d\n", rc);
332
-		goto blk_init_error;
333
-	}
321
+	dpu_hw_blk_init(&c->base, DPU_HW_BLK_INTF, idx, &dpu_hw_ops);
334322 
335323 	return c;
336
-
337
-blk_init_error:
338
-	kzfree(c);
339
-
340
-	return ERR_PTR(rc);
341324 }
342325 
343326 void dpu_hw_intf_destroy(struct dpu_hw_intf *intf)