~hc/RK356X_SDK_RELEASE.git

..	..	@@ -28,14 +28,29 @@
28	28
29	29	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30	30
31		-#include <linux/sysrq.h>
32		-#include <linux/slab.h>
33	31	#include <linux/circ_buf.h>
34		-#include <drm/drmP.h>
35		-#include <drm/i915_drm.h>
	32	+#include <linux/slab.h>
	33	+#include <linux/sysrq.h>
	34	+
	35	+#include <drm/drm_drv.h>
	36	+#include <drm/drm_irq.h>
	37	+
	38	+#include "display/intel_display_types.h"
	39	+#include "display/intel_fifo_underrun.h"
	40	+#include "display/intel_hotplug.h"
	41	+#include "display/intel_lpe_audio.h"
	42	+#include "display/intel_psr.h"
	43	+
	44	+#include "gt/intel_breadcrumbs.h"
	45	+#include "gt/intel_gt.h"
	46	+#include "gt/intel_gt_irq.h"
	47	+#include "gt/intel_gt_pm_irq.h"
	48	+#include "gt/intel_rps.h"
	49	+
36	50	#include "i915_drv.h"
	51	+#include "i915_irq.h"
37	52	#include "i915_trace.h"
38		-#include "intel_drv.h"
	53	+#include "intel_pm.h"
39	54
40	55	/**
41	56	* DOC: interrupt handling
..	..	@@ -44,6 +59,8 @@
44	59	* interrupt handling support. There's a lot more functionality in i915_irq.c
45	60	* and related files, but that will be described in separate chapters.
46	61	*/
	62	+
	63	+typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val);
47	64
48	65	static const u32 hpd_ilk[HPD_NUM_PINS] = {
49	66	[HPD_PORT_A] = DE_DP_A_HOTPLUG,
..	..	@@ -62,7 +79,7 @@
62	79	[HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
63	80	[HPD_PORT_B] = SDE_PORTB_HOTPLUG,
64	81	[HPD_PORT_C] = SDE_PORTC_HOTPLUG,
65		- [HPD_PORT_D] = SDE_PORTD_HOTPLUG
	82	+ [HPD_PORT_D] = SDE_PORTD_HOTPLUG,
66	83	};
67	84
68	85	static const u32 hpd_cpt[HPD_NUM_PINS] = {
..	..	@@ -70,7 +87,7 @@
70	87	[HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
71	88	[HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
72	89	[HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
73		- [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
	90	+ [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
74	91	};
75	92
76	93	static const u32 hpd_spt[HPD_NUM_PINS] = {
..	..	@@ -78,7 +95,7 @@
78	95	[HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
79	96	[HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
80	97	[HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
81		- [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
	98	+ [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT,
82	99	};
83	100
84	101	static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
..	..	@@ -87,7 +104,7 @@
87	104	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
88	105	[HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
89	106	[HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
90		- [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
	107	+ [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN,
91	108	};
92	109
93	110	static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
..	..	@@ -96,7 +113,7 @@
96	113	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
97	114	[HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
98	115	[HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
99		- [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
	116	+ [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS,
100	117	};
101	118
102	119	static const u32 hpd_status_i915[HPD_NUM_PINS] = {
..	..	@@ -105,132 +122,180 @@
105	122	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
106	123	[HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
107	124	[HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
108		- [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
	125	+ [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS,
109	126	};
110	127
111		-/* BXT hpd list */
112	128	static const u32 hpd_bxt[HPD_NUM_PINS] = {
113	129	[HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
114	130	[HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
115		- [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
	131	+ [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC,
116	132	};
117	133
118	134	static const u32 hpd_gen11[HPD_NUM_PINS] = {
119		- [HPD_PORT_C] = GEN11_TC1_HOTPLUG \| GEN11_TBT1_HOTPLUG,
120		- [HPD_PORT_D] = GEN11_TC2_HOTPLUG \| GEN11_TBT2_HOTPLUG,
121		- [HPD_PORT_E] = GEN11_TC3_HOTPLUG \| GEN11_TBT3_HOTPLUG,
122		- [HPD_PORT_F] = GEN11_TC4_HOTPLUG \| GEN11_TBT4_HOTPLUG
	135	+ [HPD_PORT_TC1] = GEN11_TC_HOTPLUG(PORT_TC1) \| GEN11_TBT_HOTPLUG(PORT_TC1),
	136	+ [HPD_PORT_TC2] = GEN11_TC_HOTPLUG(PORT_TC2) \| GEN11_TBT_HOTPLUG(PORT_TC2),
	137	+ [HPD_PORT_TC3] = GEN11_TC_HOTPLUG(PORT_TC3) \| GEN11_TBT_HOTPLUG(PORT_TC3),
	138	+ [HPD_PORT_TC4] = GEN11_TC_HOTPLUG(PORT_TC4) \| GEN11_TBT_HOTPLUG(PORT_TC4),
	139	+ [HPD_PORT_TC5] = GEN11_TC_HOTPLUG(PORT_TC5) \| GEN11_TBT_HOTPLUG(PORT_TC5),
	140	+ [HPD_PORT_TC6] = GEN11_TC_HOTPLUG(PORT_TC6) \| GEN11_TBT_HOTPLUG(PORT_TC6),
123	141	};
124	142
125	143	static const u32 hpd_icp[HPD_NUM_PINS] = {
126		- [HPD_PORT_A] = SDE_DDIA_HOTPLUG_ICP,
127		- [HPD_PORT_B] = SDE_DDIB_HOTPLUG_ICP,
128		- [HPD_PORT_C] = SDE_TC1_HOTPLUG_ICP,
129		- [HPD_PORT_D] = SDE_TC2_HOTPLUG_ICP,
130		- [HPD_PORT_E] = SDE_TC3_HOTPLUG_ICP,
131		- [HPD_PORT_F] = SDE_TC4_HOTPLUG_ICP
	144	+ [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A),
	145	+ [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B),
	146	+ [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PORT_C),
	147	+ [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(PORT_TC1),
	148	+ [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(PORT_TC2),
	149	+ [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(PORT_TC3),
	150	+ [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(PORT_TC4),
	151	+ [HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(PORT_TC5),
	152	+ [HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(PORT_TC6),
132	153	};
133	154
134		-/* IIR can theoretically queue up two events. Be paranoid. */
135		-#define GEN8_IRQ_RESET_NDX(type, which) do { \
136		- I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
137		- POSTING_READ(GEN8_##type##_IMR(which)); \
138		- I915_WRITE(GEN8_##type##_IER(which), 0); \
139		- I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
140		- POSTING_READ(GEN8_##type##_IIR(which)); \
141		- I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
142		- POSTING_READ(GEN8_##type##_IIR(which)); \
143		-} while (0)
	155	+static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
	156	+{
	157	+ struct i915_hotplug *hpd = &dev_priv->hotplug;
144	158
145		-#define GEN3_IRQ_RESET(type) do { \
146		- I915_WRITE(type##IMR, 0xffffffff); \
147		- POSTING_READ(type##IMR); \
148		- I915_WRITE(type##IER, 0); \
149		- I915_WRITE(type##IIR, 0xffffffff); \
150		- POSTING_READ(type##IIR); \
151		- I915_WRITE(type##IIR, 0xffffffff); \
152		- POSTING_READ(type##IIR); \
153		-} while (0)
	159	+ if (HAS_GMCH(dev_priv)) {
	160	+ if (IS_G4X(dev_priv) \|\| IS_VALLEYVIEW(dev_priv) \|\|
	161	+ IS_CHERRYVIEW(dev_priv))
	162	+ hpd->hpd = hpd_status_g4x;
	163	+ else
	164	+ hpd->hpd = hpd_status_i915;
	165	+ return;
	166	+ }
154	167
155		-#define GEN2_IRQ_RESET(type) do { \
156		- I915_WRITE16(type##IMR, 0xffff); \
157		- POSTING_READ16(type##IMR); \
158		- I915_WRITE16(type##IER, 0); \
159		- I915_WRITE16(type##IIR, 0xffff); \
160		- POSTING_READ16(type##IIR); \
161		- I915_WRITE16(type##IIR, 0xffff); \
162		- POSTING_READ16(type##IIR); \
163		-} while (0)
	168	+ if (INTEL_GEN(dev_priv) >= 11)
	169	+ hpd->hpd = hpd_gen11;
	170	+ else if (IS_GEN9_LP(dev_priv))
	171	+ hpd->hpd = hpd_bxt;
	172	+ else if (INTEL_GEN(dev_priv) >= 8)
	173	+ hpd->hpd = hpd_bdw;
	174	+ else if (INTEL_GEN(dev_priv) >= 7)
	175	+ hpd->hpd = hpd_ivb;
	176	+ else
	177	+ hpd->hpd = hpd_ilk;
	178	+
	179	+ if (!HAS_PCH_SPLIT(dev_priv) \|\| HAS_PCH_NOP(dev_priv))
	180	+ return;
	181	+
	182	+ if (HAS_PCH_TGP(dev_priv) \|\| HAS_PCH_JSP(dev_priv) \|\|
	183	+ HAS_PCH_ICP(dev_priv) \|\| HAS_PCH_MCC(dev_priv))
	184	+ hpd->pch_hpd = hpd_icp;
	185	+ else if (HAS_PCH_CNP(dev_priv) \|\| HAS_PCH_SPT(dev_priv))
	186	+ hpd->pch_hpd = hpd_spt;
	187	+ else if (HAS_PCH_LPT(dev_priv) \|\| HAS_PCH_CPT(dev_priv))
	188	+ hpd->pch_hpd = hpd_cpt;
	189	+ else if (HAS_PCH_IBX(dev_priv))
	190	+ hpd->pch_hpd = hpd_ibx;
	191	+ else
	192	+ MISSING_CASE(INTEL_PCH_TYPE(dev_priv));
	193	+}
	194	+
	195	+static void
	196	+intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
	197	+{
	198	+ struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
	199	+
	200	+ drm_crtc_handle_vblank(&crtc->base);
	201	+}
	202	+
	203	+void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
	204	+ i915_reg_t iir, i915_reg_t ier)
	205	+{
	206	+ intel_uncore_write(uncore, imr, 0xffffffff);
	207	+ intel_uncore_posting_read(uncore, imr);
	208	+
	209	+ intel_uncore_write(uncore, ier, 0);
	210	+
	211	+ /* IIR can theoretically queue up two events. Be paranoid. */
	212	+ intel_uncore_write(uncore, iir, 0xffffffff);
	213	+ intel_uncore_posting_read(uncore, iir);
	214	+ intel_uncore_write(uncore, iir, 0xffffffff);
	215	+ intel_uncore_posting_read(uncore, iir);
	216	+}
	217	+
	218	+void gen2_irq_reset(struct intel_uncore *uncore)
	219	+{
	220	+ intel_uncore_write16(uncore, GEN2_IMR, 0xffff);
	221	+ intel_uncore_posting_read16(uncore, GEN2_IMR);
	222	+
	223	+ intel_uncore_write16(uncore, GEN2_IER, 0);
	224	+
	225	+ /* IIR can theoretically queue up two events. Be paranoid. */
	226	+ intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
	227	+ intel_uncore_posting_read16(uncore, GEN2_IIR);
	228	+ intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
	229	+ intel_uncore_posting_read16(uncore, GEN2_IIR);
	230	+}
164	231
165	232	/*
166	233	* We should clear IMR at preinstall/uninstall, and just check at postinstall.
167	234	*/
168		-static void gen3_assert_iir_is_zero(struct drm_i915_private *dev_priv,
169		- i915_reg_t reg)
	235	+static void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg)
170	236	{
171		- u32 val = I915_READ(reg);
	237	+ u32 val = intel_uncore_read(uncore, reg);
172	238
173	239	if (val == 0)
174	240	return;
175	241
176		- WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
177		- i915_mmio_reg_offset(reg), val);
178		- I915_WRITE(reg, 0xffffffff);
179		- POSTING_READ(reg);
180		- I915_WRITE(reg, 0xffffffff);
181		- POSTING_READ(reg);
	242	+ drm_WARN(&uncore->i915->drm, 1,
	243	+ "Interrupt register 0x%x is not zero: 0x%08x\n",
	244	+ i915_mmio_reg_offset(reg), val);
	245	+ intel_uncore_write(uncore, reg, 0xffffffff);
	246	+ intel_uncore_posting_read(uncore, reg);
	247	+ intel_uncore_write(uncore, reg, 0xffffffff);
	248	+ intel_uncore_posting_read(uncore, reg);
182	249	}
183	250
184		-static void gen2_assert_iir_is_zero(struct drm_i915_private *dev_priv,
185		- i915_reg_t reg)
	251	+static void gen2_assert_iir_is_zero(struct intel_uncore *uncore)
186	252	{
187		- u16 val = I915_READ16(reg);
	253	+ u16 val = intel_uncore_read16(uncore, GEN2_IIR);
188	254
189	255	if (val == 0)
190	256	return;
191	257
192		- WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
193		- i915_mmio_reg_offset(reg), val);
194		- I915_WRITE16(reg, 0xffff);
195		- POSTING_READ16(reg);
196		- I915_WRITE16(reg, 0xffff);
197		- POSTING_READ16(reg);
	258	+ drm_WARN(&uncore->i915->drm, 1,
	259	+ "Interrupt register 0x%x is not zero: 0x%08x\n",
	260	+ i915_mmio_reg_offset(GEN2_IIR), val);
	261	+ intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
	262	+ intel_uncore_posting_read16(uncore, GEN2_IIR);
	263	+ intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
	264	+ intel_uncore_posting_read16(uncore, GEN2_IIR);
198	265	}
199	266
200		-#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
201		- gen3_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
202		- I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
203		- I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
204		- POSTING_READ(GEN8_##type##_IMR(which)); \
205		-} while (0)
	267	+void gen3_irq_init(struct intel_uncore *uncore,
	268	+ i915_reg_t imr, u32 imr_val,
	269	+ i915_reg_t ier, u32 ier_val,
	270	+ i915_reg_t iir)
	271	+{
	272	+ gen3_assert_iir_is_zero(uncore, iir);
206	273
207		-#define GEN3_IRQ_INIT(type, imr_val, ier_val) do { \
208		- gen3_assert_iir_is_zero(dev_priv, type##IIR); \
209		- I915_WRITE(type##IER, (ier_val)); \
210		- I915_WRITE(type##IMR, (imr_val)); \
211		- POSTING_READ(type##IMR); \
212		-} while (0)
	274	+ intel_uncore_write(uncore, ier, ier_val);
	275	+ intel_uncore_write(uncore, imr, imr_val);
	276	+ intel_uncore_posting_read(uncore, imr);
	277	+}
213	278
214		-#define GEN2_IRQ_INIT(type, imr_val, ier_val) do { \
215		- gen2_assert_iir_is_zero(dev_priv, type##IIR); \
216		- I915_WRITE16(type##IER, (ier_val)); \
217		- I915_WRITE16(type##IMR, (imr_val)); \
218		- POSTING_READ16(type##IMR); \
219		-} while (0)
	279	+void gen2_irq_init(struct intel_uncore *uncore,
	280	+ u32 imr_val, u32 ier_val)
	281	+{
	282	+ gen2_assert_iir_is_zero(uncore);
220	283
221		-static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
222		-static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
	284	+ intel_uncore_write16(uncore, GEN2_IER, ier_val);
	285	+ intel_uncore_write16(uncore, GEN2_IMR, imr_val);
	286	+ intel_uncore_posting_read16(uncore, GEN2_IMR);
	287	+}
223	288
224	289	/* For display hotplug interrupt */
225	290	static inline void
226	291	i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
227		- uint32_t mask,
228		- uint32_t bits)
	292	+ u32 mask,
	293	+ u32 bits)
229	294	{
230		- uint32_t val;
	295	+ u32 val;
231	296
232	297	lockdep_assert_held(&dev_priv->irq_lock);
233		- WARN_ON(bits & ~mask);
	298	+ drm_WARN_ON(&dev_priv->drm, bits & ~mask);
234	299
235	300	val = I915_READ(PORT_HOTPLUG_EN);
236	301	val &= ~mask;
..	..	@@ -251,47 +316,12 @@
251	316	* version is also available.
252	317	*/
253	318	void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
254		- uint32_t mask,
255		- uint32_t bits)
	319	+ u32 mask,
	320	+ u32 bits)
256	321	{
257	322	spin_lock_irq(&dev_priv->irq_lock);
258	323	i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
259	324	spin_unlock_irq(&dev_priv->irq_lock);
260		-}
261		-
262		-static u32
263		-gen11_gt_engine_identity(struct drm_i915_private * const i915,
264		- const unsigned int bank, const unsigned int bit);
265		-
266		-static bool gen11_reset_one_iir(struct drm_i915_private * const i915,
267		- const unsigned int bank,
268		- const unsigned int bit)
269		-{
270		- void __iomem * const regs = i915->regs;
271		- u32 dw;
272		-
273		- lockdep_assert_held(&i915->irq_lock);
274		-
275		- dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
276		- if (dw & BIT(bit)) {
277		- /*
278		- * According to the BSpec, DW_IIR bits cannot be cleared without
279		- * first servicing the Selector & Shared IIR registers.
280		- */
281		- gen11_gt_engine_identity(i915, bank, bit);
282		-
283		- /*
284		- * We locked GT INT DW by reading it. If we want to (try
285		- * to) recover from this succesfully, we need to clear
286		- * our bit, otherwise we are locking the register for
287		- * everybody.
288		- */
289		- raw_reg_write(regs, GEN11_GT_INTR_DW(bank), BIT(bit));
290		-
291		- return true;
292		- }
293		-
294		- return false;
295	325	}
296	326
297	327	/**
..	..	@@ -301,16 +331,16 @@
301	331	* @enabled_irq_mask: mask of interrupt bits to enable
302	332	*/
303	333	void ilk_update_display_irq(struct drm_i915_private *dev_priv,
304		- uint32_t interrupt_mask,
305		- uint32_t enabled_irq_mask)
	334	+ u32 interrupt_mask,
	335	+ u32 enabled_irq_mask)
306	336	{
307		- uint32_t new_val;
	337	+ u32 new_val;
308	338
309	339	lockdep_assert_held(&dev_priv->irq_lock);
310	340
311		- WARN_ON(enabled_irq_mask & ~interrupt_mask);
	341	+ drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
312	342
313		- if (WARN_ON(!intel_irqs_enabled(dev_priv)))
	343	+ if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
314	344	return;
315	345
316	346	new_val = dev_priv->irq_mask;
..	..	@@ -325,270 +355,23 @@
325	355	}
326	356
327	357	/**
328		- * ilk_update_gt_irq - update GTIMR
329		- * @dev_priv: driver private
330		- * @interrupt_mask: mask of interrupt bits to update
331		- * @enabled_irq_mask: mask of interrupt bits to enable
332		- */
333		-static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
334		- uint32_t interrupt_mask,
335		- uint32_t enabled_irq_mask)
336		-{
337		- lockdep_assert_held(&dev_priv->irq_lock);
338		-
339		- WARN_ON(enabled_irq_mask & ~interrupt_mask);
340		-
341		- if (WARN_ON(!intel_irqs_enabled(dev_priv)))
342		- return;
343		-
344		- dev_priv->gt_irq_mask &= ~interrupt_mask;
345		- dev_priv->gt_irq_mask \|= (~enabled_irq_mask & interrupt_mask);
346		- I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
347		-}
348		-
349		-void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
350		-{
351		- ilk_update_gt_irq(dev_priv, mask, mask);
352		- POSTING_READ_FW(GTIMR);
353		-}
354		-
355		-void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
356		-{
357		- ilk_update_gt_irq(dev_priv, mask, 0);
358		-}
359		-
360		-static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
361		-{
362		- WARN_ON_ONCE(INTEL_GEN(dev_priv) >= 11);
363		-
364		- return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
365		-}
366		-
367		-static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
368		-{
369		- if (INTEL_GEN(dev_priv) >= 11)
370		- return GEN11_GPM_WGBOXPERF_INTR_MASK;
371		- else if (INTEL_GEN(dev_priv) >= 8)
372		- return GEN8_GT_IMR(2);
373		- else
374		- return GEN6_PMIMR;
375		-}
376		-
377		-static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
378		-{
379		- if (INTEL_GEN(dev_priv) >= 11)
380		- return GEN11_GPM_WGBOXPERF_INTR_ENABLE;
381		- else if (INTEL_GEN(dev_priv) >= 8)
382		- return GEN8_GT_IER(2);
383		- else
384		- return GEN6_PMIER;
385		-}
386		-
387		-/**
388		- * snb_update_pm_irq - update GEN6_PMIMR
389		- * @dev_priv: driver private
390		- * @interrupt_mask: mask of interrupt bits to update
391		- * @enabled_irq_mask: mask of interrupt bits to enable
392		- */
393		-static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
394		- uint32_t interrupt_mask,
395		- uint32_t enabled_irq_mask)
396		-{
397		- uint32_t new_val;
398		-
399		- WARN_ON(enabled_irq_mask & ~interrupt_mask);
400		-
401		- lockdep_assert_held(&dev_priv->irq_lock);
402		-
403		- new_val = dev_priv->pm_imr;
404		- new_val &= ~interrupt_mask;
405		- new_val \|= (~enabled_irq_mask & interrupt_mask);
406		-
407		- if (new_val != dev_priv->pm_imr) {
408		- dev_priv->pm_imr = new_val;
409		- I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_imr);
410		- POSTING_READ(gen6_pm_imr(dev_priv));
411		- }
412		-}
413		-
414		-void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
415		-{
416		- if (WARN_ON(!intel_irqs_enabled(dev_priv)))
417		- return;
418		-
419		- snb_update_pm_irq(dev_priv, mask, mask);
420		-}
421		-
422		-static void __gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
423		-{
424		- snb_update_pm_irq(dev_priv, mask, 0);
425		-}
426		-
427		-void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
428		-{
429		- if (WARN_ON(!intel_irqs_enabled(dev_priv)))
430		- return;
431		-
432		- __gen6_mask_pm_irq(dev_priv, mask);
433		-}
434		-
435		-static void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
436		-{
437		- i915_reg_t reg = gen6_pm_iir(dev_priv);
438		-
439		- lockdep_assert_held(&dev_priv->irq_lock);
440		-
441		- I915_WRITE(reg, reset_mask);
442		- I915_WRITE(reg, reset_mask);
443		- POSTING_READ(reg);
444		-}
445		-
446		-static void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
447		-{
448		- lockdep_assert_held(&dev_priv->irq_lock);
449		-
450		- dev_priv->pm_ier \|= enable_mask;
451		- I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier);
452		- gen6_unmask_pm_irq(dev_priv, enable_mask);
453		- /* unmask_pm_irq provides an implicit barrier (POSTING_READ) */
454		-}
455		-
456		-static void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask)
457		-{
458		- lockdep_assert_held(&dev_priv->irq_lock);
459		-
460		- dev_priv->pm_ier &= ~disable_mask;
461		- __gen6_mask_pm_irq(dev_priv, disable_mask);
462		- I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier);
463		- /* though a barrier is missing here, but don't really need a one */
464		-}
465		-
466		-void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv)
467		-{
468		- spin_lock_irq(&dev_priv->irq_lock);
469		-
470		- while (gen11_reset_one_iir(dev_priv, 0, GEN11_GTPM))
471		- ;
472		-
473		- dev_priv->gt_pm.rps.pm_iir = 0;
474		-
475		- spin_unlock_irq(&dev_priv->irq_lock);
476		-}
477		-
478		-void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
479		-{
480		- spin_lock_irq(&dev_priv->irq_lock);
481		- gen6_reset_pm_iir(dev_priv, dev_priv->pm_rps_events);
482		- dev_priv->gt_pm.rps.pm_iir = 0;
483		- spin_unlock_irq(&dev_priv->irq_lock);
484		-}
485		-
486		-void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
487		-{
488		- struct intel_rps *rps = &dev_priv->gt_pm.rps;
489		-
490		- if (READ_ONCE(rps->interrupts_enabled))
491		- return;
492		-
493		- spin_lock_irq(&dev_priv->irq_lock);
494		- WARN_ON_ONCE(rps->pm_iir);
495		-
496		- if (INTEL_GEN(dev_priv) >= 11)
497		- WARN_ON_ONCE(gen11_reset_one_iir(dev_priv, 0, GEN11_GTPM));
498		- else
499		- WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
500		-
501		- rps->interrupts_enabled = true;
502		- gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
503		-
504		- spin_unlock_irq(&dev_priv->irq_lock);
505		-}
506		-
507		-void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
508		-{
509		- struct intel_rps *rps = &dev_priv->gt_pm.rps;
510		-
511		- if (!READ_ONCE(rps->interrupts_enabled))
512		- return;
513		-
514		- spin_lock_irq(&dev_priv->irq_lock);
515		- rps->interrupts_enabled = false;
516		-
517		- I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u));
518		-
519		- gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
520		-
521		- spin_unlock_irq(&dev_priv->irq_lock);
522		- synchronize_irq(dev_priv->drm.irq);
523		-
524		- /* Now that we will not be generating any more work, flush any
525		- * outstanding tasks. As we are called on the RPS idle path,
526		- * we will reset the GPU to minimum frequencies, so the current
527		- * state of the worker can be discarded.
528		- */
529		- cancel_work_sync(&rps->work);
530		- if (INTEL_GEN(dev_priv) >= 11)
531		- gen11_reset_rps_interrupts(dev_priv);
532		- else
533		- gen6_reset_rps_interrupts(dev_priv);
534		-}
535		-
536		-void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
537		-{
538		- assert_rpm_wakelock_held(dev_priv);
539		-
540		- spin_lock_irq(&dev_priv->irq_lock);
541		- gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events);
542		- spin_unlock_irq(&dev_priv->irq_lock);
543		-}
544		-
545		-void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
546		-{
547		- assert_rpm_wakelock_held(dev_priv);
548		-
549		- spin_lock_irq(&dev_priv->irq_lock);
550		- if (!dev_priv->guc.interrupts_enabled) {
551		- WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
552		- dev_priv->pm_guc_events);
553		- dev_priv->guc.interrupts_enabled = true;
554		- gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
555		- }
556		- spin_unlock_irq(&dev_priv->irq_lock);
557		-}
558		-
559		-void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
560		-{
561		- assert_rpm_wakelock_held(dev_priv);
562		-
563		- spin_lock_irq(&dev_priv->irq_lock);
564		- dev_priv->guc.interrupts_enabled = false;
565		-
566		- gen6_disable_pm_irq(dev_priv, dev_priv->pm_guc_events);
567		-
568		- spin_unlock_irq(&dev_priv->irq_lock);
569		- synchronize_irq(dev_priv->drm.irq);
570		-
571		- gen9_reset_guc_interrupts(dev_priv);
572		-}
573		-
574		-/**
575	358	* bdw_update_port_irq - update DE port interrupt
576	359	* @dev_priv: driver private
577	360	* @interrupt_mask: mask of interrupt bits to update
578	361	* @enabled_irq_mask: mask of interrupt bits to enable
579	362	*/
580	363	static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
581		- uint32_t interrupt_mask,
582		- uint32_t enabled_irq_mask)
	364	+ u32 interrupt_mask,
	365	+ u32 enabled_irq_mask)
583	366	{
584		- uint32_t new_val;
585		- uint32_t old_val;
	367	+ u32 new_val;
	368	+ u32 old_val;
586	369
587	370	lockdep_assert_held(&dev_priv->irq_lock);
588	371
589		- WARN_ON(enabled_irq_mask & ~interrupt_mask);
	372	+ drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
590	373
591		- if (WARN_ON(!intel_irqs_enabled(dev_priv)))
	374	+ if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
592	375	return;
593	376
594	377	old_val = I915_READ(GEN8_DE_PORT_IMR);
..	..	@@ -612,16 +395,16 @@
612	395	*/
613	396	void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
614	397	enum pipe pipe,
615		- uint32_t interrupt_mask,
616		- uint32_t enabled_irq_mask)
	398	+ u32 interrupt_mask,
	399	+ u32 enabled_irq_mask)
617	400	{
618		- uint32_t new_val;
	401	+ u32 new_val;
619	402
620	403	lockdep_assert_held(&dev_priv->irq_lock);
621	404
622		- WARN_ON(enabled_irq_mask & ~interrupt_mask);
	405	+ drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
623	406
624		- if (WARN_ON(!intel_irqs_enabled(dev_priv)))
	407	+ if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
625	408	return;
626	409
627	410	new_val = dev_priv->de_irq_mask[pipe];
..	..	@@ -642,18 +425,18 @@
642	425	* @enabled_irq_mask: mask of interrupt bits to enable
643	426	*/
644	427	void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
645		- uint32_t interrupt_mask,
646		- uint32_t enabled_irq_mask)
	428	+ u32 interrupt_mask,
	429	+ u32 enabled_irq_mask)
647	430	{
648		- uint32_t sdeimr = I915_READ(SDEIMR);
	431	+ u32 sdeimr = I915_READ(SDEIMR);
649	432	sdeimr &= ~interrupt_mask;
650	433	sdeimr \|= (~enabled_irq_mask & interrupt_mask);
651	434
652		- WARN_ON(enabled_irq_mask & ~interrupt_mask);
	435	+ drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
653	436
654	437	lockdep_assert_held(&dev_priv->irq_lock);
655	438
656		- if (WARN_ON(!intel_irqs_enabled(dev_priv)))
	439	+ if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
657	440	return;
658	441
659	442	I915_WRITE(SDEIMR, sdeimr);
..	..	@@ -675,13 +458,15 @@
675	458	* On pipe A we don't support the PSR interrupt yet,
676	459	* on pipe B and C the same bit MBZ.
677	460	*/
678		- if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
	461	+ if (drm_WARN_ON_ONCE(&dev_priv->drm,
	462	+ status_mask & PIPE_A_PSR_STATUS_VLV))
679	463	return 0;
680	464	/*
681	465	* On pipe B and C we don't support the PSR interrupt yet, on pipe
682	466	* A the same bit is for perf counters which we don't use either.
683	467	*/
684		- if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
	468	+ if (drm_WARN_ON_ONCE(&dev_priv->drm,
	469	+ status_mask & PIPE_B_PSR_STATUS_VLV))
685	470	return 0;
686	471
687	472	enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS \|
..	..	@@ -693,10 +478,11 @@
693	478	enable_mask \|= SPRITE1_FLIP_DONE_INT_EN_VLV;
694	479
695	480	out:
696		- WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK \|\|
697		- status_mask & ~PIPESTAT_INT_STATUS_MASK,
698		- "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
699		- pipe_name(pipe), enable_mask, status_mask);
	481	+ drm_WARN_ONCE(&dev_priv->drm,
	482	+ enable_mask & ~PIPESTAT_INT_ENABLE_MASK \|\|
	483	+ status_mask & ~PIPESTAT_INT_STATUS_MASK,
	484	+ "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
	485	+ pipe_name(pipe), enable_mask, status_mask);
700	486
701	487	return enable_mask;
702	488	}
..	..	@@ -707,12 +493,12 @@
707	493	i915_reg_t reg = PIPESTAT(pipe);
708	494	u32 enable_mask;
709	495
710		- WARN_ONCE(status_mask & ~PIPESTAT_INT_STATUS_MASK,
711		- "pipe %c: status_mask=0x%x\n",
712		- pipe_name(pipe), status_mask);
	496	+ drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
	497	+ "pipe %c: status_mask=0x%x\n",
	498	+ pipe_name(pipe), status_mask);
713	499
714	500	lockdep_assert_held(&dev_priv->irq_lock);
715		- WARN_ON(!intel_irqs_enabled(dev_priv));
	501	+ drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));
716	502
717	503	if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == status_mask)
718	504	return;
..	..	@@ -730,12 +516,12 @@
730	516	i915_reg_t reg = PIPESTAT(pipe);
731	517	u32 enable_mask;
732	518
733		- WARN_ONCE(status_mask & ~PIPESTAT_INT_STATUS_MASK,
734		- "pipe %c: status_mask=0x%x\n",
735		- pipe_name(pipe), status_mask);
	519	+ drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
	520	+ "pipe %c: status_mask=0x%x\n",
	521	+ pipe_name(pipe), status_mask);
736	522
737	523	lockdep_assert_held(&dev_priv->irq_lock);
738		- WARN_ON(!intel_irqs_enabled(dev_priv));
	524	+ drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));
739	525
740	526	if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == 0)
741	527	return;
..	..	@@ -747,13 +533,21 @@
747	533	POSTING_READ(reg);
748	534	}
749	535
	536	+static bool i915_has_asle(struct drm_i915_private *dev_priv)
	537	+{
	538	+ if (!dev_priv->opregion.asle)
	539	+ return false;
	540	+
	541	+ return IS_PINEVIEW(dev_priv) \|\| IS_MOBILE(dev_priv);
	542	+}
	543	+
750	544	/**
751	545	* i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
752	546	* @dev_priv: i915 device private
753	547	*/
754	548	static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
755	549	{
756		- if (!dev_priv->opregion.asle \|\| !IS_MOBILE(dev_priv))
	550	+ if (!i915_has_asle(dev_priv))
757	551	return;
758	552
759	553	spin_lock_irq(&dev_priv->irq_lock);
..	..	@@ -819,13 +613,29 @@
819	613	/* Called from drm generic code, passed a 'crtc', which
820	614	* we use as a pipe index
821	615	*/
822		-static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
	616	+u32 i915_get_vblank_counter(struct drm_crtc *crtc)
823	617	{
824		- struct drm_i915_private *dev_priv = to_i915(dev);
	618	+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
	619	+ struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)];
	620	+ const struct drm_display_mode *mode = &vblank->hwmode;
	621	+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
825	622	i915_reg_t high_frame, low_frame;
826	623	u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
827		- const struct drm_display_mode *mode = &dev->vblank[pipe].hwmode;
828	624	unsigned long irqflags;
	625	+
	626	+ /*
	627	+ * On i965gm TV output the frame counter only works up to
	628	+ * the point when we enable the TV encoder. After that the
	629	+ * frame counter ceases to work and reads zero. We need a
	630	+ * vblank wait before enabling the TV encoder and so we
	631	+ * have to enable vblank interrupts while the frame counter
	632	+ * is still in a working state. However the core vblank code
	633	+ * does not like us returning non-zero frame counter values
	634	+ * when we've told it that we don't have a working frame
	635	+ * counter. Thus we must stop non-zero values leaking out.
	636	+ */
	637	+ if (!vblank->max_vblank_count)
	638	+ return 0;
829	639
830	640	htotal = mode->crtc_htotal;
831	641	hsync_start = mode->crtc_hsync_start;
..	..	@@ -850,9 +660,9 @@
850	660	* register.
851	661	*/
852	662	do {
853		- high1 = I915_READ_FW(high_frame) & PIPE_FRAME_HIGH_MASK;
854		- low = I915_READ_FW(low_frame);
855		- high2 = I915_READ_FW(high_frame) & PIPE_FRAME_HIGH_MASK;
	663	+ high1 = intel_de_read_fw(dev_priv, high_frame) & PIPE_FRAME_HIGH_MASK;
	664	+ low = intel_de_read_fw(dev_priv, low_frame);
	665	+ high2 = intel_de_read_fw(dev_priv, high_frame) & PIPE_FRAME_HIGH_MASK;
856	666	} while (high1 != high2);
857	667
858	668	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
..	..	@@ -869,9 +679,10 @@
869	679	return (((high1 << 8) \| low) + (pixel >= vbl_start)) & 0xffffff;
870	680	}
871	681
872		-static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
	682	+u32 g4x_get_vblank_counter(struct drm_crtc *crtc)
873	683	{
874		- struct drm_i915_private *dev_priv = to_i915(dev);
	684	+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
	685	+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
875	686
876	687	return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
877	688	}
..	..	@@ -908,15 +719,17 @@
908	719	* pipe frame time stamp. The time stamp value
909	720	* is sampled at every start of vertical blank.
910	721	*/
911		- scan_prev_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe));
	722	+ scan_prev_time = intel_de_read_fw(dev_priv,
	723	+ PIPE_FRMTMSTMP(crtc->pipe));
912	724
913	725	/*
914	726	* The TIMESTAMP_CTR register has the current
915	727	* time stamp value.
916	728	*/
917		- scan_curr_time = I915_READ_FW(IVB_TIMESTAMP_CTR);
	729	+ scan_curr_time = intel_de_read_fw(dev_priv, IVB_TIMESTAMP_CTR);
918	730
919		- scan_post_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe));
	731	+ scan_post_time = intel_de_read_fw(dev_priv,
	732	+ PIPE_FRMTMSTMP(crtc->pipe));
920	733	} while (scan_post_time != scan_prev_time);
921	734
922	735	scanline = div_u64(mul_u32_u32(scan_curr_time - scan_prev_time,
..	..	@@ -927,7 +740,10 @@
927	740	return scanline;
928	741	}
929	742
930		-/* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
	743	+/*
	744	+ * intel_de_read_fw(), only for fast reads of display block, no need for
	745	+ * forcewake etc.
	746	+ */
931	747	static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
932	748	{
933	749	struct drm_device *dev = crtc->base.dev;
..	..	@@ -943,17 +759,17 @@
943	759	vblank = &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
944	760	mode = &vblank->hwmode;
945	761
946		- if (mode->private_flags & I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP)
	762	+ if (crtc->mode_flags & I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP)
947	763	return __intel_get_crtc_scanline_from_timestamp(crtc);
948	764
949	765	vtotal = mode->crtc_vtotal;
950	766	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
951	767	vtotal /= 2;
952	768
953		- if (IS_GEN2(dev_priv))
954		- position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
	769	+ if (IS_GEN(dev_priv, 2))
	770	+ position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
955	771	else
956		- position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
	772	+ position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
957	773
958	774	/*
959	775	* On HSW, the DSL reg (0x70000) appears to return 0 if we
..	..	@@ -972,7 +788,7 @@
972	788
973	789	for (i = 0; i < 100; i++) {
974	790	udelay(1);
975		- temp = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
	791	+ temp = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
976	792	if (temp != position) {
977	793	position = temp;
978	794	break;
..	..	@@ -987,21 +803,27 @@
987	803	return (position + crtc->scanline_offset) % vtotal;
988	804	}
989	805
990		-static bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
991		- bool in_vblank_irq, int vpos, int hpos,
	806	+static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
	807	+ bool in_vblank_irq,
	808	+ int vpos, int hpos,
992	809	ktime_t stime, ktime_t etime,
993	810	const struct drm_display_mode *mode)
994	811	{
	812	+ struct drm_device *dev = _crtc->dev;
995	813	struct drm_i915_private *dev_priv = to_i915(dev);
996		- struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
997		- pipe);
	814	+ struct intel_crtc *crtc = to_intel_crtc(_crtc);
	815	+ enum pipe pipe = crtc->pipe;
998	816	int position;
999	817	int vbl_start, vbl_end, hsync_start, htotal, vtotal;
1000	818	unsigned long irqflags;
	819	+ bool use_scanline_counter = INTEL_GEN(dev_priv) >= 5 \|\|
	820	+ IS_G4X(dev_priv) \|\| IS_GEN(dev_priv, 2) \|\|
	821	+ crtc->mode_flags & I915_MODE_FLAG_USE_SCANLINE_COUNTER;
1001	822
1002		- if (WARN_ON(!mode->crtc_clock)) {
1003		- DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
1004		- "pipe %c\n", pipe_name(pipe));
	823	+ if (drm_WARN_ON(&dev_priv->drm, !mode->crtc_clock)) {
	824	+ drm_dbg(&dev_priv->drm,
	825	+ "trying to get scanoutpos for disabled "
	826	+ "pipe %c\n", pipe_name(pipe));
1005	827	return false;
1006	828	}
1007	829
..	..	@@ -1025,22 +847,23 @@
1025	847	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1026	848
1027	849	/* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
	850	+ preempt_disable_rt();
1028	851
1029	852	/* Get optional system timestamp before query. */
1030	853	if (stime)
1031	854	*stime = ktime_get();
1032	855
1033		- if (IS_GEN2(dev_priv) \|\| IS_G4X(dev_priv) \|\| INTEL_GEN(dev_priv) >= 5) {
	856	+ if (use_scanline_counter) {
1034	857	/* No obvious pixelcount register. Only query vertical
1035	858	* scanout position from Display scan line register.
1036	859	*/
1037		- position = __intel_get_crtc_scanline(intel_crtc);
	860	+ position = __intel_get_crtc_scanline(crtc);
1038	861	} else {
1039	862	/* Have access to pixelcount since start of frame.
1040	863	* We can split this into vertical and horizontal
1041	864	* scanout position.
1042	865	*/
1043		- position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
	866	+ position = (intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
1044	867
1045	868	/* convert to pixel counts */
1046	869	vbl_start *= htotal;
..	..	@@ -1076,6 +899,7 @@
1076	899	*etime = ktime_get();
1077	900
1078	901	/* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
	902	+ preempt_enable_rt();
1079	903
1080	904	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1081	905
..	..	@@ -1090,7 +914,7 @@
1090	914	else
1091	915	position += vtotal - vbl_end;
1092	916
1093		- if (IS_GEN2(dev_priv) \|\| IS_G4X(dev_priv) \|\| INTEL_GEN(dev_priv) >= 5) {
	917	+ if (use_scanline_counter) {
1094	918	*vpos = position;
1095	919	*hpos = 0;
1096	920	} else {
..	..	@@ -1099,6 +923,14 @@
1099	923	}
1100	924
1101	925	return true;
	926	+}
	927	+
	928	+bool intel_crtc_get_vblank_timestamp(struct drm_crtc crtc, int max_error,
	929	+ ktime_t *vblank_time, bool in_vblank_irq)
	930	+{
	931	+ return drm_crtc_vblank_helper_get_vblank_timestamp_internal(
	932	+ crtc, max_error, vblank_time, in_vblank_irq,
	933	+ i915_get_crtc_scanoutpos);
1102	934	}
1103	935
1104	936	int intel_get_crtc_scanline(struct intel_crtc *crtc)
..	..	@@ -1114,255 +946,8 @@
1114	946	return position;
1115	947	}
1116	948
1117		-static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv)
1118		-{
1119		- u32 busy_up, busy_down, max_avg, min_avg;
1120		- u8 new_delay;
1121		-
1122		- spin_lock(&mchdev_lock);
1123		-
1124		- I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
1125		-
1126		- new_delay = dev_priv->ips.cur_delay;
1127		-
1128		- I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
1129		- busy_up = I915_READ(RCPREVBSYTUPAVG);
1130		- busy_down = I915_READ(RCPREVBSYTDNAVG);
1131		- max_avg = I915_READ(RCBMAXAVG);
1132		- min_avg = I915_READ(RCBMINAVG);
1133		-
1134		- /* Handle RCS change request from hw */
1135		- if (busy_up > max_avg) {
1136		- if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
1137		- new_delay = dev_priv->ips.cur_delay - 1;
1138		- if (new_delay < dev_priv->ips.max_delay)
1139		- new_delay = dev_priv->ips.max_delay;
1140		- } else if (busy_down < min_avg) {
1141		- if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
1142		- new_delay = dev_priv->ips.cur_delay + 1;
1143		- if (new_delay > dev_priv->ips.min_delay)
1144		- new_delay = dev_priv->ips.min_delay;
1145		- }
1146		-
1147		- if (ironlake_set_drps(dev_priv, new_delay))
1148		- dev_priv->ips.cur_delay = new_delay;
1149		-
1150		- spin_unlock(&mchdev_lock);
1151		-
1152		- return;
1153		-}
1154		-
1155		-static void notify_ring(struct intel_engine_cs *engine)
1156		-{
1157		- const u32 seqno = intel_engine_get_seqno(engine);
1158		- struct i915_request *rq = NULL;
1159		- struct task_struct *tsk = NULL;
1160		- struct intel_wait *wait;
1161		-
1162		- if (unlikely(!engine->breadcrumbs.irq_armed))
1163		- return;
1164		-
1165		- rcu_read_lock();
1166		-
1167		- spin_lock(&engine->breadcrumbs.irq_lock);
1168		- wait = engine->breadcrumbs.irq_wait;
1169		- if (wait) {
1170		- /*
1171		- * We use a callback from the dma-fence to submit
1172		- * requests after waiting on our own requests. To
1173		- * ensure minimum delay in queuing the next request to
1174		- * hardware, signal the fence now rather than wait for
1175		- * the signaler to be woken up. We still wake up the
1176		- * waiter in order to handle the irq-seqno coherency
1177		- * issues (we may receive the interrupt before the
1178		- * seqno is written, see __i915_request_irq_complete())
1179		- * and to handle coalescing of multiple seqno updates
1180		- * and many waiters.
1181		- */
1182		- if (i915_seqno_passed(seqno, wait->seqno)) {
1183		- struct i915_request *waiter = wait->request;
1184		-
1185		- if (waiter &&
1186		- !test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
1187		- &waiter->fence.flags) &&
1188		- intel_wait_check_request(wait, waiter))
1189		- rq = i915_request_get(waiter);
1190		-
1191		- tsk = wait->tsk;
1192		- } else {
1193		- if (engine->irq_seqno_barrier &&
1194		- i915_seqno_passed(seqno, wait->seqno - 1)) {
1195		- set_bit(ENGINE_IRQ_BREADCRUMB,
1196		- &engine->irq_posted);
1197		- tsk = wait->tsk;
1198		- }
1199		- }
1200		-
1201		- engine->breadcrumbs.irq_count++;
1202		- } else {
1203		- if (engine->breadcrumbs.irq_armed)
1204		- __intel_engine_disarm_breadcrumbs(engine);
1205		- }
1206		- spin_unlock(&engine->breadcrumbs.irq_lock);
1207		-
1208		- if (rq) {
1209		- spin_lock(&rq->lock);
1210		- dma_fence_signal_locked(&rq->fence);
1211		- GEM_BUG_ON(!i915_request_completed(rq));
1212		- spin_unlock(&rq->lock);
1213		-
1214		- i915_request_put(rq);
1215		- }
1216		-
1217		- if (tsk && tsk->state & TASK_NORMAL)
1218		- wake_up_process(tsk);
1219		-
1220		- rcu_read_unlock();
1221		-
1222		- trace_intel_engine_notify(engine, wait);
1223		-}
1224		-
1225		-static void vlv_c0_read(struct drm_i915_private *dev_priv,
1226		- struct intel_rps_ei *ei)
1227		-{
1228		- ei->ktime = ktime_get_raw();
1229		- ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
1230		- ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
1231		-}
1232		-
1233		-void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
1234		-{
1235		- memset(&dev_priv->gt_pm.rps.ei, 0, sizeof(dev_priv->gt_pm.rps.ei));
1236		-}
1237		-
1238		-static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
1239		-{
1240		- struct intel_rps *rps = &dev_priv->gt_pm.rps;
1241		- const struct intel_rps_ei *prev = &rps->ei;
1242		- struct intel_rps_ei now;
1243		- u32 events = 0;
1244		-
1245		- if ((pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) == 0)
1246		- return 0;
1247		-
1248		- vlv_c0_read(dev_priv, &now);
1249		-
1250		- if (prev->ktime) {
1251		- u64 time, c0;
1252		- u32 render, media;
1253		-
1254		- time = ktime_us_delta(now.ktime, prev->ktime);
1255		-
1256		- time *= dev_priv->czclk_freq;
1257		-
1258		- /* Workload can be split between render + media,
1259		- * e.g. SwapBuffers being blitted in X after being rendered in
1260		- * mesa. To account for this we need to combine both engines
1261		- * into our activity counter.
1262		- */
1263		- render = now.render_c0 - prev->render_c0;
1264		- media = now.media_c0 - prev->media_c0;
1265		- c0 = max(render, media);
1266		- c0 = 1000 100 << 8; /* to usecs and scale to threshold% */
1267		-
1268		- if (c0 > time * rps->power.up_threshold)
1269		- events = GEN6_PM_RP_UP_THRESHOLD;
1270		- else if (c0 < time * rps->power.down_threshold)
1271		- events = GEN6_PM_RP_DOWN_THRESHOLD;
1272		- }
1273		-
1274		- rps->ei = now;
1275		- return events;
1276		-}
1277		-
1278		-static void gen6_pm_rps_work(struct work_struct *work)
1279		-{
1280		- struct drm_i915_private *dev_priv =
1281		- container_of(work, struct drm_i915_private, gt_pm.rps.work);
1282		- struct intel_rps *rps = &dev_priv->gt_pm.rps;
1283		- bool client_boost = false;
1284		- int new_delay, adj, min, max;
1285		- u32 pm_iir = 0;
1286		-
1287		- spin_lock_irq(&dev_priv->irq_lock);
1288		- if (rps->interrupts_enabled) {
1289		- pm_iir = fetch_and_zero(&rps->pm_iir);
1290		- client_boost = atomic_read(&rps->num_waiters);
1291		- }
1292		- spin_unlock_irq(&dev_priv->irq_lock);
1293		-
1294		- /* Make sure we didn't queue anything we're not going to process. */
1295		- WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1296		- if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
1297		- goto out;
1298		-
1299		- mutex_lock(&dev_priv->pcu_lock);
1300		-
1301		- pm_iir \|= vlv_wa_c0_ei(dev_priv, pm_iir);
1302		-
1303		- adj = rps->last_adj;
1304		- new_delay = rps->cur_freq;
1305		- min = rps->min_freq_softlimit;
1306		- max = rps->max_freq_softlimit;
1307		- if (client_boost)
1308		- max = rps->max_freq;
1309		- if (client_boost && new_delay < rps->boost_freq) {
1310		- new_delay = rps->boost_freq;
1311		- adj = 0;
1312		- } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1313		- if (adj > 0)
1314		- adj *= 2;
1315		- else /* CHV needs even encode values */
1316		- adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
1317		-
1318		- if (new_delay >= rps->max_freq_softlimit)
1319		- adj = 0;
1320		- } else if (client_boost) {
1321		- adj = 0;
1322		- } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1323		- if (rps->cur_freq > rps->efficient_freq)
1324		- new_delay = rps->efficient_freq;
1325		- else if (rps->cur_freq > rps->min_freq_softlimit)
1326		- new_delay = rps->min_freq_softlimit;
1327		- adj = 0;
1328		- } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1329		- if (adj < 0)
1330		- adj *= 2;
1331		- else /* CHV needs even encode values */
1332		- adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
1333		-
1334		- if (new_delay <= rps->min_freq_softlimit)
1335		- adj = 0;
1336		- } else { /* unknown event */
1337		- adj = 0;
1338		- }
1339		-
1340		- rps->last_adj = adj;
1341		-
1342		- /* sysfs frequency interfaces may have snuck in while servicing the
1343		- * interrupt
1344		- */
1345		- new_delay += adj;
1346		- new_delay = clamp_t(int, new_delay, min, max);
1347		-
1348		- if (intel_set_rps(dev_priv, new_delay)) {
1349		- DRM_DEBUG_DRIVER("Failed to set new GPU frequency\n");
1350		- rps->last_adj = 0;
1351		- }
1352		-
1353		- mutex_unlock(&dev_priv->pcu_lock);
1354		-
1355		-out:
1356		- /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1357		- spin_lock_irq(&dev_priv->irq_lock);
1358		- if (rps->interrupts_enabled)
1359		- gen6_unmask_pm_irq(dev_priv, dev_priv->pm_rps_events);
1360		- spin_unlock_irq(&dev_priv->irq_lock);
1361		-}
1362		-
1363		-
1364	949	/**
1365		- * ivybridge_parity_work - Workqueue called when a parity error interrupt
	950	+ * ivb_parity_work - Workqueue called when a parity error interrupt
1366	951	* occurred.
1367	952	* @work: workqueue struct
1368	953	*
..	..	@@ -1370,14 +955,15 @@
1370	955	* this event, userspace should try to remap the bad rows since statistically
1371	956	* it is likely the same row is more likely to go bad again.
1372	957	*/
1373		-static void ivybridge_parity_work(struct work_struct *work)
	958	+static void ivb_parity_work(struct work_struct *work)
1374	959	{
1375	960	struct drm_i915_private *dev_priv =
1376	961	container_of(work, typeof(*dev_priv), l3_parity.error_work);
	962	+ struct intel_gt *gt = &dev_priv->gt;
1377	963	u32 error_status, row, bank, subbank;
1378	964	char *parity_event[6];
1379		- uint32_t misccpctl;
1380		- uint8_t slice = 0;
	965	+ u32 misccpctl;
	966	+ u8 slice = 0;
1381	967
1382	968	/* We must turn off DOP level clock gating to access the L3 registers.
1383	969	* In order to prevent a get/put style interface, acquire struct mutex
..	..	@@ -1386,7 +972,7 @@
1386	972	mutex_lock(&dev_priv->drm.struct_mutex);
1387	973
1388	974	/* If we've screwed up tracking, just let the interrupt fire again */
1389		- if (WARN_ON(!dev_priv->l3_parity.which_slice))
	975	+ if (drm_WARN_ON(&dev_priv->drm, !dev_priv->l3_parity.which_slice))
1390	976	goto out;
1391	977
1392	978	misccpctl = I915_READ(GEN7_MISCCPCTL);
..	..	@@ -1397,7 +983,8 @@
1397	983	i915_reg_t reg;
1398	984
1399	985	slice--;
1400		- if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv)))
	986	+ if (drm_WARN_ON_ONCE(&dev_priv->drm,
	987	+ slice >= NUM_L3_SLICES(dev_priv)))
1401	988	break;
1402	989
1403	990	dev_priv->l3_parity.which_slice &= ~(1<<slice);
..	..	@@ -1434,159 +1021,29 @@
1434	1021	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1435	1022
1436	1023	out:
1437		- WARN_ON(dev_priv->l3_parity.which_slice);
1438		- spin_lock_irq(&dev_priv->irq_lock);
1439		- gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1440		- spin_unlock_irq(&dev_priv->irq_lock);
	1024	+ drm_WARN_ON(&dev_priv->drm, dev_priv->l3_parity.which_slice);
	1025	+ spin_lock_irq(&gt->irq_lock);
	1026	+ gen5_gt_enable_irq(gt, GT_PARITY_ERROR(dev_priv));
	1027	+ spin_unlock_irq(&gt->irq_lock);
1441	1028
1442	1029	mutex_unlock(&dev_priv->drm.struct_mutex);
1443		-}
1444		-
1445		-static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv,
1446		- u32 iir)
1447		-{
1448		- if (!HAS_L3_DPF(dev_priv))
1449		- return;
1450		-
1451		- spin_lock(&dev_priv->irq_lock);
1452		- gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1453		- spin_unlock(&dev_priv->irq_lock);
1454		-
1455		- iir &= GT_PARITY_ERROR(dev_priv);
1456		- if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1457		- dev_priv->l3_parity.which_slice \|= 1 << 1;
1458		-
1459		- if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1460		- dev_priv->l3_parity.which_slice \|= 1 << 0;
1461		-
1462		- queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1463		-}
1464		-
1465		-static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv,
1466		- u32 gt_iir)
1467		-{
1468		- if (gt_iir & GT_RENDER_USER_INTERRUPT)
1469		- notify_ring(dev_priv->engine[RCS]);
1470		- if (gt_iir & ILK_BSD_USER_INTERRUPT)
1471		- notify_ring(dev_priv->engine[VCS]);
1472		-}
1473		-
1474		-static void snb_gt_irq_handler(struct drm_i915_private *dev_priv,
1475		- u32 gt_iir)
1476		-{
1477		- if (gt_iir & GT_RENDER_USER_INTERRUPT)
1478		- notify_ring(dev_priv->engine[RCS]);
1479		- if (gt_iir & GT_BSD_USER_INTERRUPT)
1480		- notify_ring(dev_priv->engine[VCS]);
1481		- if (gt_iir & GT_BLT_USER_INTERRUPT)
1482		- notify_ring(dev_priv->engine[BCS]);
1483		-
1484		- if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT \|
1485		- GT_BSD_CS_ERROR_INTERRUPT \|
1486		- GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1487		- DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1488		-
1489		- if (gt_iir & GT_PARITY_ERROR(dev_priv))
1490		- ivybridge_parity_error_irq_handler(dev_priv, gt_iir);
1491		-}
1492		-
1493		-static void
1494		-gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
1495		-{
1496		- bool tasklet = false;
1497		-
1498		- if (iir & GT_CONTEXT_SWITCH_INTERRUPT)
1499		- tasklet = true;
1500		-
1501		- if (iir & GT_RENDER_USER_INTERRUPT) {
1502		- notify_ring(engine);
1503		- tasklet \|= USES_GUC_SUBMISSION(engine->i915);
1504		- }
1505		-
1506		- if (tasklet)
1507		- tasklet_hi_schedule(&engine->execlists.tasklet);
1508		-}
1509		-
1510		-static void gen8_gt_irq_ack(struct drm_i915_private *i915,
1511		- u32 master_ctl, u32 gt_iir[4])
1512		-{
1513		- void __iomem * const regs = i915->regs;
1514		-
1515		-#define GEN8_GT_IRQS (GEN8_GT_RCS_IRQ \| \
1516		- GEN8_GT_BCS_IRQ \| \
1517		- GEN8_GT_VCS1_IRQ \| \
1518		- GEN8_GT_VCS2_IRQ \| \
1519		- GEN8_GT_VECS_IRQ \| \
1520		- GEN8_GT_PM_IRQ \| \
1521		- GEN8_GT_GUC_IRQ)
1522		-
1523		- if (master_ctl & (GEN8_GT_RCS_IRQ \| GEN8_GT_BCS_IRQ)) {
1524		- gt_iir[0] = raw_reg_read(regs, GEN8_GT_IIR(0));
1525		- if (likely(gt_iir[0]))
1526		- raw_reg_write(regs, GEN8_GT_IIR(0), gt_iir[0]);
1527		- }
1528		-
1529		- if (master_ctl & (GEN8_GT_VCS1_IRQ \| GEN8_GT_VCS2_IRQ)) {
1530		- gt_iir[1] = raw_reg_read(regs, GEN8_GT_IIR(1));
1531		- if (likely(gt_iir[1]))
1532		- raw_reg_write(regs, GEN8_GT_IIR(1), gt_iir[1]);
1533		- }
1534		-
1535		- if (master_ctl & (GEN8_GT_PM_IRQ \| GEN8_GT_GUC_IRQ)) {
1536		- gt_iir[2] = raw_reg_read(regs, GEN8_GT_IIR(2));
1537		- if (likely(gt_iir[2] & (i915->pm_rps_events \|
1538		- i915->pm_guc_events)))
1539		- raw_reg_write(regs, GEN8_GT_IIR(2),
1540		- gt_iir[2] & (i915->pm_rps_events \|
1541		- i915->pm_guc_events));
1542		- }
1543		-
1544		- if (master_ctl & GEN8_GT_VECS_IRQ) {
1545		- gt_iir[3] = raw_reg_read(regs, GEN8_GT_IIR(3));
1546		- if (likely(gt_iir[3]))
1547		- raw_reg_write(regs, GEN8_GT_IIR(3), gt_iir[3]);
1548		- }
1549		-}
1550		-
1551		-static void gen8_gt_irq_handler(struct drm_i915_private *i915,
1552		- u32 master_ctl, u32 gt_iir[4])
1553		-{
1554		- if (master_ctl & (GEN8_GT_RCS_IRQ \| GEN8_GT_BCS_IRQ)) {
1555		- gen8_cs_irq_handler(i915->engine[RCS],
1556		- gt_iir[0] >> GEN8_RCS_IRQ_SHIFT);
1557		- gen8_cs_irq_handler(i915->engine[BCS],
1558		- gt_iir[0] >> GEN8_BCS_IRQ_SHIFT);
1559		- }
1560		-
1561		- if (master_ctl & (GEN8_GT_VCS1_IRQ \| GEN8_GT_VCS2_IRQ)) {
1562		- gen8_cs_irq_handler(i915->engine[VCS],
1563		- gt_iir[1] >> GEN8_VCS1_IRQ_SHIFT);
1564		- gen8_cs_irq_handler(i915->engine[VCS2],
1565		- gt_iir[1] >> GEN8_VCS2_IRQ_SHIFT);
1566		- }
1567		-
1568		- if (master_ctl & GEN8_GT_VECS_IRQ) {
1569		- gen8_cs_irq_handler(i915->engine[VECS],
1570		- gt_iir[3] >> GEN8_VECS_IRQ_SHIFT);
1571		- }
1572		-
1573		- if (master_ctl & (GEN8_GT_PM_IRQ \| GEN8_GT_GUC_IRQ)) {
1574		- gen6_rps_irq_handler(i915, gt_iir[2]);
1575		- gen9_guc_irq_handler(i915, gt_iir[2]);
1576		- }
1577	1030	}
1578	1031
1579	1032	static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1580	1033	{
1581	1034	switch (pin) {
1582		- case HPD_PORT_C:
	1035	+ case HPD_PORT_TC1:
1583	1036	return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC1);
1584		- case HPD_PORT_D:
	1037	+ case HPD_PORT_TC2:
1585	1038	return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC2);
1586		- case HPD_PORT_E:
	1039	+ case HPD_PORT_TC3:
1587	1040	return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC3);
1588		- case HPD_PORT_F:
	1041	+ case HPD_PORT_TC4:
1589	1042	return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC4);
	1043	+ case HPD_PORT_TC5:
	1044	+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC5);
	1045	+ case HPD_PORT_TC6:
	1046	+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC6);
1590	1047	default:
1591	1048	return false;
1592	1049	}
..	..	@@ -1610,9 +1067,11 @@
1610	1067	{
1611	1068	switch (pin) {
1612	1069	case HPD_PORT_A:
1613		- return val & ICP_DDIA_HPD_LONG_DETECT;
	1070	+ return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_A);
1614	1071	case HPD_PORT_B:
1615		- return val & ICP_DDIB_HPD_LONG_DETECT;
	1072	+ return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_B);
	1073	+ case HPD_PORT_C:
	1074	+ return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_C);
1616	1075	default:
1617	1076	return false;
1618	1077	}
..	..	@@ -1621,14 +1080,18 @@
1621	1080	static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1622	1081	{
1623	1082	switch (pin) {
1624		- case HPD_PORT_C:
	1083	+ case HPD_PORT_TC1:
1625	1084	return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
1626		- case HPD_PORT_D:
	1085	+ case HPD_PORT_TC2:
1627	1086	return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
1628		- case HPD_PORT_E:
	1087	+ case HPD_PORT_TC3:
1629	1088	return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
1630		- case HPD_PORT_F:
	1089	+ case HPD_PORT_TC4:
1631	1090	return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
	1091	+ case HPD_PORT_TC5:
	1092	+ return val & ICP_TC_HPD_LONG_DETECT(PORT_TC5);
	1093	+ case HPD_PORT_TC6:
	1094	+ return val & ICP_TC_HPD_LONG_DETECT(PORT_TC6);
1632	1095	default:
1633	1096	return false;
1634	1097	}
..	..	@@ -1713,6 +1176,8 @@
1713	1176	{
1714	1177	enum hpd_pin pin;
1715	1178
	1179	+ BUILD_BUG_ON(BITS_PER_TYPE(*pin_mask) < HPD_NUM_PINS);
	1180	+
1716	1181	for_each_hpd_pin(pin) {
1717	1182	if ((hpd[pin] & hotplug_trigger) == 0)
1718	1183	continue;
..	..	@@ -1723,8 +1188,9 @@
1723	1188	*long_mask \|= BIT(pin);
1724	1189	}
1725	1190
1726		- DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x, long 0x%08x\n",
1727		- hotplug_trigger, dig_hotplug_reg, pin_mask, long_mask);
	1191	+ drm_dbg(&dev_priv->drm,
	1192	+ "hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x, long 0x%08x\n",
	1193	+ hotplug_trigger, dig_hotplug_reg, pin_mask, long_mask);
1728	1194
1729	1195	}
1730	1196
..	..	@@ -1741,13 +1207,15 @@
1741	1207	#if defined(CONFIG_DEBUG_FS)
1742	1208	static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1743	1209	enum pipe pipe,
1744		- uint32_t crc0, uint32_t crc1,
1745		- uint32_t crc2, uint32_t crc3,
1746		- uint32_t crc4)
	1210	+ u32 crc0, u32 crc1,
	1211	+ u32 crc2, u32 crc3,
	1212	+ u32 crc4)
1747	1213	{
1748		- struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1749	1214	struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1750		- uint32_t crcs[5];
	1215	+ struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
	1216	+ u32 crcs[5] = { crc0, crc1, crc2, crc3, crc4 };
	1217	+
	1218	+ trace_intel_pipe_crc(crtc, crcs);
1751	1219
1752	1220	spin_lock(&pipe_crc->lock);
1753	1221	/*
..	..	@@ -1766,11 +1234,6 @@
1766	1234	}
1767	1235	spin_unlock(&pipe_crc->lock);
1768	1236
1769		- crcs[0] = crc0;
1770		- crcs[1] = crc1;
1771		- crcs[2] = crc2;
1772		- crcs[3] = crc3;
1773		- crcs[4] = crc4;
1774	1237	drm_crtc_add_crc_entry(&crtc->base, true,
1775	1238	drm_crtc_accurate_vblank_count(&crtc->base),
1776	1239	crcs);
..	..	@@ -1779,9 +1242,9 @@
1779	1242	static inline void
1780	1243	display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1781	1244	enum pipe pipe,
1782		- uint32_t crc0, uint32_t crc1,
1783		- uint32_t crc2, uint32_t crc3,
1784		- uint32_t crc4) {}
	1245	+ u32 crc0, u32 crc1,
	1246	+ u32 crc2, u32 crc3,
	1247	+ u32 crc4) {}
1785	1248	#endif
1786	1249
1787	1250
..	..	@@ -1807,7 +1270,7 @@
1807	1270	static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1808	1271	enum pipe pipe)
1809	1272	{
1810		- uint32_t res1, res2;
	1273	+ u32 res1, res2;
1811	1274
1812	1275	if (INTEL_GEN(dev_priv) >= 3)
1813	1276	res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
..	..	@@ -1826,41 +1289,6 @@
1826	1289	res1, res2);
1827	1290	}
1828	1291
1829		-/* The RPS events need forcewake, so we add them to a work queue and mask their
1830		- * IMR bits until the work is done. Other interrupts can be processed without
1831		- * the work queue. */
1832		-static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1833		-{
1834		- struct intel_rps *rps = &dev_priv->gt_pm.rps;
1835		-
1836		- if (pm_iir & dev_priv->pm_rps_events) {
1837		- spin_lock(&dev_priv->irq_lock);
1838		- gen6_mask_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1839		- if (rps->interrupts_enabled) {
1840		- rps->pm_iir \|= pm_iir & dev_priv->pm_rps_events;
1841		- schedule_work(&rps->work);
1842		- }
1843		- spin_unlock(&dev_priv->irq_lock);
1844		- }
1845		-
1846		- if (INTEL_GEN(dev_priv) >= 8)
1847		- return;
1848		-
1849		- if (HAS_VEBOX(dev_priv)) {
1850		- if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1851		- notify_ring(dev_priv->engine[VECS]);
1852		-
1853		- if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1854		- DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
1855		- }
1856		-}
1857		-
1858		-static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir)
1859		-{
1860		- if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT)
1861		- intel_guc_to_host_event_handler(&dev_priv->guc);
1862		-}
1863		-
1864	1292	static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
1865	1293	{
1866	1294	enum pipe pipe;
..	..	@@ -1877,7 +1305,7 @@
1877	1305	static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
1878	1306	u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1879	1307	{
1880		- int pipe;
	1308	+ enum pipe pipe;
1881	1309
1882	1310	spin_lock(&dev_priv->irq_lock);
1883	1311
..	..	@@ -1902,6 +1330,7 @@
1902	1330	status_mask = PIPE_FIFO_UNDERRUN_STATUS;
1903	1331
1904	1332	switch (pipe) {
	1333	+ default:
1905	1334	case PIPE_A:
1906	1335	iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1907	1336	break;
..	..	@@ -1946,7 +1375,7 @@
1946	1375
1947	1376	for_each_pipe(dev_priv, pipe) {
1948	1377	if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1949		- drm_handle_vblank(&dev_priv->drm, pipe);
	1378	+ intel_handle_vblank(dev_priv, pipe);
1950	1379
1951	1380	if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1952	1381	i9xx_pipe_crc_irq_handler(dev_priv, pipe);
..	..	@@ -1964,7 +1393,7 @@
1964	1393
1965	1394	for_each_pipe(dev_priv, pipe) {
1966	1395	if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1967		- drm_handle_vblank(&dev_priv->drm, pipe);
	1396	+ intel_handle_vblank(dev_priv, pipe);
1968	1397
1969	1398	if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1970	1399	blc_event = true;
..	..	@@ -1988,7 +1417,7 @@
1988	1417
1989	1418	for_each_pipe(dev_priv, pipe) {
1990	1419	if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1991		- drm_handle_vblank(&dev_priv->drm, pipe);
	1420	+ intel_handle_vblank(dev_priv, pipe);
1992	1421
1993	1422	if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1994	1423	blc_event = true;
..	..	@@ -2014,7 +1443,7 @@
2014	1443
2015	1444	for_each_pipe(dev_priv, pipe) {
2016	1445	if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
2017		- drm_handle_vblank(&dev_priv->drm, pipe);
	1446	+ intel_handle_vblank(dev_priv, pipe);
2018	1447
2019	1448	if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
2020	1449	i9xx_pipe_crc_irq_handler(dev_priv, pipe);
..	..	@@ -2058,9 +1487,9 @@
2058	1487	I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2059	1488	}
2060	1489
2061		- WARN_ONCE(1,
2062		- "PORT_HOTPLUG_STAT did not clear (0x%08x)\n",
2063		- I915_READ(PORT_HOTPLUG_STAT));
	1490	+ drm_WARN_ONCE(&dev_priv->drm, 1,
	1491	+ "PORT_HOTPLUG_STAT did not clear (0x%08x)\n",
	1492	+ I915_READ(PORT_HOTPLUG_STAT));
2064	1493
2065	1494	return hotplug_status;
2066	1495	}
..	..	@@ -2069,46 +1498,39 @@
2069	1498	u32 hotplug_status)
2070	1499	{
2071	1500	u32 pin_mask = 0, long_mask = 0;
	1501	+ u32 hotplug_trigger;
2072	1502
2073		- if (IS_G4X(dev_priv) \|\| IS_VALLEYVIEW(dev_priv) \|\|
2074		- IS_CHERRYVIEW(dev_priv)) {
2075		- u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
	1503	+ if (IS_G4X(dev_priv) \|\|
	1504	+ IS_VALLEYVIEW(dev_priv) \|\| IS_CHERRYVIEW(dev_priv))
	1505	+ hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
	1506	+ else
	1507	+ hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
2076	1508
2077		- if (hotplug_trigger) {
2078		- intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2079		- hotplug_trigger, hotplug_trigger,
2080		- hpd_status_g4x,
2081		- i9xx_port_hotplug_long_detect);
	1509	+ if (hotplug_trigger) {
	1510	+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
	1511	+ hotplug_trigger, hotplug_trigger,
	1512	+ dev_priv->hotplug.hpd,
	1513	+ i9xx_port_hotplug_long_detect);
2082	1514
2083		- intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2084		- }
2085		-
2086		- if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
2087		- dp_aux_irq_handler(dev_priv);
2088		- } else {
2089		- u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
2090		-
2091		- if (hotplug_trigger) {
2092		- intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2093		- hotplug_trigger, hotplug_trigger,
2094		- hpd_status_i915,
2095		- i9xx_port_hotplug_long_detect);
2096		- intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2097		- }
	1515	+ intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2098	1516	}
	1517	+
	1518	+ if ((IS_G4X(dev_priv) \|\|
	1519	+ IS_VALLEYVIEW(dev_priv) \|\| IS_CHERRYVIEW(dev_priv)) &&
	1520	+ hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
	1521	+ dp_aux_irq_handler(dev_priv);
2099	1522	}
2100	1523
2101	1524	static irqreturn_t valleyview_irq_handler(int irq, void *arg)
2102	1525	{
2103		- struct drm_device *dev = arg;
2104		- struct drm_i915_private *dev_priv = to_i915(dev);
	1526	+ struct drm_i915_private *dev_priv = arg;
2105	1527	irqreturn_t ret = IRQ_NONE;
2106	1528
2107	1529	if (!intel_irqs_enabled(dev_priv))
2108	1530	return IRQ_NONE;
2109	1531
2110	1532	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
2111		- disable_rpm_wakeref_asserts(dev_priv);
	1533	+ disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2112	1534
2113	1535	do {
2114	1536	u32 iir, gt_iir, pm_iir;
..	..	@@ -2169,9 +1591,9 @@
2169	1591	I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2170	1592
2171	1593	if (gt_iir)
2172		- snb_gt_irq_handler(dev_priv, gt_iir);
	1594	+ gen6_gt_irq_handler(&dev_priv->gt, gt_iir);
2173	1595	if (pm_iir)
2174		- gen6_rps_irq_handler(dev_priv, pm_iir);
	1596	+ gen6_rps_irq_handler(&dev_priv->gt.rps, pm_iir);
2175	1597
2176	1598	if (hotplug_status)
2177	1599	i9xx_hpd_irq_handler(dev_priv, hotplug_status);
..	..	@@ -2179,28 +1601,26 @@
2179	1601	valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
2180	1602	} while (0);
2181	1603
2182		- enable_rpm_wakeref_asserts(dev_priv);
	1604	+ enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2183	1605
2184	1606	return ret;
2185	1607	}
2186	1608
2187	1609	static irqreturn_t cherryview_irq_handler(int irq, void *arg)
2188	1610	{
2189		- struct drm_device *dev = arg;
2190		- struct drm_i915_private *dev_priv = to_i915(dev);
	1611	+ struct drm_i915_private *dev_priv = arg;
2191	1612	irqreturn_t ret = IRQ_NONE;
2192	1613
2193	1614	if (!intel_irqs_enabled(dev_priv))
2194	1615	return IRQ_NONE;
2195	1616
2196	1617	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
2197		- disable_rpm_wakeref_asserts(dev_priv);
	1618	+ disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2198	1619
2199	1620	do {
2200	1621	u32 master_ctl, iir;
2201	1622	u32 pipe_stats[I915_MAX_PIPES] = {};
2202	1623	u32 hotplug_status = 0;
2203		- u32 gt_iir[4];
2204	1624	u32 ier = 0;
2205	1625
2206	1626	master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
..	..	@@ -2228,7 +1648,7 @@
2228	1648	ier = I915_READ(VLV_IER);
2229	1649	I915_WRITE(VLV_IER, 0);
2230	1650
2231		- gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
	1651	+ gen8_gt_irq_handler(&dev_priv->gt, master_ctl);
2232	1652
2233	1653	if (iir & I915_DISPLAY_PORT_INTERRUPT)
2234	1654	hotplug_status = i9xx_hpd_irq_ack(dev_priv);
..	..	@@ -2252,22 +1672,19 @@
2252	1672	I915_WRITE(VLV_IER, ier);
2253	1673	I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2254	1674
2255		- gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir);
2256		-
2257	1675	if (hotplug_status)
2258	1676	i9xx_hpd_irq_handler(dev_priv, hotplug_status);
2259	1677
2260	1678	valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
2261	1679	} while (0);
2262	1680
2263		- enable_rpm_wakeref_asserts(dev_priv);
	1681	+ enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2264	1682
2265	1683	return ret;
2266	1684	}
2267	1685
2268	1686	static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
2269		- u32 hotplug_trigger,
2270		- const u32 hpd[HPD_NUM_PINS])
	1687	+ u32 hotplug_trigger)
2271	1688	{
2272	1689	u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2273	1690
..	..	@@ -2290,8 +1707,9 @@
2290	1707	if (!hotplug_trigger)
2291	1708	return;
2292	1709
2293		- intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
2294		- dig_hotplug_reg, hpd,
	1710	+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
	1711	+ hotplug_trigger, dig_hotplug_reg,
	1712	+ dev_priv->hotplug.pch_hpd,
2295	1713	pch_port_hotplug_long_detect);
2296	1714
2297	1715	intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
..	..	@@ -2299,16 +1717,16 @@
2299	1717
2300	1718	static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2301	1719	{
2302		- int pipe;
	1720	+ enum pipe pipe;
2303	1721	u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
2304	1722
2305		- ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx);
	1723	+ ibx_hpd_irq_handler(dev_priv, hotplug_trigger);
2306	1724
2307	1725	if (pch_iir & SDE_AUDIO_POWER_MASK) {
2308	1726	int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
2309	1727	SDE_AUDIO_POWER_SHIFT);
2310		- DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
2311		- port_name(port));
	1728	+ drm_dbg(&dev_priv->drm, "PCH audio power change on port %d\n",
	1729	+ port_name(port));
2312	1730	}
2313	1731
2314	1732	if (pch_iir & SDE_AUX_MASK)
..	..	@@ -2318,25 +1736,27 @@
2318	1736	gmbus_irq_handler(dev_priv);
2319	1737
2320	1738	if (pch_iir & SDE_AUDIO_HDCP_MASK)
2321		- DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
	1739	+ drm_dbg(&dev_priv->drm, "PCH HDCP audio interrupt\n");
2322	1740
2323	1741	if (pch_iir & SDE_AUDIO_TRANS_MASK)
2324		- DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
	1742	+ drm_dbg(&dev_priv->drm, "PCH transcoder audio interrupt\n");
2325	1743
2326	1744	if (pch_iir & SDE_POISON)
2327		- DRM_ERROR("PCH poison interrupt\n");
	1745	+ drm_err(&dev_priv->drm, "PCH poison interrupt\n");
2328	1746
2329		- if (pch_iir & SDE_FDI_MASK)
	1747	+ if (pch_iir & SDE_FDI_MASK) {
2330	1748	for_each_pipe(dev_priv, pipe)
2331		- DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2332		- pipe_name(pipe),
2333		- I915_READ(FDI_RX_IIR(pipe)));
	1749	+ drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n",
	1750	+ pipe_name(pipe),
	1751	+ I915_READ(FDI_RX_IIR(pipe)));
	1752	+ }
2334	1753
2335	1754	if (pch_iir & (SDE_TRANSB_CRC_DONE \| SDE_TRANSA_CRC_DONE))
2336		- DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
	1755	+ drm_dbg(&dev_priv->drm, "PCH transcoder CRC done interrupt\n");
2337	1756
2338	1757	if (pch_iir & (SDE_TRANSB_CRC_ERR \| SDE_TRANSA_CRC_ERR))
2339		- DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
	1758	+ drm_dbg(&dev_priv->drm,
	1759	+ "PCH transcoder CRC error interrupt\n");
2340	1760
2341	1761	if (pch_iir & SDE_TRANSA_FIFO_UNDER)
2342	1762	intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A);
..	..	@@ -2351,7 +1771,7 @@
2351	1771	enum pipe pipe;
2352	1772
2353	1773	if (err_int & ERR_INT_POISON)
2354		- DRM_ERROR("Poison interrupt\n");
	1774	+ drm_err(&dev_priv->drm, "Poison interrupt\n");
2355	1775
2356	1776	for_each_pipe(dev_priv, pipe) {
2357	1777	if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
..	..	@@ -2374,7 +1794,7 @@
2374	1794	enum pipe pipe;
2375	1795
2376	1796	if (serr_int & SERR_INT_POISON)
2377		- DRM_ERROR("PCH poison interrupt\n");
	1797	+ drm_err(&dev_priv->drm, "PCH poison interrupt\n");
2378	1798
2379	1799	for_each_pipe(dev_priv, pipe)
2380	1800	if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe))
..	..	@@ -2385,16 +1805,16 @@
2385	1805
2386	1806	static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2387	1807	{
2388		- int pipe;
	1808	+ enum pipe pipe;
2389	1809	u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2390	1810
2391		- ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt);
	1811	+ ibx_hpd_irq_handler(dev_priv, hotplug_trigger);
2392	1812
2393	1813	if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2394	1814	int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2395	1815	SDE_AUDIO_POWER_SHIFT_CPT);
2396		- DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2397		- port_name(port));
	1816	+ drm_dbg(&dev_priv->drm, "PCH audio power change on port %c\n",
	1817	+ port_name(port));
2398	1818	}
2399	1819
2400	1820	if (pch_iir & SDE_AUX_MASK_CPT)
..	..	@@ -2404,16 +1824,17 @@
2404	1824	gmbus_irq_handler(dev_priv);
2405	1825
2406	1826	if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2407		- DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
	1827	+ drm_dbg(&dev_priv->drm, "Audio CP request interrupt\n");
2408	1828
2409	1829	if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2410		- DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
	1830	+ drm_dbg(&dev_priv->drm, "Audio CP change interrupt\n");
2411	1831
2412		- if (pch_iir & SDE_FDI_MASK_CPT)
	1832	+ if (pch_iir & SDE_FDI_MASK_CPT) {
2413	1833	for_each_pipe(dev_priv, pipe)
2414		- DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2415		- pipe_name(pipe),
2416		- I915_READ(FDI_RX_IIR(pipe)));
	1834	+ drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n",
	1835	+ pipe_name(pipe),
	1836	+ I915_READ(FDI_RX_IIR(pipe)));
	1837	+ }
2417	1838
2418	1839	if (pch_iir & SDE_ERROR_CPT)
2419	1840	cpt_serr_int_handler(dev_priv);
..	..	@@ -2421,9 +1842,26 @@
2421	1842
2422	1843	static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2423	1844	{
2424		- u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
2425		- u32 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
	1845	+ u32 ddi_hotplug_trigger, tc_hotplug_trigger;
2426	1846	u32 pin_mask = 0, long_mask = 0;
	1847	+
	1848	+ if (HAS_PCH_TGP(dev_priv)) {
	1849	+ ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
	1850	+ tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
	1851	+ } else if (HAS_PCH_JSP(dev_priv)) {
	1852	+ ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
	1853	+ tc_hotplug_trigger = 0;
	1854	+ } else if (HAS_PCH_MCC(dev_priv)) {
	1855	+ ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
	1856	+ tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(PORT_TC1);
	1857	+ } else {
	1858	+ drm_WARN(&dev_priv->drm, !HAS_PCH_ICP(dev_priv),
	1859	+ "Unrecognized PCH type 0x%x\n",
	1860	+ INTEL_PCH_TYPE(dev_priv));
	1861	+
	1862	+ ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
	1863	+ tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
	1864	+ }
2427	1865
2428	1866	if (ddi_hotplug_trigger) {
2429	1867	u32 dig_hotplug_reg;
..	..	@@ -2432,8 +1870,8 @@
2432	1870	I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg);
2433	1871
2434	1872	intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2435		- ddi_hotplug_trigger,
2436		- dig_hotplug_reg, hpd_icp,
	1873	+ ddi_hotplug_trigger, dig_hotplug_reg,
	1874	+ dev_priv->hotplug.pch_hpd,
2437	1875	icp_ddi_port_hotplug_long_detect);
2438	1876	}
2439	1877
..	..	@@ -2444,8 +1882,8 @@
2444	1882	I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg);
2445	1883
2446	1884	intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2447		- tc_hotplug_trigger,
2448		- dig_hotplug_reg, hpd_icp,
	1885	+ tc_hotplug_trigger, dig_hotplug_reg,
	1886	+ dev_priv->hotplug.pch_hpd,
2449	1887	icp_tc_port_hotplug_long_detect);
2450	1888	}
2451	1889
..	..	@@ -2470,7 +1908,8 @@
2470	1908	I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2471	1909
2472	1910	intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2473		- hotplug_trigger, dig_hotplug_reg, hpd_spt,
	1911	+ hotplug_trigger, dig_hotplug_reg,
	1912	+ dev_priv->hotplug.pch_hpd,
2474	1913	spt_port_hotplug_long_detect);
2475	1914	}
2476	1915
..	..	@@ -2481,7 +1920,8 @@
2481	1920	I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
2482	1921
2483	1922	intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2484		- hotplug2_trigger, dig_hotplug_reg, hpd_spt,
	1923	+ hotplug2_trigger, dig_hotplug_reg,
	1924	+ dev_priv->hotplug.pch_hpd,
2485	1925	spt_port_hotplug2_long_detect);
2486	1926	}
2487	1927
..	..	@@ -2493,16 +1933,16 @@
2493	1933	}
2494	1934
2495	1935	static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
2496		- u32 hotplug_trigger,
2497		- const u32 hpd[HPD_NUM_PINS])
	1936	+ u32 hotplug_trigger)
2498	1937	{
2499	1938	u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2500	1939
2501	1940	dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
2502	1941	I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
2503	1942
2504		- intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
2505		- dig_hotplug_reg, hpd,
	1943	+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
	1944	+ hotplug_trigger, dig_hotplug_reg,
	1945	+ dev_priv->hotplug.hpd,
2506	1946	ilk_port_hotplug_long_detect);
2507	1947
2508	1948	intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
..	..	@@ -2515,7 +1955,7 @@
2515	1955	u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2516	1956
2517	1957	if (hotplug_trigger)
2518		- ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk);
	1958	+ ilk_hpd_irq_handler(dev_priv, hotplug_trigger);
2519	1959
2520	1960	if (de_iir & DE_AUX_CHANNEL_A)
2521	1961	dp_aux_irq_handler(dev_priv);
..	..	@@ -2524,11 +1964,11 @@
2524	1964	intel_opregion_asle_intr(dev_priv);
2525	1965
2526	1966	if (de_iir & DE_POISON)
2527		- DRM_ERROR("Poison interrupt\n");
	1967	+ drm_err(&dev_priv->drm, "Poison interrupt\n");
2528	1968
2529	1969	for_each_pipe(dev_priv, pipe) {
2530	1970	if (de_iir & DE_PIPE_VBLANK(pipe))
2531		- drm_handle_vblank(&dev_priv->drm, pipe);
	1971	+ intel_handle_vblank(dev_priv, pipe);
2532	1972
2533	1973	if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2534	1974	intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
..	..	@@ -2550,8 +1990,8 @@
2550	1990	I915_WRITE(SDEIIR, pch_iir);
2551	1991	}
2552	1992
2553		- if (IS_GEN5(dev_priv) && de_iir & DE_PCU_EVENT)
2554		- ironlake_rps_change_irq_handler(dev_priv);
	1993	+ if (IS_GEN(dev_priv, 5) && de_iir & DE_PCU_EVENT)
	1994	+ gen5_rps_irq_handler(&dev_priv->gt.rps);
2555	1995	}
2556	1996
2557	1997	static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
..	..	@@ -2561,7 +2001,7 @@
2561	2001	u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2562	2002
2563	2003	if (hotplug_trigger)
2564		- ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb);
	2004	+ ilk_hpd_irq_handler(dev_priv, hotplug_trigger);
2565	2005
2566	2006	if (de_iir & DE_ERR_INT_IVB)
2567	2007	ivb_err_int_handler(dev_priv);
..	..	@@ -2581,7 +2021,7 @@
2581	2021
2582	2022	for_each_pipe(dev_priv, pipe) {
2583	2023	if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
2584		- drm_handle_vblank(&dev_priv->drm, pipe);
	2024	+ intel_handle_vblank(dev_priv, pipe);
2585	2025	}
2586	2026
2587	2027	/* check event from PCH */
..	..	@@ -2603,85 +2043,85 @@
2603	2043	* 4 - Process the interrupt(s) that had bits set in the IIRs.
2604	2044	* 5 - Re-enable Master Interrupt Control.
2605	2045	*/
2606		-static irqreturn_t ironlake_irq_handler(int irq, void *arg)
	2046	+static irqreturn_t ilk_irq_handler(int irq, void *arg)
2607	2047	{
2608		- struct drm_device *dev = arg;
2609		- struct drm_i915_private *dev_priv = to_i915(dev);
	2048	+ struct drm_i915_private *i915 = arg;
	2049	+ void __iomem * const regs = i915->uncore.regs;
2610	2050	u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2611	2051	irqreturn_t ret = IRQ_NONE;
2612	2052
2613		- if (!intel_irqs_enabled(dev_priv))
	2053	+ if (unlikely(!intel_irqs_enabled(i915)))
2614	2054	return IRQ_NONE;
2615	2055
2616	2056	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
2617		- disable_rpm_wakeref_asserts(dev_priv);
	2057	+ disable_rpm_wakeref_asserts(&i915->runtime_pm);
2618	2058
2619	2059	/* disable master interrupt before clearing iir */
2620		- de_ier = I915_READ(DEIER);
2621		- I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
	2060	+ de_ier = raw_reg_read(regs, DEIER);
	2061	+ raw_reg_write(regs, DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2622	2062
2623	2063	/* Disable south interrupts. We'll only write to SDEIIR once, so further
2624	2064	* interrupts will will be stored on its back queue, and then we'll be
2625	2065	* able to process them after we restore SDEIER (as soon as we restore
2626	2066	* it, we'll get an interrupt if SDEIIR still has something to process
2627	2067	* due to its back queue). */
2628		- if (!HAS_PCH_NOP(dev_priv)) {
2629		- sde_ier = I915_READ(SDEIER);
2630		- I915_WRITE(SDEIER, 0);
	2068	+ if (!HAS_PCH_NOP(i915)) {
	2069	+ sde_ier = raw_reg_read(regs, SDEIER);
	2070	+ raw_reg_write(regs, SDEIER, 0);
2631	2071	}
2632	2072
2633	2073	/* Find, clear, then process each source of interrupt */
2634	2074
2635		- gt_iir = I915_READ(GTIIR);
	2075	+ gt_iir = raw_reg_read(regs, GTIIR);
2636	2076	if (gt_iir) {
2637		- I915_WRITE(GTIIR, gt_iir);
2638		- ret = IRQ_HANDLED;
2639		- if (INTEL_GEN(dev_priv) >= 6)
2640		- snb_gt_irq_handler(dev_priv, gt_iir);
	2077	+ raw_reg_write(regs, GTIIR, gt_iir);
	2078	+ if (INTEL_GEN(i915) >= 6)
	2079	+ gen6_gt_irq_handler(&i915->gt, gt_iir);
2641	2080	else
2642		- ilk_gt_irq_handler(dev_priv, gt_iir);
	2081	+ gen5_gt_irq_handler(&i915->gt, gt_iir);
	2082	+ ret = IRQ_HANDLED;
2643	2083	}
2644	2084
2645		- de_iir = I915_READ(DEIIR);
	2085	+ de_iir = raw_reg_read(regs, DEIIR);
2646	2086	if (de_iir) {
2647		- I915_WRITE(DEIIR, de_iir);
2648		- ret = IRQ_HANDLED;
2649		- if (INTEL_GEN(dev_priv) >= 7)
2650		- ivb_display_irq_handler(dev_priv, de_iir);
	2087	+ raw_reg_write(regs, DEIIR, de_iir);
	2088	+ if (INTEL_GEN(i915) >= 7)
	2089	+ ivb_display_irq_handler(i915, de_iir);
2651	2090	else
2652		- ilk_display_irq_handler(dev_priv, de_iir);
	2091	+ ilk_display_irq_handler(i915, de_iir);
	2092	+ ret = IRQ_HANDLED;
2653	2093	}
2654	2094
2655		- if (INTEL_GEN(dev_priv) >= 6) {
2656		- u32 pm_iir = I915_READ(GEN6_PMIIR);
	2095	+ if (INTEL_GEN(i915) >= 6) {
	2096	+ u32 pm_iir = raw_reg_read(regs, GEN6_PMIIR);
2657	2097	if (pm_iir) {
2658		- I915_WRITE(GEN6_PMIIR, pm_iir);
	2098	+ raw_reg_write(regs, GEN6_PMIIR, pm_iir);
	2099	+ gen6_rps_irq_handler(&i915->gt.rps, pm_iir);
2659	2100	ret = IRQ_HANDLED;
2660		- gen6_rps_irq_handler(dev_priv, pm_iir);
2661	2101	}
2662	2102	}
2663	2103
2664		- I915_WRITE(DEIER, de_ier);
2665		- if (!HAS_PCH_NOP(dev_priv))
2666		- I915_WRITE(SDEIER, sde_ier);
	2104	+ raw_reg_write(regs, DEIER, de_ier);
	2105	+ if (sde_ier)
	2106	+ raw_reg_write(regs, SDEIER, sde_ier);
2667	2107
2668	2108	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
2669		- enable_rpm_wakeref_asserts(dev_priv);
	2109	+ enable_rpm_wakeref_asserts(&i915->runtime_pm);
2670	2110
2671	2111	return ret;
2672	2112	}
2673	2113
2674	2114	static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
2675		- u32 hotplug_trigger,
2676		- const u32 hpd[HPD_NUM_PINS])
	2115	+ u32 hotplug_trigger)
2677	2116	{
2678	2117	u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2679	2118
2680	2119	dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2681	2120	I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2682	2121
2683		- intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
2684		- dig_hotplug_reg, hpd,
	2122	+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
	2123	+ hotplug_trigger, dig_hotplug_reg,
	2124	+ dev_priv->hotplug.hpd,
2685	2125	bxt_port_hotplug_long_detect);
2686	2126
2687	2127	intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
..	..	@@ -2699,8 +2139,9 @@
2699	2139	dig_hotplug_reg = I915_READ(GEN11_TC_HOTPLUG_CTL);
2700	2140	I915_WRITE(GEN11_TC_HOTPLUG_CTL, dig_hotplug_reg);
2701	2141
2702		- intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tc,
2703		- dig_hotplug_reg, hpd_gen11,
	2142	+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
	2143	+ trigger_tc, dig_hotplug_reg,
	2144	+ dev_priv->hotplug.hpd,
2704	2145	gen11_port_hotplug_long_detect);
2705	2146	}
2706	2147
..	..	@@ -2710,15 +2151,92 @@
2710	2151	dig_hotplug_reg = I915_READ(GEN11_TBT_HOTPLUG_CTL);
2711	2152	I915_WRITE(GEN11_TBT_HOTPLUG_CTL, dig_hotplug_reg);
2712	2153
2713		- intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tbt,
2714		- dig_hotplug_reg, hpd_gen11,
	2154	+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
	2155	+ trigger_tbt, dig_hotplug_reg,
	2156	+ dev_priv->hotplug.hpd,
2715	2157	gen11_port_hotplug_long_detect);
2716	2158	}
2717	2159
2718	2160	if (pin_mask)
2719	2161	intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2720	2162	else
2721		- DRM_ERROR("Unexpected DE HPD interrupt 0x%08x\n", iir);
	2163	+ drm_err(&dev_priv->drm,
	2164	+ "Unexpected DE HPD interrupt 0x%08x\n", iir);
	2165	+}
	2166	+
	2167	+static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
	2168	+{
	2169	+ u32 mask;
	2170	+
	2171	+ if (INTEL_GEN(dev_priv) >= 12)
	2172	+ return TGL_DE_PORT_AUX_DDIA \|
	2173	+ TGL_DE_PORT_AUX_DDIB \|
	2174	+ TGL_DE_PORT_AUX_DDIC \|
	2175	+ TGL_DE_PORT_AUX_USBC1 \|
	2176	+ TGL_DE_PORT_AUX_USBC2 \|
	2177	+ TGL_DE_PORT_AUX_USBC3 \|
	2178	+ TGL_DE_PORT_AUX_USBC4 \|
	2179	+ TGL_DE_PORT_AUX_USBC5 \|
	2180	+ TGL_DE_PORT_AUX_USBC6;
	2181	+
	2182	+
	2183	+ mask = GEN8_AUX_CHANNEL_A;
	2184	+ if (INTEL_GEN(dev_priv) >= 9)
	2185	+ mask \|= GEN9_AUX_CHANNEL_B \|
	2186	+ GEN9_AUX_CHANNEL_C \|
	2187	+ GEN9_AUX_CHANNEL_D;
	2188	+
	2189	+ if (IS_CNL_WITH_PORT_F(dev_priv) \|\| IS_GEN(dev_priv, 11))
	2190	+ mask \|= CNL_AUX_CHANNEL_F;
	2191	+
	2192	+ if (IS_GEN(dev_priv, 11))
	2193	+ mask \|= ICL_AUX_CHANNEL_E;
	2194	+
	2195	+ return mask;
	2196	+}
	2197	+
	2198	+static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
	2199	+{
	2200	+ if (IS_ROCKETLAKE(dev_priv))
	2201	+ return RKL_DE_PIPE_IRQ_FAULT_ERRORS;
	2202	+ else if (INTEL_GEN(dev_priv) >= 11)
	2203	+ return GEN11_DE_PIPE_IRQ_FAULT_ERRORS;
	2204	+ else if (INTEL_GEN(dev_priv) >= 9)
	2205	+ return GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
	2206	+ else
	2207	+ return GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
	2208	+}
	2209	+
	2210	+static void
	2211	+gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
	2212	+{
	2213	+ bool found = false;
	2214	+
	2215	+ if (iir & GEN8_DE_MISC_GSE) {
	2216	+ intel_opregion_asle_intr(dev_priv);
	2217	+ found = true;
	2218	+ }
	2219	+
	2220	+ if (iir & GEN8_DE_EDP_PSR) {
	2221	+ u32 psr_iir;
	2222	+ i915_reg_t iir_reg;
	2223	+
	2224	+ if (INTEL_GEN(dev_priv) >= 12)
	2225	+ iir_reg = TRANS_PSR_IIR(dev_priv->psr.transcoder);
	2226	+ else
	2227	+ iir_reg = EDP_PSR_IIR;
	2228	+
	2229	+ psr_iir = I915_READ(iir_reg);
	2230	+ I915_WRITE(iir_reg, psr_iir);
	2231	+
	2232	+ if (psr_iir)
	2233	+ found = true;
	2234	+
	2235	+ intel_psr_irq_handler(dev_priv, psr_iir);
	2236	+ }
	2237	+
	2238	+ if (!found)
	2239	+ drm_err(&dev_priv->drm, "Unexpected DE Misc interrupt\n");
2722	2240	}
2723	2241
2724	2242	static irqreturn_t
..	..	@@ -2731,29 +2249,13 @@
2731	2249	if (master_ctl & GEN8_DE_MISC_IRQ) {
2732	2250	iir = I915_READ(GEN8_DE_MISC_IIR);
2733	2251	if (iir) {
2734		- bool found = false;
2735		-
2736	2252	I915_WRITE(GEN8_DE_MISC_IIR, iir);
2737	2253	ret = IRQ_HANDLED;
2738		-
2739		- if (iir & GEN8_DE_MISC_GSE) {
2740		- intel_opregion_asle_intr(dev_priv);
2741		- found = true;
2742		- }
2743		-
2744		- if (iir & GEN8_DE_EDP_PSR) {
2745		- u32 psr_iir = I915_READ(EDP_PSR_IIR);
2746		-
2747		- intel_psr_irq_handler(dev_priv, psr_iir);
2748		- I915_WRITE(EDP_PSR_IIR, psr_iir);
2749		- found = true;
2750		- }
2751		-
2752		- if (!found)
2753		- DRM_ERROR("Unexpected DE Misc interrupt\n");
	2254	+ gen8_de_misc_irq_handler(dev_priv, iir);
	2255	+ } else {
	2256	+ drm_err(&dev_priv->drm,
	2257	+ "The master control interrupt lied (DE MISC)!\n");
2754	2258	}
2755		- else
2756		- DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2757	2259	}
2758	2260
2759	2261	if (INTEL_GEN(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) {
..	..	@@ -2763,7 +2265,8 @@
2763	2265	ret = IRQ_HANDLED;
2764	2266	gen11_hpd_irq_handler(dev_priv, iir);
2765	2267	} else {
2766		- DRM_ERROR("The master control interrupt lied, (DE HPD)!\n");
	2268	+ drm_err(&dev_priv->drm,
	2269	+ "The master control interrupt lied, (DE HPD)!\n");
2767	2270	}
2768	2271	}
2769	2272
..	..	@@ -2776,20 +2279,7 @@
2776	2279	I915_WRITE(GEN8_DE_PORT_IIR, iir);
2777	2280	ret = IRQ_HANDLED;
2778	2281
2779		- tmp_mask = GEN8_AUX_CHANNEL_A;
2780		- if (INTEL_GEN(dev_priv) >= 9)
2781		- tmp_mask \|= GEN9_AUX_CHANNEL_B \|
2782		- GEN9_AUX_CHANNEL_C \|
2783		- GEN9_AUX_CHANNEL_D;
2784		-
2785		- if (INTEL_GEN(dev_priv) >= 11)
2786		- tmp_mask \|= ICL_AUX_CHANNEL_E;
2787		-
2788		- if (IS_CNL_WITH_PORT_F(dev_priv) \|\|
2789		- INTEL_GEN(dev_priv) >= 11)
2790		- tmp_mask \|= CNL_AUX_CHANNEL_F;
2791		-
2792		- if (iir & tmp_mask) {
	2282	+ if (iir & gen8_de_port_aux_mask(dev_priv)) {
2793	2283	dp_aux_irq_handler(dev_priv);
2794	2284	found = true;
2795	2285	}
..	..	@@ -2797,15 +2287,13 @@
2797	2287	if (IS_GEN9_LP(dev_priv)) {
2798	2288	tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
2799	2289	if (tmp_mask) {
2800		- bxt_hpd_irq_handler(dev_priv, tmp_mask,
2801		- hpd_bxt);
	2290	+ bxt_hpd_irq_handler(dev_priv, tmp_mask);
2802	2291	found = true;
2803	2292	}
2804	2293	} else if (IS_BROADWELL(dev_priv)) {
2805	2294	tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
2806	2295	if (tmp_mask) {
2807		- ilk_hpd_irq_handler(dev_priv,
2808		- tmp_mask, hpd_bdw);
	2296	+ ilk_hpd_irq_handler(dev_priv, tmp_mask);
2809	2297	found = true;
2810	2298	}
2811	2299	}
..	..	@@ -2816,10 +2304,12 @@
2816	2304	}
2817	2305
2818	2306	if (!found)
2819		- DRM_ERROR("Unexpected DE Port interrupt\n");
	2307	+ drm_err(&dev_priv->drm,
	2308	+ "Unexpected DE Port interrupt\n");
2820	2309	}
2821	2310	else
2822		- DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
	2311	+ drm_err(&dev_priv->drm,
	2312	+ "The master control interrupt lied (DE PORT)!\n");
2823	2313	}
2824	2314
2825	2315	for_each_pipe(dev_priv, pipe) {
..	..	@@ -2830,7 +2320,8 @@
2830	2320
2831	2321	iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2832	2322	if (!iir) {
2833		- DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
	2323	+ drm_err(&dev_priv->drm,
	2324	+ "The master control interrupt lied (DE PIPE)!\n");
2834	2325	continue;
2835	2326	}
2836	2327
..	..	@@ -2838,7 +2329,7 @@
2838	2329	I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2839	2330
2840	2331	if (iir & GEN8_PIPE_VBLANK)
2841		- drm_handle_vblank(&dev_priv->drm, pipe);
	2332	+ intel_handle_vblank(dev_priv, pipe);
2842	2333
2843	2334	if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2844	2335	hsw_pipe_crc_irq_handler(dev_priv, pipe);
..	..	@@ -2846,16 +2337,12 @@
2846	2337	if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2847	2338	intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2848	2339
2849		- fault_errors = iir;
2850		- if (INTEL_GEN(dev_priv) >= 9)
2851		- fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2852		- else
2853		- fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2854		-
	2340	+ fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv);
2855	2341	if (fault_errors)
2856		- DRM_ERROR("Fault errors on pipe %c: 0x%08x\n",
2857		- pipe_name(pipe),
2858		- fault_errors);
	2342	+ drm_err(&dev_priv->drm,
	2343	+ "Fault errors on pipe %c: 0x%08x\n",
	2344	+ pipe_name(pipe),
	2345	+ fault_errors);
2859	2346	}
2860	2347
2861	2348	if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
..	..	@@ -2870,11 +2357,9 @@
2870	2357	I915_WRITE(SDEIIR, iir);
2871	2358	ret = IRQ_HANDLED;
2872	2359
2873		- if (HAS_PCH_ICP(dev_priv))
	2360	+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2874	2361	icp_irq_handler(dev_priv, iir);
2875		- else if (HAS_PCH_SPT(dev_priv) \|\|
2876		- HAS_PCH_KBP(dev_priv) \|\|
2877		- HAS_PCH_CNP(dev_priv))
	2362	+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
2878	2363	spt_irq_handler(dev_priv, iir);
2879	2364	else
2880	2365	cpt_irq_handler(dev_priv, iir);
..	..	@@ -2883,218 +2368,66 @@
2883	2368	* Like on previous PCH there seems to be something
2884	2369	* fishy going on with forwarding PCH interrupts.
2885	2370	*/
2886		- DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
	2371	+ drm_dbg(&dev_priv->drm,
	2372	+ "The master control interrupt lied (SDE)!\n");
2887	2373	}
2888	2374	}
2889	2375
2890	2376	return ret;
2891	2377	}
2892	2378
	2379	+static inline u32 gen8_master_intr_disable(void __iomem * const regs)
	2380	+{
	2381	+ raw_reg_write(regs, GEN8_MASTER_IRQ, 0);
	2382	+
	2383	+ /*
	2384	+ * Now with master disabled, get a sample of level indications
	2385	+ * for this interrupt. Indications will be cleared on related acks.
	2386	+ * New indications can and will light up during processing,
	2387	+ * and will generate new interrupt after enabling master.
	2388	+ */
	2389	+ return raw_reg_read(regs, GEN8_MASTER_IRQ);
	2390	+}
	2391	+
	2392	+static inline void gen8_master_intr_enable(void __iomem * const regs)
	2393	+{
	2394	+ raw_reg_write(regs, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
	2395	+}
	2396	+
2893	2397	static irqreturn_t gen8_irq_handler(int irq, void *arg)
2894	2398	{
2895		- struct drm_i915_private *dev_priv = to_i915(arg);
	2399	+ struct drm_i915_private *dev_priv = arg;
	2400	+ void __iomem * const regs = dev_priv->uncore.regs;
2896	2401	u32 master_ctl;
2897		- u32 gt_iir[4];
2898	2402
2899	2403	if (!intel_irqs_enabled(dev_priv))
2900	2404	return IRQ_NONE;
2901	2405
2902		- master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
2903		- master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2904		- if (!master_ctl)
	2406	+ master_ctl = gen8_master_intr_disable(regs);
	2407	+ if (!master_ctl) {
	2408	+ gen8_master_intr_enable(regs);
2905	2409	return IRQ_NONE;
	2410	+ }
2906	2411
2907		- I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
2908		-
2909		- /* Find, clear, then process each source of interrupt */
2910		- gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
	2412	+ /* Find, queue (onto bottom-halves), then clear each source */
	2413	+ gen8_gt_irq_handler(&dev_priv->gt, master_ctl);
2911	2414
2912	2415	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
2913	2416	if (master_ctl & ~GEN8_GT_IRQS) {
2914		- disable_rpm_wakeref_asserts(dev_priv);
	2417	+ disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2915	2418	gen8_de_irq_handler(dev_priv, master_ctl);
2916		- enable_rpm_wakeref_asserts(dev_priv);
	2419	+ enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2917	2420	}
2918	2421
2919		- I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2920		-
2921		- gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir);
	2422	+ gen8_master_intr_enable(regs);
2922	2423
2923	2424	return IRQ_HANDLED;
2924	2425	}
2925	2426
2926		-struct wedge_me {
2927		- struct delayed_work work;
2928		- struct drm_i915_private *i915;
2929		- const char *name;
2930		-};
2931		-
2932		-static void wedge_me(struct work_struct *work)
2933		-{
2934		- struct wedge_me w = container_of(work, typeof(w), work.work);
2935		-
2936		- dev_err(w->i915->drm.dev,
2937		- "%s timed out, cancelling all in-flight rendering.\n",
2938		- w->name);
2939		- i915_gem_set_wedged(w->i915);
2940		-}
2941		-
2942		-static void __init_wedge(struct wedge_me *w,
2943		- struct drm_i915_private *i915,
2944		- long timeout,
2945		- const char *name)
2946		-{
2947		- w->i915 = i915;
2948		- w->name = name;
2949		-
2950		- INIT_DELAYED_WORK_ONSTACK(&w->work, wedge_me);
2951		- schedule_delayed_work(&w->work, timeout);
2952		-}
2953		-
2954		-static void __fini_wedge(struct wedge_me *w)
2955		-{
2956		- cancel_delayed_work_sync(&w->work);
2957		- destroy_delayed_work_on_stack(&w->work);
2958		- w->i915 = NULL;
2959		-}
2960		-
2961		-#define i915_wedge_on_timeout(W, DEV, TIMEOUT) \
2962		- for (__init_wedge((W), (DEV), (TIMEOUT), __func__); \
2963		- (W)->i915; \
2964		- __fini_wedge((W)))
2965		-
2966	2427	static u32
2967		-gen11_gt_engine_identity(struct drm_i915_private * const i915,
2968		- const unsigned int bank, const unsigned int bit)
	2428	+gen11_gu_misc_irq_ack(struct intel_gt *gt, const u32 master_ctl)
2969	2429	{
2970		- void __iomem * const regs = i915->regs;
2971		- u32 timeout_ts;
2972		- u32 ident;
2973		-
2974		- lockdep_assert_held(&i915->irq_lock);
2975		-
2976		- raw_reg_write(regs, GEN11_IIR_REG_SELECTOR(bank), BIT(bit));
2977		-
2978		- /*
2979		- * NB: Specs do not specify how long to spin wait,
2980		- * so we do ~100us as an educated guess.
2981		- */
2982		- timeout_ts = (local_clock() >> 10) + 100;
2983		- do {
2984		- ident = raw_reg_read(regs, GEN11_INTR_IDENTITY_REG(bank));
2985		- } while (!(ident & GEN11_INTR_DATA_VALID) &&
2986		- !time_after32(local_clock() >> 10, timeout_ts));
2987		-
2988		- if (unlikely(!(ident & GEN11_INTR_DATA_VALID))) {
2989		- DRM_ERROR("INTR_IDENTITY_REG%u:%u 0x%08x not valid!\n",
2990		- bank, bit, ident);
2991		- return 0;
2992		- }
2993		-
2994		- raw_reg_write(regs, GEN11_INTR_IDENTITY_REG(bank),
2995		- GEN11_INTR_DATA_VALID);
2996		-
2997		- return ident;
2998		-}
2999		-
3000		-static void
3001		-gen11_other_irq_handler(struct drm_i915_private * const i915,
3002		- const u8 instance, const u16 iir)
3003		-{
3004		- if (instance == OTHER_GTPM_INSTANCE)
3005		- return gen6_rps_irq_handler(i915, iir);
3006		-
3007		- WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
3008		- instance, iir);
3009		-}
3010		-
3011		-static void
3012		-gen11_engine_irq_handler(struct drm_i915_private * const i915,
3013		- const u8 class, const u8 instance, const u16 iir)
3014		-{
3015		- struct intel_engine_cs *engine;
3016		-
3017		- if (instance <= MAX_ENGINE_INSTANCE)
3018		- engine = i915->engine_class[class][instance];
3019		- else
3020		- engine = NULL;
3021		-
3022		- if (likely(engine))
3023		- return gen8_cs_irq_handler(engine, iir);
3024		-
3025		- WARN_ONCE(1, "unhandled engine interrupt class=0x%x, instance=0x%x\n",
3026		- class, instance);
3027		-}
3028		-
3029		-static void
3030		-gen11_gt_identity_handler(struct drm_i915_private * const i915,
3031		- const u32 identity)
3032		-{
3033		- const u8 class = GEN11_INTR_ENGINE_CLASS(identity);
3034		- const u8 instance = GEN11_INTR_ENGINE_INSTANCE(identity);
3035		- const u16 intr = GEN11_INTR_ENGINE_INTR(identity);
3036		-
3037		- if (unlikely(!intr))
3038		- return;
3039		-
3040		- if (class <= COPY_ENGINE_CLASS)
3041		- return gen11_engine_irq_handler(i915, class, instance, intr);
3042		-
3043		- if (class == OTHER_CLASS)
3044		- return gen11_other_irq_handler(i915, instance, intr);
3045		-
3046		- WARN_ONCE(1, "unknown interrupt class=0x%x, instance=0x%x, intr=0x%x\n",
3047		- class, instance, intr);
3048		-}
3049		-
3050		-static void
3051		-gen11_gt_bank_handler(struct drm_i915_private * const i915,
3052		- const unsigned int bank)
3053		-{
3054		- void __iomem * const regs = i915->regs;
3055		- unsigned long intr_dw;
3056		- unsigned int bit;
3057		-
3058		- lockdep_assert_held(&i915->irq_lock);
3059		-
3060		- intr_dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
3061		-
3062		- if (unlikely(!intr_dw)) {
3063		- DRM_ERROR("GT_INTR_DW%u blank!\n", bank);
3064		- return;
3065		- }
3066		-
3067		- for_each_set_bit(bit, &intr_dw, 32) {
3068		- const u32 ident = gen11_gt_engine_identity(i915,
3069		- bank, bit);
3070		-
3071		- gen11_gt_identity_handler(i915, ident);
3072		- }
3073		-
3074		- /* Clear must be after shared has been served for engine */
3075		- raw_reg_write(regs, GEN11_GT_INTR_DW(bank), intr_dw);
3076		-}
3077		-
3078		-static void
3079		-gen11_gt_irq_handler(struct drm_i915_private * const i915,
3080		- const u32 master_ctl)
3081		-{
3082		- unsigned int bank;
3083		-
3084		- spin_lock(&i915->irq_lock);
3085		-
3086		- for (bank = 0; bank < 2; bank++) {
3087		- if (master_ctl & GEN11_GT_DW_IRQ(bank))
3088		- gen11_gt_bank_handler(i915, bank);
3089		- }
3090		-
3091		- spin_unlock(&i915->irq_lock);
3092		-}
3093		-
3094		-static u32
3095		-gen11_gu_misc_irq_ack(struct drm_i915_private *dev_priv, const u32 master_ctl)
3096		-{
3097		- void __iomem * const regs = dev_priv->regs;
	2430	+ void __iomem * const regs = gt->uncore->regs;
3098	2431	u32 iir;
3099	2432
3100	2433	if (!(master_ctl & GEN11_GU_MISC_IRQ))
..	..	@@ -3108,242 +2441,138 @@
3108	2441	}
3109	2442
3110	2443	static void
3111		-gen11_gu_misc_irq_handler(struct drm_i915_private *dev_priv, const u32 iir)
	2444	+gen11_gu_misc_irq_handler(struct intel_gt *gt, const u32 iir)
3112	2445	{
3113	2446	if (iir & GEN11_GU_MISC_GSE)
3114		- intel_opregion_asle_intr(dev_priv);
	2447	+ intel_opregion_asle_intr(gt->i915);
3115	2448	}
3116	2449
3117		-static irqreturn_t gen11_irq_handler(int irq, void *arg)
	2450	+static inline u32 gen11_master_intr_disable(void __iomem * const regs)
3118	2451	{
3119		- struct drm_i915_private * const i915 = to_i915(arg);
3120		- void __iomem * const regs = i915->regs;
	2452	+ raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, 0);
	2453	+
	2454	+ /*
	2455	+ * Now with master disabled, get a sample of level indications
	2456	+ * for this interrupt. Indications will be cleared on related acks.
	2457	+ * New indications can and will light up during processing,
	2458	+ * and will generate new interrupt after enabling master.
	2459	+ */
	2460	+ return raw_reg_read(regs, GEN11_GFX_MSTR_IRQ);
	2461	+}
	2462	+
	2463	+static inline void gen11_master_intr_enable(void __iomem * const regs)
	2464	+{
	2465	+ raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
	2466	+}
	2467	+
	2468	+static void
	2469	+gen11_display_irq_handler(struct drm_i915_private *i915)
	2470	+{
	2471	+ void __iomem * const regs = i915->uncore.regs;
	2472	+ const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL);
	2473	+
	2474	+ disable_rpm_wakeref_asserts(&i915->runtime_pm);
	2475	+ /*
	2476	+ * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ
	2477	+ * for the display related bits.
	2478	+ */
	2479	+ raw_reg_write(regs, GEN11_DISPLAY_INT_CTL, 0x0);
	2480	+ gen8_de_irq_handler(i915, disp_ctl);
	2481	+ raw_reg_write(regs, GEN11_DISPLAY_INT_CTL,
	2482	+ GEN11_DISPLAY_IRQ_ENABLE);
	2483	+
	2484	+ enable_rpm_wakeref_asserts(&i915->runtime_pm);
	2485	+}
	2486	+
	2487	+static __always_inline irqreturn_t
	2488	+__gen11_irq_handler(struct drm_i915_private * const i915,
	2489	+ u32 (intr_disable)(void __iomem const regs),
	2490	+ void (intr_enable)(void __iomem const regs))
	2491	+{
	2492	+ void __iomem * const regs = i915->uncore.regs;
	2493	+ struct intel_gt *gt = &i915->gt;
3121	2494	u32 master_ctl;
3122	2495	u32 gu_misc_iir;
3123	2496
3124	2497	if (!intel_irqs_enabled(i915))
3125	2498	return IRQ_NONE;
3126	2499
3127		- master_ctl = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ);
3128		- master_ctl &= ~GEN11_MASTER_IRQ;
3129		- if (!master_ctl)
	2500	+ master_ctl = intr_disable(regs);
	2501	+ if (!master_ctl) {
	2502	+ intr_enable(regs);
3130	2503	return IRQ_NONE;
3131		-
3132		- /* Disable interrupts. */
3133		- raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, 0);
3134		-
3135		- /* Find, clear, then process each source of interrupt. */
3136		- gen11_gt_irq_handler(i915, master_ctl);
3137		-
3138		- /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3139		- if (master_ctl & GEN11_DISPLAY_IRQ) {
3140		- const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL);
3141		-
3142		- disable_rpm_wakeref_asserts(i915);
3143		- /*
3144		- * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ
3145		- * for the display related bits.
3146		- */
3147		- gen8_de_irq_handler(i915, disp_ctl);
3148		- enable_rpm_wakeref_asserts(i915);
3149	2504	}
3150	2505
3151		- gu_misc_iir = gen11_gu_misc_irq_ack(i915, master_ctl);
	2506	+ /* Find, queue (onto bottom-halves), then clear each source */
	2507	+ gen11_gt_irq_handler(gt, master_ctl);
3152	2508
3153		- /* Acknowledge and enable interrupts. */
3154		- raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ \| master_ctl);
	2509	+ /* IRQs are synced during runtime_suspend, we don't require a wakeref */
	2510	+ if (master_ctl & GEN11_DISPLAY_IRQ)
	2511	+ gen11_display_irq_handler(i915);
3155	2512
3156		- gen11_gu_misc_irq_handler(i915, gu_misc_iir);
	2513	+ gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
	2514	+
	2515	+ intr_enable(regs);
	2516	+
	2517	+ gen11_gu_misc_irq_handler(gt, gu_misc_iir);
3157	2518
3158	2519	return IRQ_HANDLED;
3159	2520	}
3160	2521
3161		-static void i915_reset_device(struct drm_i915_private *dev_priv,
3162		- u32 engine_mask,
3163		- const char *reason)
	2522	+static irqreturn_t gen11_irq_handler(int irq, void *arg)
3164	2523	{
3165		- struct i915_gpu_error *error = &dev_priv->gpu_error;
3166		- struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj;
3167		- char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
3168		- char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
3169		- char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
3170		- struct wedge_me w;
3171		-
3172		- kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
3173		-
3174		- DRM_DEBUG_DRIVER("resetting chip\n");
3175		- kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
3176		-
3177		- /* Use a watchdog to ensure that our reset completes */
3178		- i915_wedge_on_timeout(&w, dev_priv, 5*HZ) {
3179		- intel_prepare_reset(dev_priv);
3180		-
3181		- error->reason = reason;
3182		- error->stalled_mask = engine_mask;
3183		-
3184		- /* Signal that locked waiters should reset the GPU */
3185		- smp_mb__before_atomic();
3186		- set_bit(I915_RESET_HANDOFF, &error->flags);
3187		- wake_up_all(&error->wait_queue);
3188		-
3189		- /* Wait for anyone holding the lock to wakeup, without
3190		- * blocking indefinitely on struct_mutex.
3191		- */
3192		- do {
3193		- if (mutex_trylock(&dev_priv->drm.struct_mutex)) {
3194		- i915_reset(dev_priv, engine_mask, reason);
3195		- mutex_unlock(&dev_priv->drm.struct_mutex);
3196		- }
3197		- } while (wait_on_bit_timeout(&error->flags,
3198		- I915_RESET_HANDOFF,
3199		- TASK_UNINTERRUPTIBLE,
3200		- 1));
3201		-
3202		- error->stalled_mask = 0;
3203		- error->reason = NULL;
3204		-
3205		- intel_finish_reset(dev_priv);
3206		- }
3207		-
3208		- if (!test_bit(I915_WEDGED, &error->flags))
3209		- kobject_uevent_env(kobj, KOBJ_CHANGE, reset_done_event);
	2524	+ return __gen11_irq_handler(arg,
	2525	+ gen11_master_intr_disable,
	2526	+ gen11_master_intr_enable);
3210	2527	}
3211	2528
3212		-static void i915_clear_error_registers(struct drm_i915_private *dev_priv)
	2529	+static u32 dg1_master_intr_disable_and_ack(void __iomem * const regs)
3213	2530	{
3214		- u32 eir;
	2531	+ u32 val;
3215	2532
3216		- if (!IS_GEN2(dev_priv))
3217		- I915_WRITE(PGTBL_ER, I915_READ(PGTBL_ER));
	2533	+ /* First disable interrupts */
	2534	+ raw_reg_write(regs, DG1_MSTR_UNIT_INTR, 0);
3218	2535
3219		- if (INTEL_GEN(dev_priv) < 4)
3220		- I915_WRITE(IPEIR, I915_READ(IPEIR));
3221		- else
3222		- I915_WRITE(IPEIR_I965, I915_READ(IPEIR_I965));
	2536	+ /* Get the indication levels and ack the master unit */
	2537	+ val = raw_reg_read(regs, DG1_MSTR_UNIT_INTR);
	2538	+ if (unlikely(!val))
	2539	+ return 0;
3223	2540
3224		- I915_WRITE(EIR, I915_READ(EIR));
3225		- eir = I915_READ(EIR);
3226		- if (eir) {
3227		- /*
3228		- * some errors might have become stuck,
3229		- * mask them.
3230		- */
3231		- DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir);
3232		- I915_WRITE(EMR, I915_READ(EMR) \| eir);
3233		- I915_WRITE(IIR, I915_MASTER_ERROR_INTERRUPT);
3234		- }
	2541	+ raw_reg_write(regs, DG1_MSTR_UNIT_INTR, val);
	2542	+
	2543	+ /*
	2544	+ * Now with master disabled, get a sample of level indications
	2545	+ * for this interrupt and ack them right away - we keep GEN11_MASTER_IRQ
	2546	+ * out as this bit doesn't exist anymore for DG1
	2547	+ */
	2548	+ val = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ) & ~GEN11_MASTER_IRQ;
	2549	+ if (unlikely(!val))
	2550	+ return 0;
	2551	+
	2552	+ raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, val);
	2553	+
	2554	+ return val;
3235	2555	}
3236	2556
3237		-/**
3238		- * i915_handle_error - handle a gpu error
3239		- * @dev_priv: i915 device private
3240		- * @engine_mask: mask representing engines that are hung
3241		- * @flags: control flags
3242		- * @fmt: Error message format string
3243		- *
3244		- * Do some basic checking of register state at error time and
3245		- * dump it to the syslog. Also call i915_capture_error_state() to make
3246		- * sure we get a record and make it available in debugfs. Fire a uevent
3247		- * so userspace knows something bad happened (should trigger collection
3248		- * of a ring dump etc.).
3249		- */
3250		-void i915_handle_error(struct drm_i915_private *dev_priv,
3251		- u32 engine_mask,
3252		- unsigned long flags,
3253		- const char *fmt, ...)
	2557	+static inline void dg1_master_intr_enable(void __iomem * const regs)
3254	2558	{
3255		- struct intel_engine_cs *engine;
3256		- unsigned int tmp;
3257		- char error_msg[80];
3258		- char *msg = NULL;
	2559	+ raw_reg_write(regs, DG1_MSTR_UNIT_INTR, DG1_MSTR_IRQ);
	2560	+}
3259	2561
3260		- if (fmt) {
3261		- va_list args;
3262		-
3263		- va_start(args, fmt);
3264		- vscnprintf(error_msg, sizeof(error_msg), fmt, args);
3265		- va_end(args);
3266		-
3267		- msg = error_msg;
3268		- }
3269		-
3270		- /*
3271		- * In most cases it's guaranteed that we get here with an RPM
3272		- * reference held, for example because there is a pending GPU
3273		- * request that won't finish until the reset is done. This
3274		- * isn't the case at least when we get here by doing a
3275		- * simulated reset via debugfs, so get an RPM reference.
3276		- */
3277		- intel_runtime_pm_get(dev_priv);
3278		-
3279		- engine_mask &= INTEL_INFO(dev_priv)->ring_mask;
3280		-
3281		- if (flags & I915_ERROR_CAPTURE) {
3282		- i915_capture_error_state(dev_priv, engine_mask, msg);
3283		- i915_clear_error_registers(dev_priv);
3284		- }
3285		-
3286		- /*
3287		- * Try engine reset when available. We fall back to full reset if
3288		- * single reset fails.
3289		- */
3290		- if (intel_has_reset_engine(dev_priv)) {
3291		- for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
3292		- BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE);
3293		- if (test_and_set_bit(I915_RESET_ENGINE + engine->id,
3294		- &dev_priv->gpu_error.flags))
3295		- continue;
3296		-
3297		- if (i915_reset_engine(engine, msg) == 0)
3298		- engine_mask &= ~intel_engine_flag(engine);
3299		-
3300		- clear_bit(I915_RESET_ENGINE + engine->id,
3301		- &dev_priv->gpu_error.flags);
3302		- wake_up_bit(&dev_priv->gpu_error.flags,
3303		- I915_RESET_ENGINE + engine->id);
3304		- }
3305		- }
3306		-
3307		- if (!engine_mask)
3308		- goto out;
3309		-
3310		- /* Full reset needs the mutex, stop any other user trying to do so. */
3311		- if (test_and_set_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags)) {
3312		- wait_event(dev_priv->gpu_error.reset_queue,
3313		- !test_bit(I915_RESET_BACKOFF,
3314		- &dev_priv->gpu_error.flags));
3315		- goto out;
3316		- }
3317		-
3318		- /* Prevent any other reset-engine attempt. */
3319		- for_each_engine(engine, dev_priv, tmp) {
3320		- while (test_and_set_bit(I915_RESET_ENGINE + engine->id,
3321		- &dev_priv->gpu_error.flags))
3322		- wait_on_bit(&dev_priv->gpu_error.flags,
3323		- I915_RESET_ENGINE + engine->id,
3324		- TASK_UNINTERRUPTIBLE);
3325		- }
3326		-
3327		- i915_reset_device(dev_priv, engine_mask, msg);
3328		-
3329		- for_each_engine(engine, dev_priv, tmp) {
3330		- clear_bit(I915_RESET_ENGINE + engine->id,
3331		- &dev_priv->gpu_error.flags);
3332		- }
3333		-
3334		- clear_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags);
3335		- wake_up_all(&dev_priv->gpu_error.reset_queue);
3336		-
3337		-out:
3338		- intel_runtime_pm_put(dev_priv);
	2562	+static irqreturn_t dg1_irq_handler(int irq, void *arg)
	2563	+{
	2564	+ return __gen11_irq_handler(arg,
	2565	+ dg1_master_intr_disable_and_ack,
	2566	+ dg1_master_intr_enable);
3339	2567	}
3340	2568
3341	2569	/* Called from drm generic code, passed 'crtc' which
3342	2570	* we use as a pipe index
3343	2571	*/
3344		-static int i8xx_enable_vblank(struct drm_device *dev, unsigned int pipe)
	2572	+int i8xx_enable_vblank(struct drm_crtc *crtc)
3345	2573	{
3346		- struct drm_i915_private *dev_priv = to_i915(dev);
	2574	+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
	2575	+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
3347	2576	unsigned long irqflags;
3348	2577
3349	2578	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
..	..	@@ -3353,9 +2582,26 @@
3353	2582	return 0;
3354	2583	}
3355	2584
3356		-static int i965_enable_vblank(struct drm_device *dev, unsigned int pipe)
	2585	+int i915gm_enable_vblank(struct drm_crtc *crtc)
3357	2586	{
3358		- struct drm_i915_private *dev_priv = to_i915(dev);
	2587	+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
	2588	+
	2589	+ /*
	2590	+ * Vblank interrupts fail to wake the device up from C2+.
	2591	+ * Disabling render clock gating during C-states avoids
	2592	+ * the problem. There is a small power cost so we do this
	2593	+ * only when vblank interrupts are actually enabled.
	2594	+ */
	2595	+ if (dev_priv->vblank_enabled++ == 0)
	2596	+ I915_WRITE(SCPD0, _MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
	2597	+
	2598	+ return i8xx_enable_vblank(crtc);
	2599	+}
	2600	+
	2601	+int i965_enable_vblank(struct drm_crtc *crtc)
	2602	+{
	2603	+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
	2604	+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
3359	2605	unsigned long irqflags;
3360	2606
3361	2607	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
..	..	@@ -3366,11 +2612,12 @@
3366	2612	return 0;
3367	2613	}
3368	2614
3369		-static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
	2615	+int ilk_enable_vblank(struct drm_crtc *crtc)
3370	2616	{
3371		- struct drm_i915_private *dev_priv = to_i915(dev);
	2617	+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
	2618	+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
3372	2619	unsigned long irqflags;
3373		- uint32_t bit = INTEL_GEN(dev_priv) >= 7 ?
	2620	+ u32 bit = INTEL_GEN(dev_priv) >= 7 ?
3374	2621	DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
3375	2622
3376	2623	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
..	..	@@ -3381,14 +2628,15 @@
3381	2628	* PSR is active as no frames are generated.
3382	2629	*/
3383	2630	if (HAS_PSR(dev_priv))
3384		- drm_vblank_restore(dev, pipe);
	2631	+ drm_crtc_vblank_restore(crtc);
3385	2632
3386	2633	return 0;
3387	2634	}
3388	2635
3389		-static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
	2636	+int bdw_enable_vblank(struct drm_crtc *crtc)
3390	2637	{
3391		- struct drm_i915_private *dev_priv = to_i915(dev);
	2638	+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
	2639	+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
3392	2640	unsigned long irqflags;
3393	2641
3394	2642	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
..	..	@@ -3399,7 +2647,7 @@
3399	2647	* PSR is active as no frames are generated, so check only for PSR.
3400	2648	*/
3401	2649	if (HAS_PSR(dev_priv))
3402		- drm_vblank_restore(dev, pipe);
	2650	+ drm_crtc_vblank_restore(crtc);
3403	2651
3404	2652	return 0;
3405	2653	}
..	..	@@ -3407,9 +2655,10 @@
3407	2655	/* Called from drm generic code, passed 'crtc' which
3408	2656	* we use as a pipe index
3409	2657	*/
3410		-static void i8xx_disable_vblank(struct drm_device *dev, unsigned int pipe)
	2658	+void i8xx_disable_vblank(struct drm_crtc *crtc)
3411	2659	{
3412		- struct drm_i915_private *dev_priv = to_i915(dev);
	2660	+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
	2661	+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
3413	2662	unsigned long irqflags;
3414	2663
3415	2664	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
..	..	@@ -3417,9 +2666,20 @@
3417	2666	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3418	2667	}
3419	2668
3420		-static void i965_disable_vblank(struct drm_device *dev, unsigned int pipe)
	2669	+void i915gm_disable_vblank(struct drm_crtc *crtc)
3421	2670	{
3422		- struct drm_i915_private *dev_priv = to_i915(dev);
	2671	+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
	2672	+
	2673	+ i8xx_disable_vblank(crtc);
	2674	+
	2675	+ if (--dev_priv->vblank_enabled == 0)
	2676	+ I915_WRITE(SCPD0, _MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
	2677	+}
	2678	+
	2679	+void i965_disable_vblank(struct drm_crtc *crtc)
	2680	+{
	2681	+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
	2682	+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
3423	2683	unsigned long irqflags;
3424	2684
3425	2685	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
..	..	@@ -3428,11 +2688,12 @@
3428	2688	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3429	2689	}
3430	2690
3431		-static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
	2691	+void ilk_disable_vblank(struct drm_crtc *crtc)
3432	2692	{
3433		- struct drm_i915_private *dev_priv = to_i915(dev);
	2693	+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
	2694	+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
3434	2695	unsigned long irqflags;
3435		- uint32_t bit = INTEL_GEN(dev_priv) >= 7 ?
	2696	+ u32 bit = INTEL_GEN(dev_priv) >= 7 ?
3436	2697	DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
3437	2698
3438	2699	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
..	..	@@ -3440,9 +2701,10 @@
3440	2701	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3441	2702	}
3442	2703
3443		-static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
	2704	+void bdw_disable_vblank(struct drm_crtc *crtc)
3444	2705	{
3445		- struct drm_i915_private *dev_priv = to_i915(dev);
	2706	+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
	2707	+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
3446	2708	unsigned long irqflags;
3447	2709
3448	2710	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
..	..	@@ -3452,10 +2714,12 @@
3452	2714
3453	2715	static void ibx_irq_reset(struct drm_i915_private *dev_priv)
3454	2716	{
	2717	+ struct intel_uncore *uncore = &dev_priv->uncore;
	2718	+
3455	2719	if (HAS_PCH_NOP(dev_priv))
3456	2720	return;
3457	2721
3458		- GEN3_IRQ_RESET(SDE);
	2722	+ GEN3_IRQ_RESET(uncore, SDE);
3459	2723
3460	2724	if (HAS_PCH_CPT(dev_priv) \|\| HAS_PCH_LPT(dev_priv))
3461	2725	I915_WRITE(SERR_INT, 0xffffffff);
..	..	@@ -3469,43 +2733,38 @@
3469	2733	*
3470	2734	* This function needs to be called before interrupts are enabled.
3471	2735	*/
3472		-static void ibx_irq_pre_postinstall(struct drm_device *dev)
	2736	+static void ibx_irq_pre_postinstall(struct drm_i915_private *dev_priv)
3473	2737	{
3474		- struct drm_i915_private *dev_priv = to_i915(dev);
3475		-
3476	2738	if (HAS_PCH_NOP(dev_priv))
3477	2739	return;
3478	2740
3479		- WARN_ON(I915_READ(SDEIER) != 0);
	2741	+ drm_WARN_ON(&dev_priv->drm, I915_READ(SDEIER) != 0);
3480	2742	I915_WRITE(SDEIER, 0xffffffff);
3481	2743	POSTING_READ(SDEIER);
3482	2744	}
3483	2745
3484		-static void gen5_gt_irq_reset(struct drm_i915_private *dev_priv)
3485		-{
3486		- GEN3_IRQ_RESET(GT);
3487		- if (INTEL_GEN(dev_priv) >= 6)
3488		- GEN3_IRQ_RESET(GEN6_PM);
3489		-}
3490		-
3491	2746	static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
3492	2747	{
	2748	+ struct intel_uncore *uncore = &dev_priv->uncore;
	2749	+
3493	2750	if (IS_CHERRYVIEW(dev_priv))
3494		- I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
	2751	+ intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3495	2752	else
3496		- I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
	2753	+ intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK);
3497	2754
3498	2755	i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
3499		- I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	2756	+ intel_uncore_write(uncore, PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3500	2757
3501	2758	i9xx_pipestat_irq_reset(dev_priv);
3502	2759
3503		- GEN3_IRQ_RESET(VLV_);
	2760	+ GEN3_IRQ_RESET(uncore, VLV_);
3504	2761	dev_priv->irq_mask = ~0u;
3505	2762	}
3506	2763
3507	2764	static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
3508	2765	{
	2766	+ struct intel_uncore *uncore = &dev_priv->uncore;
	2767	+
3509	2768	u32 pipestat_mask;
3510	2769	u32 enable_mask;
3511	2770	enum pipe pipe;
..	..	@@ -3526,44 +2785,39 @@
3526	2785	enable_mask \|= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT \|
3527	2786	I915_LPE_PIPE_C_INTERRUPT;
3528	2787
3529		- WARN_ON(dev_priv->irq_mask != ~0u);
	2788	+ drm_WARN_ON(&dev_priv->drm, dev_priv->irq_mask != ~0u);
3530	2789
3531	2790	dev_priv->irq_mask = ~enable_mask;
3532	2791
3533		- GEN3_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask);
	2792	+ GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq_mask, enable_mask);
3534	2793	}
3535	2794
3536	2795	/* drm_dma.h hooks
3537	2796	*/
3538		-static void ironlake_irq_reset(struct drm_device *dev)
	2797	+static void ilk_irq_reset(struct drm_i915_private *dev_priv)
3539	2798	{
3540		- struct drm_i915_private *dev_priv = to_i915(dev);
	2799	+ struct intel_uncore *uncore = &dev_priv->uncore;
3541	2800
3542		- if (IS_GEN5(dev_priv))
3543		- I915_WRITE(HWSTAM, 0xffffffff);
3544		-
3545		- GEN3_IRQ_RESET(DE);
3546		- if (IS_GEN7(dev_priv))
3547		- I915_WRITE(GEN7_ERR_INT, 0xffffffff);
	2801	+ GEN3_IRQ_RESET(uncore, DE);
	2802	+ if (IS_GEN(dev_priv, 7))
	2803	+ intel_uncore_write(uncore, GEN7_ERR_INT, 0xffffffff);
3548	2804
3549	2805	if (IS_HASWELL(dev_priv)) {
3550		- I915_WRITE(EDP_PSR_IMR, 0xffffffff);
3551		- I915_WRITE(EDP_PSR_IIR, 0xffffffff);
	2806	+ intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
	2807	+ intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
3552	2808	}
3553	2809
3554		- gen5_gt_irq_reset(dev_priv);
	2810	+ gen5_gt_irq_reset(&dev_priv->gt);
3555	2811
3556	2812	ibx_irq_reset(dev_priv);
3557	2813	}
3558	2814
3559		-static void valleyview_irq_reset(struct drm_device *dev)
	2815	+static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
3560	2816	{
3561		- struct drm_i915_private *dev_priv = to_i915(dev);
3562		-
3563	2817	I915_WRITE(VLV_MASTER_IER, 0);
3564	2818	POSTING_READ(VLV_MASTER_IER);
3565	2819
3566		- gen5_gt_irq_reset(dev_priv);
	2820	+ gen5_gt_irq_reset(&dev_priv->gt);
3567	2821
3568	2822	spin_lock_irq(&dev_priv->irq_lock);
3569	2823	if (dev_priv->display_irqs_enabled)
..	..	@@ -3571,88 +2825,101 @@
3571	2825	spin_unlock_irq(&dev_priv->irq_lock);
3572	2826	}
3573	2827
3574		-static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
	2828	+static void gen8_irq_reset(struct drm_i915_private *dev_priv)
3575	2829	{
3576		- GEN8_IRQ_RESET_NDX(GT, 0);
3577		- GEN8_IRQ_RESET_NDX(GT, 1);
3578		- GEN8_IRQ_RESET_NDX(GT, 2);
3579		- GEN8_IRQ_RESET_NDX(GT, 3);
3580		-}
	2830	+ struct intel_uncore *uncore = &dev_priv->uncore;
	2831	+ enum pipe pipe;
3581	2832
3582		-static void gen8_irq_reset(struct drm_device *dev)
3583		-{
3584		- struct drm_i915_private *dev_priv = to_i915(dev);
3585		- int pipe;
	2833	+ gen8_master_intr_disable(dev_priv->uncore.regs);
3586	2834
3587		- I915_WRITE(GEN8_MASTER_IRQ, 0);
3588		- POSTING_READ(GEN8_MASTER_IRQ);
	2835	+ gen8_gt_irq_reset(&dev_priv->gt);
3589	2836
3590		- gen8_gt_irq_reset(dev_priv);
3591		-
3592		- I915_WRITE(EDP_PSR_IMR, 0xffffffff);
3593		- I915_WRITE(EDP_PSR_IIR, 0xffffffff);
	2837	+ intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
	2838	+ intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
3594	2839
3595	2840	for_each_pipe(dev_priv, pipe)
3596	2841	if (intel_display_power_is_enabled(dev_priv,
3597	2842	POWER_DOMAIN_PIPE(pipe)))
3598		- GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
	2843	+ GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
3599	2844
3600		- GEN3_IRQ_RESET(GEN8_DE_PORT_);
3601		- GEN3_IRQ_RESET(GEN8_DE_MISC_);
3602		- GEN3_IRQ_RESET(GEN8_PCU_);
	2845	+ GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
	2846	+ GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
	2847	+ GEN3_IRQ_RESET(uncore, GEN8_PCU_);
3603	2848
3604	2849	if (HAS_PCH_SPLIT(dev_priv))
3605	2850	ibx_irq_reset(dev_priv);
3606	2851	}
3607	2852
3608		-static void gen11_gt_irq_reset(struct drm_i915_private *dev_priv)
	2853	+static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
3609	2854	{
3610		- /* Disable RCS, BCS, VCS and VECS class engines. */
3611		- I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, 0);
3612		- I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE, 0);
	2855	+ struct intel_uncore *uncore = &dev_priv->uncore;
	2856	+ enum pipe pipe;
	2857	+ u32 trans_mask = BIT(TRANSCODER_A) \| BIT(TRANSCODER_B) \|
	2858	+ BIT(TRANSCODER_C) \| BIT(TRANSCODER_D);
3613	2859
3614		- /* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
3615		- I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK, ~0);
3616		- I915_WRITE(GEN11_BCS_RSVD_INTR_MASK, ~0);
3617		- I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK, ~0);
3618		- I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK, ~0);
3619		- I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK, ~0);
	2860	+ intel_uncore_write(uncore, GEN11_DISPLAY_INT_CTL, 0);
3620	2861
3621		- I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
3622		- I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
3623		-}
	2862	+ if (INTEL_GEN(dev_priv) >= 12) {
	2863	+ enum transcoder trans;
3624	2864
3625		-static void gen11_irq_reset(struct drm_device *dev)
3626		-{
3627		- struct drm_i915_private *dev_priv = dev->dev_private;
3628		- int pipe;
	2865	+ for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {
	2866	+ enum intel_display_power_domain domain;
3629	2867
3630		- I915_WRITE(GEN11_GFX_MSTR_IRQ, 0);
3631		- POSTING_READ(GEN11_GFX_MSTR_IRQ);
	2868	+ domain = POWER_DOMAIN_TRANSCODER(trans);
	2869	+ if (!intel_display_power_is_enabled(dev_priv, domain))
	2870	+ continue;
3632	2871
3633		- gen11_gt_irq_reset(dev_priv);
3634		-
3635		- I915_WRITE(GEN11_DISPLAY_INT_CTL, 0);
	2872	+ intel_uncore_write(uncore, TRANS_PSR_IMR(trans), 0xffffffff);
	2873	+ intel_uncore_write(uncore, TRANS_PSR_IIR(trans), 0xffffffff);
	2874	+ }
	2875	+ } else {
	2876	+ intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
	2877	+ intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
	2878	+ }
3636	2879
3637	2880	for_each_pipe(dev_priv, pipe)
3638	2881	if (intel_display_power_is_enabled(dev_priv,
3639	2882	POWER_DOMAIN_PIPE(pipe)))
3640		- GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
	2883	+ GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
3641	2884
3642		- GEN3_IRQ_RESET(GEN8_DE_PORT_);
3643		- GEN3_IRQ_RESET(GEN8_DE_MISC_);
3644		- GEN3_IRQ_RESET(GEN11_DE_HPD_);
3645		- GEN3_IRQ_RESET(GEN11_GU_MISC_);
3646		- GEN3_IRQ_RESET(GEN8_PCU_);
	2885	+ GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
	2886	+ GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
	2887	+ GEN3_IRQ_RESET(uncore, GEN11_DE_HPD_);
3647	2888
3648		- if (HAS_PCH_ICP(dev_priv))
3649		- GEN3_IRQ_RESET(SDE);
	2889	+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
	2890	+ GEN3_IRQ_RESET(uncore, SDE);
	2891	+
	2892	+ /* Wa_14010685332:icl,jsl,ehl,tgl,rkl */
	2893	+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
	2894	+ intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
	2895	+ SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
	2896	+ intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
	2897	+ SBCLK_RUN_REFCLK_DIS, 0);
	2898	+ }
	2899	+}
	2900	+
	2901	+static void gen11_irq_reset(struct drm_i915_private *dev_priv)
	2902	+{
	2903	+ struct intel_uncore *uncore = &dev_priv->uncore;
	2904	+
	2905	+ if (HAS_MASTER_UNIT_IRQ(dev_priv))
	2906	+ dg1_master_intr_disable_and_ack(dev_priv->uncore.regs);
	2907	+ else
	2908	+ gen11_master_intr_disable(dev_priv->uncore.regs);
	2909	+
	2910	+ gen11_gt_irq_reset(&dev_priv->gt);
	2911	+ gen11_display_irq_reset(dev_priv);
	2912	+
	2913	+ GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
	2914	+ GEN3_IRQ_RESET(uncore, GEN8_PCU_);
3650	2915	}
3651	2916
3652	2917	void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3653	2918	u8 pipe_mask)
3654	2919	{
3655		- uint32_t extra_ier = GEN8_PIPE_VBLANK \| GEN8_PIPE_FIFO_UNDERRUN;
	2920	+ struct intel_uncore *uncore = &dev_priv->uncore;
	2921	+
	2922	+ u32 extra_ier = GEN8_PIPE_VBLANK \| GEN8_PIPE_FIFO_UNDERRUN;
3656	2923	enum pipe pipe;
3657	2924
3658	2925	spin_lock_irq(&dev_priv->irq_lock);
..	..	@@ -3663,7 +2930,7 @@
3663	2930	}
3664	2931
3665	2932	for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3666		- GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
	2933	+ GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
3667	2934	dev_priv->de_irq_mask[pipe],
3668	2935	~dev_priv->de_irq_mask[pipe] \| extra_ier);
3669	2936
..	..	@@ -3673,6 +2940,7 @@
3673	2940	void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
3674	2941	u8 pipe_mask)
3675	2942	{
	2943	+ struct intel_uncore *uncore = &dev_priv->uncore;
3676	2944	enum pipe pipe;
3677	2945
3678	2946	spin_lock_irq(&dev_priv->irq_lock);
..	..	@@ -3683,24 +2951,24 @@
3683	2951	}
3684	2952
3685	2953	for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3686		- GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
	2954	+ GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
3687	2955
3688	2956	spin_unlock_irq(&dev_priv->irq_lock);
3689	2957
3690	2958	/* make sure we're done processing display irqs */
3691		- synchronize_irq(dev_priv->drm.irq);
	2959	+ intel_synchronize_irq(dev_priv);
3692	2960	}
3693	2961
3694		-static void cherryview_irq_reset(struct drm_device *dev)
	2962	+static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
3695	2963	{
3696		- struct drm_i915_private *dev_priv = to_i915(dev);
	2964	+ struct intel_uncore *uncore = &dev_priv->uncore;
3697	2965
3698	2966	I915_WRITE(GEN8_MASTER_IRQ, 0);
3699	2967	POSTING_READ(GEN8_MASTER_IRQ);
3700	2968
3701		- gen8_gt_irq_reset(dev_priv);
	2969	+ gen8_gt_irq_reset(&dev_priv->gt);
3702	2970
3703		- GEN3_IRQ_RESET(GEN8_PCU_);
	2971	+ GEN3_IRQ_RESET(uncore, GEN8_PCU_);
3704	2972
3705	2973	spin_lock_irq(&dev_priv->irq_lock);
3706	2974	if (dev_priv->display_irqs_enabled)
..	..	@@ -3719,6 +2987,18 @@
3719	2987	enabled_irqs \|= hpd[encoder->hpd_pin];
3720	2988
3721	2989	return enabled_irqs;
	2990	+}
	2991	+
	2992	+static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv,
	2993	+ const u32 hpd[HPD_NUM_PINS])
	2994	+{
	2995	+ struct intel_encoder *encoder;
	2996	+ u32 hotplug_irqs = 0;
	2997	+
	2998	+ for_each_intel_encoder(&dev_priv->drm, encoder)
	2999	+ hotplug_irqs \|= hpd[encoder->hpd_pin];
	3000	+
	3001	+ return hotplug_irqs;
3722	3002	}
3723	3003
3724	3004	static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
..	..	@@ -3750,46 +3030,71 @@
3750	3030	{
3751	3031	u32 hotplug_irqs, enabled_irqs;
3752	3032
3753		- if (HAS_PCH_IBX(dev_priv)) {
3754		- hotplug_irqs = SDE_HOTPLUG_MASK;
3755		- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ibx);
3756		- } else {
3757		- hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3758		- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_cpt);
3759		- }
	3033	+ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
	3034	+ hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3760	3035
3761	3036	ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3762	3037
3763	3038	ibx_hpd_detection_setup(dev_priv);
3764	3039	}
3765	3040
3766		-static void icp_hpd_detection_setup(struct drm_i915_private *dev_priv)
	3041	+static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv,
	3042	+ u32 enable_mask)
3767	3043	{
3768	3044	u32 hotplug;
3769	3045
3770	3046	hotplug = I915_READ(SHOTPLUG_CTL_DDI);
3771		- hotplug \|= ICP_DDIA_HPD_ENABLE \|
3772		- ICP_DDIB_HPD_ENABLE;
	3047	+ hotplug \|= enable_mask;
3773	3048	I915_WRITE(SHOTPLUG_CTL_DDI, hotplug);
	3049	+}
	3050	+
	3051	+static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv,
	3052	+ u32 enable_mask)
	3053	+{
	3054	+ u32 hotplug;
3774	3055
3775	3056	hotplug = I915_READ(SHOTPLUG_CTL_TC);
3776		- hotplug \|= ICP_TC_HPD_ENABLE(PORT_TC1) \|
3777		- ICP_TC_HPD_ENABLE(PORT_TC2) \|
3778		- ICP_TC_HPD_ENABLE(PORT_TC3) \|
3779		- ICP_TC_HPD_ENABLE(PORT_TC4);
	3057	+ hotplug \|= enable_mask;
3780	3058	I915_WRITE(SHOTPLUG_CTL_TC, hotplug);
3781	3059	}
3782	3060
3783		-static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)
	3061	+static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv,
	3062	+ u32 ddi_enable_mask, u32 tc_enable_mask)
3784	3063	{
3785	3064	u32 hotplug_irqs, enabled_irqs;
3786	3065
3787		- hotplug_irqs = SDE_DDI_MASK_ICP \| SDE_TC_MASK_ICP;
3788		- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_icp);
	3066	+ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
	3067	+ hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
	3068	+
	3069	+ if (INTEL_PCH_TYPE(dev_priv) <= PCH_TGP)
	3070	+ I915_WRITE(SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
3789	3071
3790	3072	ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3791	3073
3792		- icp_hpd_detection_setup(dev_priv);
	3074	+ icp_ddi_hpd_detection_setup(dev_priv, ddi_enable_mask);
	3075	+ if (tc_enable_mask)
	3076	+ icp_tc_hpd_detection_setup(dev_priv, tc_enable_mask);
	3077	+}
	3078	+
	3079	+/*
	3080	+ * EHL doesn't need most of gen11_hpd_irq_setup, it's handling only the
	3081	+ * equivalent of SDE.
	3082	+ */
	3083	+static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv)
	3084	+{
	3085	+ icp_hpd_irq_setup(dev_priv,
	3086	+ ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(PORT_TC1));
	3087	+}
	3088	+
	3089	+/*
	3090	+ * JSP behaves exactly the same as MCC above except that port C is mapped to
	3091	+ * the DDI-C pins instead of the TC1 pins. This means we should follow TGP's
	3092	+ * masks & tables rather than ICP's masks & tables.
	3093	+ */
	3094	+static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
	3095	+{
	3096	+ icp_hpd_irq_setup(dev_priv,
	3097	+ TGP_DDI_HPD_ENABLE_MASK, 0);
3793	3098	}
3794	3099
3795	3100	static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
..	..	@@ -3800,14 +3105,18 @@
3800	3105	hotplug \|= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) \|
3801	3106	GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) \|
3802	3107	GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) \|
3803		- GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4);
	3108	+ GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4) \|
	3109	+ GEN11_HOTPLUG_CTL_ENABLE(PORT_TC5) \|
	3110	+ GEN11_HOTPLUG_CTL_ENABLE(PORT_TC6);
3804	3111	I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug);
3805	3112
3806	3113	hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL);
3807	3114	hotplug \|= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) \|
3808	3115	GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) \|
3809	3116	GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) \|
3810		- GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4);
	3117	+ GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4) \|
	3118	+ GEN11_HOTPLUG_CTL_ENABLE(PORT_TC5) \|
	3119	+ GEN11_HOTPLUG_CTL_ENABLE(PORT_TC6);
3811	3120	I915_WRITE(GEN11_TBT_HOTPLUG_CTL, hotplug);
3812	3121	}
3813	3122
..	..	@@ -3816,8 +3125,8 @@
3816	3125	u32 hotplug_irqs, enabled_irqs;
3817	3126	u32 val;
3818	3127
3819		- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_gen11);
3820		- hotplug_irqs = GEN11_DE_TC_HOTPLUG_MASK \| GEN11_DE_TBT_HOTPLUG_MASK;
	3128	+ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
	3129	+ hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);
3821	3130
3822	3131	val = I915_READ(GEN11_DE_HPD_IMR);
3823	3132	val &= ~hotplug_irqs;
..	..	@@ -3827,8 +3136,12 @@
3827	3136
3828	3137	gen11_hpd_detection_setup(dev_priv);
3829	3138
3830		- if (HAS_PCH_ICP(dev_priv))
3831		- icp_hpd_irq_setup(dev_priv);
	3139	+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP)
	3140	+ icp_hpd_irq_setup(dev_priv,
	3141	+ TGP_DDI_HPD_ENABLE_MASK, TGP_TC_HPD_ENABLE_MASK);
	3142	+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
	3143	+ icp_hpd_irq_setup(dev_priv,
	3144	+ ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE_MASK);
3832	3145	}
3833	3146
3834	3147	static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
..	..	@@ -3860,8 +3173,11 @@
3860	3173	{
3861	3174	u32 hotplug_irqs, enabled_irqs;
3862	3175
3863		- hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
3864		- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt);
	3176	+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
	3177	+ I915_WRITE(SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
	3178	+
	3179	+ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
	3180	+ hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3865	3181
3866	3182	ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3867	3183
..	..	@@ -3888,22 +3204,13 @@
3888	3204	{
3889	3205	u32 hotplug_irqs, enabled_irqs;
3890	3206
3891		- if (INTEL_GEN(dev_priv) >= 8) {
3892		- hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
3893		- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw);
	3207	+ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
	3208	+ hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);
3894	3209
	3210	+ if (INTEL_GEN(dev_priv) >= 8)
3895	3211	bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3896		- } else if (INTEL_GEN(dev_priv) >= 7) {
3897		- hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
3898		- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb);
3899		-
	3212	+ else
3900	3213	ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3901		- } else {
3902		- hotplug_irqs = DE_DP_A_HOTPLUG;
3903		- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ilk);
3904		-
3905		- ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3906		- }
3907	3214
3908	3215	ilk_hpd_detection_setup(dev_priv);
3909	3216
..	..	@@ -3920,8 +3227,9 @@
3920	3227	PORTB_HOTPLUG_ENABLE \|
3921	3228	PORTC_HOTPLUG_ENABLE;
3922	3229
3923		- DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n",
3924		- hotplug, enabled_irqs);
	3230	+ drm_dbg_kms(&dev_priv->drm,
	3231	+ "Invert bit setting: hp_ctl:%x hp_port:%x\n",
	3232	+ hotplug, enabled_irqs);
3925	3233	hotplug &= ~BXT_DDI_HPD_INVERT_MASK;
3926	3234
3927	3235	/*
..	..	@@ -3950,17 +3258,16 @@
3950	3258	{
3951	3259	u32 hotplug_irqs, enabled_irqs;
3952	3260
3953		- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt);
3954		- hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
	3261	+ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
	3262	+ hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);
3955	3263
3956	3264	bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3957	3265
3958	3266	__bxt_hpd_detection_setup(dev_priv, enabled_irqs);
3959	3267	}
3960	3268
3961		-static void ibx_irq_postinstall(struct drm_device *dev)
	3269	+static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
3962	3270	{
3963		- struct drm_i915_private *dev_priv = to_i915(dev);
3964	3271	u32 mask;
3965	3272
3966	3273	if (HAS_PCH_NOP(dev_priv))
..	..	@@ -3973,7 +3280,7 @@
3973	3280	else
3974	3281	mask = SDE_GMBUS_CPT;
3975	3282
3976		- gen3_assert_iir_is_zero(dev_priv, SDEIIR);
	3283	+ gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
3977	3284	I915_WRITE(SDEIMR, ~mask);
3978	3285
3979	3286	if (HAS_PCH_IBX(dev_priv) \|\| HAS_PCH_CPT(dev_priv) \|\|
..	..	@@ -3983,47 +3290,9 @@
3983	3290	spt_hpd_detection_setup(dev_priv);
3984	3291	}
3985	3292
3986		-static void gen5_gt_irq_postinstall(struct drm_device *dev)
	3293	+static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
3987	3294	{
3988		- struct drm_i915_private *dev_priv = to_i915(dev);
3989		- u32 pm_irqs, gt_irqs;
3990		-
3991		- pm_irqs = gt_irqs = 0;
3992		-
3993		- dev_priv->gt_irq_mask = ~0;
3994		- if (HAS_L3_DPF(dev_priv)) {
3995		- /* L3 parity interrupt is always unmasked. */
3996		- dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev_priv);
3997		- gt_irqs \|= GT_PARITY_ERROR(dev_priv);
3998		- }
3999		-
4000		- gt_irqs \|= GT_RENDER_USER_INTERRUPT;
4001		- if (IS_GEN5(dev_priv)) {
4002		- gt_irqs \|= ILK_BSD_USER_INTERRUPT;
4003		- } else {
4004		- gt_irqs \|= GT_BLT_USER_INTERRUPT \| GT_BSD_USER_INTERRUPT;
4005		- }
4006		-
4007		- GEN3_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
4008		-
4009		- if (INTEL_GEN(dev_priv) >= 6) {
4010		- /*
4011		- * RPS interrupts will get enabled/disabled on demand when RPS
4012		- * itself is enabled/disabled.
4013		- */
4014		- if (HAS_VEBOX(dev_priv)) {
4015		- pm_irqs \|= PM_VEBOX_USER_INTERRUPT;
4016		- dev_priv->pm_ier \|= PM_VEBOX_USER_INTERRUPT;
4017		- }
4018		-
4019		- dev_priv->pm_imr = 0xffffffff;
4020		- GEN3_IRQ_INIT(GEN6_PM, dev_priv->pm_imr, pm_irqs);
4021		- }
4022		-}
4023		-
4024		-static int ironlake_irq_postinstall(struct drm_device *dev)
4025		-{
4026		- struct drm_i915_private *dev_priv = to_i915(dev);
	3295	+ struct intel_uncore *uncore = &dev_priv->uncore;
4027	3296	u32 display_mask, extra_mask;
4028	3297
4029	3298	if (INTEL_GEN(dev_priv) >= 7) {
..	..	@@ -4042,22 +3311,22 @@
4042	3311	}
4043	3312
4044	3313	if (IS_HASWELL(dev_priv)) {
4045		- gen3_assert_iir_is_zero(dev_priv, EDP_PSR_IIR);
4046		- intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
	3314	+ gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
4047	3315	display_mask \|= DE_EDP_PSR_INT_HSW;
4048	3316	}
4049	3317
4050	3318	dev_priv->irq_mask = ~display_mask;
4051	3319
4052		- ibx_irq_pre_postinstall(dev);
	3320	+ ibx_irq_pre_postinstall(dev_priv);
4053	3321
4054		- GEN3_IRQ_INIT(DE, dev_priv->irq_mask, display_mask \| extra_mask);
	3322	+ GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask,
	3323	+ display_mask \| extra_mask);
4055	3324
4056		- gen5_gt_irq_postinstall(dev);
	3325	+ gen5_gt_irq_postinstall(&dev_priv->gt);
4057	3326
4058	3327	ilk_hpd_detection_setup(dev_priv);
4059	3328
4060		- ibx_irq_postinstall(dev);
	3329	+ ibx_irq_postinstall(dev_priv);
4061	3330
4062	3331	if (IS_IRONLAKE_M(dev_priv)) {
4063	3332	/* Enable PCU event interrupts
..	..	@@ -4069,8 +3338,6 @@
4069	3338	ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
4070	3339	spin_unlock_irq(&dev_priv->irq_lock);
4071	3340	}
4072		-
4073		- return 0;
4074	3341	}
4075	3342
4076	3343	void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
..	..	@@ -4102,11 +3369,9 @@
4102	3369	}
4103	3370
4104	3371
4105		-static int valleyview_irq_postinstall(struct drm_device *dev)
	3372	+static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv)
4106	3373	{
4107		- struct drm_i915_private *dev_priv = to_i915(dev);
4108		-
4109		- gen5_gt_irq_postinstall(dev);
	3374	+ gen5_gt_irq_postinstall(&dev_priv->gt);
4110	3375
4111	3376	spin_lock_irq(&dev_priv->irq_lock);
4112	3377	if (dev_priv->display_irqs_enabled)
..	..	@@ -4115,69 +3380,27 @@
4115	3380
4116	3381	I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
4117	3382	POSTING_READ(VLV_MASTER_IER);
4118		-
4119		- return 0;
4120		-}
4121		-
4122		-static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
4123		-{
4124		- /* These are interrupts we'll toggle with the ring mask register */
4125		- uint32_t gt_interrupts[] = {
4126		- GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT \|
4127		- GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT \|
4128		- GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT \|
4129		- GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
4130		- GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT \|
4131		- GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT \|
4132		- GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT \|
4133		- GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
4134		- 0,
4135		- GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT \|
4136		- GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
4137		- };
4138		-
4139		- if (HAS_L3_DPF(dev_priv))
4140		- gt_interrupts[0] \|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
4141		-
4142		- dev_priv->pm_ier = 0x0;
4143		- dev_priv->pm_imr = ~dev_priv->pm_ier;
4144		- GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
4145		- GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
4146		- /*
4147		- * RPS interrupts will get enabled/disabled on demand when RPS itself
4148		- * is enabled/disabled. Same wil be the case for GuC interrupts.
4149		- */
4150		- GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_imr, dev_priv->pm_ier);
4151		- GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
4152	3383	}
4153	3384
4154	3385	static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
4155	3386	{
4156		- uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
4157		- uint32_t de_pipe_enables;
4158		- u32 de_port_masked = GEN8_AUX_CHANNEL_A;
	3387	+ struct intel_uncore *uncore = &dev_priv->uncore;
	3388	+
	3389	+ u32 de_pipe_masked = gen8_de_pipe_fault_mask(dev_priv) \|
	3390	+ GEN8_PIPE_CDCLK_CRC_DONE;
	3391	+ u32 de_pipe_enables;
	3392	+ u32 de_port_masked = gen8_de_port_aux_mask(dev_priv);
4159	3393	u32 de_port_enables;
4160	3394	u32 de_misc_masked = GEN8_DE_EDP_PSR;
	3395	+ u32 trans_mask = BIT(TRANSCODER_A) \| BIT(TRANSCODER_B) \|
	3396	+ BIT(TRANSCODER_C) \| BIT(TRANSCODER_D);
4161	3397	enum pipe pipe;
4162	3398
4163	3399	if (INTEL_GEN(dev_priv) <= 10)
4164	3400	de_misc_masked \|= GEN8_DE_MISC_GSE;
4165	3401
4166		- if (INTEL_GEN(dev_priv) >= 9) {
4167		- de_pipe_masked \|= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
4168		- de_port_masked \|= GEN9_AUX_CHANNEL_B \| GEN9_AUX_CHANNEL_C \|
4169		- GEN9_AUX_CHANNEL_D;
4170		- if (IS_GEN9_LP(dev_priv))
4171		- de_port_masked \|= BXT_DE_PORT_GMBUS;
4172		- } else {
4173		- de_pipe_masked \|= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
4174		- }
4175		-
4176		- if (INTEL_GEN(dev_priv) >= 11)
4177		- de_port_masked \|= ICL_AUX_CHANNEL_E;
4178		-
4179		- if (IS_CNL_WITH_PORT_F(dev_priv) \|\| INTEL_GEN(dev_priv) >= 11)
4180		- de_port_masked \|= CNL_AUX_CHANNEL_F;
	3402	+ if (IS_GEN9_LP(dev_priv))
	3403	+ de_port_masked \|= BXT_DE_PORT_GMBUS;
4181	3404
4182	3405	de_pipe_enables = de_pipe_masked \| GEN8_PIPE_VBLANK \|
4183	3406	GEN8_PIPE_FIFO_UNDERRUN;
..	..	@@ -4188,28 +3411,42 @@
4188	3411	else if (IS_BROADWELL(dev_priv))
4189	3412	de_port_enables \|= GEN8_PORT_DP_A_HOTPLUG;
4190	3413
4191		- gen3_assert_iir_is_zero(dev_priv, EDP_PSR_IIR);
4192		- intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
	3414	+ if (INTEL_GEN(dev_priv) >= 12) {
	3415	+ enum transcoder trans;
	3416	+
	3417	+ for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {
	3418	+ enum intel_display_power_domain domain;
	3419	+
	3420	+ domain = POWER_DOMAIN_TRANSCODER(trans);
	3421	+ if (!intel_display_power_is_enabled(dev_priv, domain))
	3422	+ continue;
	3423	+
	3424	+ gen3_assert_iir_is_zero(uncore, TRANS_PSR_IIR(trans));
	3425	+ }
	3426	+ } else {
	3427	+ gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
	3428	+ }
4193	3429
4194	3430	for_each_pipe(dev_priv, pipe) {
4195	3431	dev_priv->de_irq_mask[pipe] = ~de_pipe_masked;
4196	3432
4197	3433	if (intel_display_power_is_enabled(dev_priv,
4198	3434	POWER_DOMAIN_PIPE(pipe)))
4199		- GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
	3435	+ GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
4200	3436	dev_priv->de_irq_mask[pipe],
4201	3437	de_pipe_enables);
4202	3438	}
4203	3439
4204		- GEN3_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
4205		- GEN3_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
	3440	+ GEN3_IRQ_INIT(uncore, GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
	3441	+ GEN3_IRQ_INIT(uncore, GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
4206	3442
4207	3443	if (INTEL_GEN(dev_priv) >= 11) {
4208	3444	u32 de_hpd_masked = 0;
4209	3445	u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK \|
4210	3446	GEN11_DE_TBT_HOTPLUG_MASK;
4211	3447
4212		- GEN3_IRQ_INIT(GEN11_DE_HPD_, ~de_hpd_masked, de_hpd_enables);
	3448	+ GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked,
	3449	+ de_hpd_enables);
4213	3450	gen11_hpd_detection_setup(dev_priv);
4214	3451	} else if (IS_GEN9_LP(dev_priv)) {
4215	3452	bxt_hpd_detection_setup(dev_priv);
..	..	@@ -4218,93 +3455,72 @@
4218	3455	}
4219	3456	}
4220	3457
4221		-static int gen8_irq_postinstall(struct drm_device *dev)
	3458	+static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
4222	3459	{
4223		- struct drm_i915_private *dev_priv = to_i915(dev);
4224		-
4225	3460	if (HAS_PCH_SPLIT(dev_priv))
4226		- ibx_irq_pre_postinstall(dev);
	3461	+ ibx_irq_pre_postinstall(dev_priv);
4227	3462
4228		- gen8_gt_irq_postinstall(dev_priv);
	3463	+ gen8_gt_irq_postinstall(&dev_priv->gt);
4229	3464	gen8_de_irq_postinstall(dev_priv);
4230	3465
4231	3466	if (HAS_PCH_SPLIT(dev_priv))
4232		- ibx_irq_postinstall(dev);
	3467	+ ibx_irq_postinstall(dev_priv);
4233	3468
4234		- I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
4235		- POSTING_READ(GEN8_MASTER_IRQ);
4236		-
4237		- return 0;
	3469	+ gen8_master_intr_enable(dev_priv->uncore.regs);
4238	3470	}
4239	3471
4240		-static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv)
	3472	+static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
4241	3473	{
4242		- const u32 irqs = GT_RENDER_USER_INTERRUPT \| GT_CONTEXT_SWITCH_INTERRUPT;
4243		-
4244		- BUILD_BUG_ON(irqs & 0xffff0000);
4245		-
4246		- /* Enable RCS, BCS, VCS and VECS class interrupts. */
4247		- I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, irqs << 16 \| irqs);
4248		- I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE, irqs << 16 \| irqs);
4249		-
4250		- /* Unmask irqs on RCS, BCS, VCS and VECS engines. */
4251		- I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK, ~(irqs << 16));
4252		- I915_WRITE(GEN11_BCS_RSVD_INTR_MASK, ~(irqs << 16));
4253		- I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK, ~(irqs \| irqs << 16));
4254		- I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK, ~(irqs \| irqs << 16));
4255		- I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK, ~(irqs \| irqs << 16));
4256		-
4257		- /*
4258		- * RPS interrupts will get enabled/disabled on demand when RPS itself
4259		- * is enabled/disabled.
4260		- */
4261		- dev_priv->pm_ier = 0x0;
4262		- dev_priv->pm_imr = ~dev_priv->pm_ier;
4263		- I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
4264		- I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
4265		-}
4266		-
4267		-static void icp_irq_postinstall(struct drm_device *dev)
4268		-{
4269		- struct drm_i915_private *dev_priv = to_i915(dev);
4270	3474	u32 mask = SDE_GMBUS_ICP;
4271	3475
4272		- WARN_ON(I915_READ(SDEIER) != 0);
	3476	+ drm_WARN_ON(&dev_priv->drm, I915_READ(SDEIER) != 0);
4273	3477	I915_WRITE(SDEIER, 0xffffffff);
4274	3478	POSTING_READ(SDEIER);
4275	3479
4276		- gen3_assert_iir_is_zero(dev_priv, SDEIIR);
	3480	+ gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
4277	3481	I915_WRITE(SDEIMR, ~mask);
4278	3482
4279		- icp_hpd_detection_setup(dev_priv);
	3483	+ if (HAS_PCH_TGP(dev_priv)) {
	3484	+ icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK);
	3485	+ icp_tc_hpd_detection_setup(dev_priv, TGP_TC_HPD_ENABLE_MASK);
	3486	+ } else if (HAS_PCH_JSP(dev_priv)) {
	3487	+ icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK);
	3488	+ } else if (HAS_PCH_MCC(dev_priv)) {
	3489	+ icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
	3490	+ icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE(PORT_TC1));
	3491	+ } else {
	3492	+ icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
	3493	+ icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE_MASK);
	3494	+ }
4280	3495	}
4281	3496
4282		-static int gen11_irq_postinstall(struct drm_device *dev)
	3497	+static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
4283	3498	{
4284		- struct drm_i915_private *dev_priv = dev->dev_private;
	3499	+ struct intel_uncore *uncore = &dev_priv->uncore;
4285	3500	u32 gu_misc_masked = GEN11_GU_MISC_GSE;
4286	3501
4287		- if (HAS_PCH_ICP(dev_priv))
4288		- icp_irq_postinstall(dev);
	3502	+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
	3503	+ icp_irq_postinstall(dev_priv);
4289	3504
4290		- gen11_gt_irq_postinstall(dev_priv);
	3505	+ gen11_gt_irq_postinstall(&dev_priv->gt);
4291	3506	gen8_de_irq_postinstall(dev_priv);
4292	3507
4293		- GEN3_IRQ_INIT(GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
	3508	+ GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
4294	3509
4295	3510	I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
4296	3511
4297		- I915_WRITE(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
4298		- POSTING_READ(GEN11_GFX_MSTR_IRQ);
4299		-
4300		- return 0;
	3512	+ if (HAS_MASTER_UNIT_IRQ(dev_priv)) {
	3513	+ dg1_master_intr_enable(uncore->regs);
	3514	+ POSTING_READ(DG1_MSTR_UNIT_INTR);
	3515	+ } else {
	3516	+ gen11_master_intr_enable(uncore->regs);
	3517	+ POSTING_READ(GEN11_GFX_MSTR_IRQ);
	3518	+ }
4301	3519	}
4302	3520
4303		-static int cherryview_irq_postinstall(struct drm_device *dev)
	3521	+static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
4304	3522	{
4305		- struct drm_i915_private *dev_priv = to_i915(dev);
4306		-
4307		- gen8_gt_irq_postinstall(dev_priv);
	3523	+ gen8_gt_irq_postinstall(&dev_priv->gt);
4308	3524
4309	3525	spin_lock_irq(&dev_priv->irq_lock);
4310	3526	if (dev_priv->display_irqs_enabled)
..	..	@@ -4313,28 +3529,26 @@
4313	3529
4314	3530	I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
4315	3531	POSTING_READ(GEN8_MASTER_IRQ);
4316		-
4317		- return 0;
4318	3532	}
4319	3533
4320		-static void i8xx_irq_reset(struct drm_device *dev)
	3534	+static void i8xx_irq_reset(struct drm_i915_private *dev_priv)
4321	3535	{
4322		- struct drm_i915_private *dev_priv = to_i915(dev);
	3536	+ struct intel_uncore *uncore = &dev_priv->uncore;
4323	3537
4324	3538	i9xx_pipestat_irq_reset(dev_priv);
4325	3539
4326		- I915_WRITE16(HWSTAM, 0xffff);
4327		-
4328		- GEN2_IRQ_RESET();
	3540	+ GEN2_IRQ_RESET(uncore);
4329	3541	}
4330	3542
4331		-static int i8xx_irq_postinstall(struct drm_device *dev)
	3543	+static void i8xx_irq_postinstall(struct drm_i915_private *dev_priv)
4332	3544	{
4333		- struct drm_i915_private *dev_priv = to_i915(dev);
	3545	+ struct intel_uncore *uncore = &dev_priv->uncore;
4334	3546	u16 enable_mask;
4335	3547
4336		- I915_WRITE16(EMR, ~(I915_ERROR_PAGE_TABLE \|
4337		- I915_ERROR_MEMORY_REFRESH));
	3548	+ intel_uncore_write16(uncore,
	3549	+ EMR,
	3550	+ ~(I915_ERROR_PAGE_TABLE \|
	3551	+ I915_ERROR_MEMORY_REFRESH));
4338	3552
4339	3553	/* Unmask the interrupts that we always want on. */
4340	3554	dev_priv->irq_mask =
..	..	@@ -4348,7 +3562,7 @@
4348	3562	I915_MASTER_ERROR_INTERRUPT \|
4349	3563	I915_USER_INTERRUPT;
4350	3564
4351		- GEN2_IRQ_INIT(, dev_priv->irq_mask, enable_mask);
	3565	+ GEN2_IRQ_INIT(uncore, dev_priv->irq_mask, enable_mask);
4352	3566
4353	3567	/* Interrupt setup is already guaranteed to be single-threaded, this is
4354	3568	* just to make the assert_spin_locked check happy. */
..	..	@@ -4356,21 +3570,20 @@
4356	3570	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4357	3571	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4358	3572	spin_unlock_irq(&dev_priv->irq_lock);
4359		-
4360		- return 0;
4361	3573	}
4362	3574
4363		-static void i8xx_error_irq_ack(struct drm_i915_private *dev_priv,
	3575	+static void i8xx_error_irq_ack(struct drm_i915_private *i915,
4364	3576	u16 eir, u16 eir_stuck)
4365	3577	{
	3578	+ struct intel_uncore *uncore = &i915->uncore;
4366	3579	u16 emr;
4367	3580
4368		- *eir = I915_READ16(EIR);
	3581	+ *eir = intel_uncore_read16(uncore, EIR);
4369	3582
4370	3583	if (*eir)
4371		- I915_WRITE16(EIR, *eir);
	3584	+ intel_uncore_write16(uncore, EIR, *eir);
4372	3585
4373		- *eir_stuck = I915_READ16(EIR);
	3586	+ *eir_stuck = intel_uncore_read16(uncore, EIR);
4374	3587	if (*eir_stuck == 0)
4375	3588	return;
4376	3589
..	..	@@ -4384,9 +3597,9 @@
4384	3597	* (or by a GPU reset) so we mask any bit that
4385	3598	* remains set.
4386	3599	*/
4387		- emr = I915_READ16(EMR);
4388		- I915_WRITE16(EMR, 0xffff);
4389		- I915_WRITE16(EMR, emr \| *eir_stuck);
	3600	+ emr = intel_uncore_read16(uncore, EMR);
	3601	+ intel_uncore_write16(uncore, EMR, 0xffff);
	3602	+ intel_uncore_write16(uncore, EMR, emr \| *eir_stuck);
4390	3603	}
4391	3604
4392	3605	static void i8xx_error_irq_handler(struct drm_i915_private *dev_priv,
..	..	@@ -4395,7 +3608,8 @@
4395	3608	DRM_DEBUG("Master Error: EIR 0x%04x\n", eir);
4396	3609
4397	3610	if (eir_stuck)
4398		- DRM_DEBUG_DRIVER("EIR stuck: 0x%04x, masked\n", eir_stuck);
	3611	+ drm_dbg(&dev_priv->drm, "EIR stuck: 0x%04x, masked\n",
	3612	+ eir_stuck);
4399	3613	}
4400	3614
4401	3615	static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv,
..	..	@@ -4432,27 +3646,27 @@
4432	3646	DRM_DEBUG("Master Error, EIR 0x%08x\n", eir);
4433	3647
4434	3648	if (eir_stuck)
4435		- DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masked\n", eir_stuck);
	3649	+ drm_dbg(&dev_priv->drm, "EIR stuck: 0x%08x, masked\n",
	3650	+ eir_stuck);
4436	3651	}
4437	3652
4438	3653	static irqreturn_t i8xx_irq_handler(int irq, void *arg)
4439	3654	{
4440		- struct drm_device *dev = arg;
4441		- struct drm_i915_private *dev_priv = to_i915(dev);
	3655	+ struct drm_i915_private *dev_priv = arg;
4442	3656	irqreturn_t ret = IRQ_NONE;
4443	3657
4444	3658	if (!intel_irqs_enabled(dev_priv))
4445	3659	return IRQ_NONE;
4446	3660
4447	3661	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
4448		- disable_rpm_wakeref_asserts(dev_priv);
	3662	+ disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4449	3663
4450	3664	do {
4451	3665	u32 pipe_stats[I915_MAX_PIPES] = {};
4452	3666	u16 eir = 0, eir_stuck = 0;
4453	3667	u16 iir;
4454	3668
4455		- iir = I915_READ16(IIR);
	3669	+ iir = intel_uncore_read16(&dev_priv->uncore, GEN2_IIR);
4456	3670	if (iir == 0)
4457	3671	break;
4458	3672
..	..	@@ -4465,10 +3679,10 @@
4465	3679	if (iir & I915_MASTER_ERROR_INTERRUPT)
4466	3680	i8xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
4467	3681
4468		- I915_WRITE16(IIR, iir);
	3682	+ intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir);
4469	3683
4470	3684	if (iir & I915_USER_INTERRUPT)
4471		- notify_ring(dev_priv->engine[RCS]);
	3685	+ intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]);
4472	3686
4473	3687	if (iir & I915_MASTER_ERROR_INTERRUPT)
4474	3688	i8xx_error_irq_handler(dev_priv, eir, eir_stuck);
..	..	@@ -4476,14 +3690,14 @@
4476	3690	i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats);
4477	3691	} while (0);
4478	3692
4479		- enable_rpm_wakeref_asserts(dev_priv);
	3693	+ enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4480	3694
4481	3695	return ret;
4482	3696	}
4483	3697
4484		-static void i915_irq_reset(struct drm_device *dev)
	3698	+static void i915_irq_reset(struct drm_i915_private *dev_priv)
4485	3699	{
4486		- struct drm_i915_private *dev_priv = to_i915(dev);
	3700	+ struct intel_uncore *uncore = &dev_priv->uncore;
4487	3701
4488	3702	if (I915_HAS_HOTPLUG(dev_priv)) {
4489	3703	i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
..	..	@@ -4492,14 +3706,12 @@
4492	3706
4493	3707	i9xx_pipestat_irq_reset(dev_priv);
4494	3708
4495		- I915_WRITE(HWSTAM, 0xffffffff);
4496		-
4497		- GEN3_IRQ_RESET();
	3709	+ GEN3_IRQ_RESET(uncore, GEN2_);
4498	3710	}
4499	3711
4500		-static int i915_irq_postinstall(struct drm_device *dev)
	3712	+static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
4501	3713	{
4502		- struct drm_i915_private *dev_priv = to_i915(dev);
	3714	+ struct intel_uncore *uncore = &dev_priv->uncore;
4503	3715	u32 enable_mask;
4504	3716
4505	3717	I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE \|
..	..	@@ -4526,7 +3738,7 @@
4526	3738	dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
4527	3739	}
4528	3740
4529		- GEN3_IRQ_INIT(, dev_priv->irq_mask, enable_mask);
	3741	+ GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);
4530	3742
4531	3743	/* Interrupt setup is already guaranteed to be single-threaded, this is
4532	3744	* just to make the assert_spin_locked check happy. */
..	..	@@ -4536,21 +3748,18 @@
4536	3748	spin_unlock_irq(&dev_priv->irq_lock);
4537	3749
4538	3750	i915_enable_asle_pipestat(dev_priv);
4539		-
4540		- return 0;
4541	3751	}
4542	3752
4543	3753	static irqreturn_t i915_irq_handler(int irq, void *arg)
4544	3754	{
4545		- struct drm_device *dev = arg;
4546		- struct drm_i915_private *dev_priv = to_i915(dev);
	3755	+ struct drm_i915_private *dev_priv = arg;
4547	3756	irqreturn_t ret = IRQ_NONE;
4548	3757
4549	3758	if (!intel_irqs_enabled(dev_priv))
4550	3759	return IRQ_NONE;
4551	3760
4552	3761	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
4553		- disable_rpm_wakeref_asserts(dev_priv);
	3762	+ disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4554	3763
4555	3764	do {
4556	3765	u32 pipe_stats[I915_MAX_PIPES] = {};
..	..	@@ -4558,7 +3767,7 @@
4558	3767	u32 hotplug_status = 0;
4559	3768	u32 iir;
4560	3769
4561		- iir = I915_READ(IIR);
	3770	+ iir = I915_READ(GEN2_IIR);
4562	3771	if (iir == 0)
4563	3772	break;
4564	3773
..	..	@@ -4575,10 +3784,10 @@
4575	3784	if (iir & I915_MASTER_ERROR_INTERRUPT)
4576	3785	i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
4577	3786
4578		- I915_WRITE(IIR, iir);
	3787	+ I915_WRITE(GEN2_IIR, iir);
4579	3788
4580	3789	if (iir & I915_USER_INTERRUPT)
4581		- notify_ring(dev_priv->engine[RCS]);
	3790	+ intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]);
4582	3791
4583	3792	if (iir & I915_MASTER_ERROR_INTERRUPT)
4584	3793	i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
..	..	@@ -4589,28 +3798,26 @@
4589	3798	i915_pipestat_irq_handler(dev_priv, iir, pipe_stats);
4590	3799	} while (0);
4591	3800
4592		- enable_rpm_wakeref_asserts(dev_priv);
	3801	+ enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4593	3802
4594	3803	return ret;
4595	3804	}
4596	3805
4597		-static void i965_irq_reset(struct drm_device *dev)
	3806	+static void i965_irq_reset(struct drm_i915_private *dev_priv)
4598	3807	{
4599		- struct drm_i915_private *dev_priv = to_i915(dev);
	3808	+ struct intel_uncore *uncore = &dev_priv->uncore;
4600	3809
4601	3810	i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4602	3811	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4603	3812
4604	3813	i9xx_pipestat_irq_reset(dev_priv);
4605	3814
4606		- I915_WRITE(HWSTAM, 0xffffffff);
4607		-
4608		- GEN3_IRQ_RESET();
	3815	+ GEN3_IRQ_RESET(uncore, GEN2_);
4609	3816	}
4610	3817
4611		-static int i965_irq_postinstall(struct drm_device *dev)
	3818	+static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
4612	3819	{
4613		- struct drm_i915_private *dev_priv = to_i915(dev);
	3820	+ struct intel_uncore *uncore = &dev_priv->uncore;
4614	3821	u32 enable_mask;
4615	3822	u32 error_mask;
4616	3823
..	..	@@ -4648,7 +3855,7 @@
4648	3855	if (IS_G4X(dev_priv))
4649	3856	enable_mask \|= I915_BSD_USER_INTERRUPT;
4650	3857
4651		- GEN3_IRQ_INIT(, dev_priv->irq_mask, enable_mask);
	3858	+ GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);
4652	3859
4653	3860	/* Interrupt setup is already guaranteed to be single-threaded, this is
4654	3861	* just to make the assert_spin_locked check happy. */
..	..	@@ -4659,8 +3866,6 @@
4659	3866	spin_unlock_irq(&dev_priv->irq_lock);
4660	3867
4661	3868	i915_enable_asle_pipestat(dev_priv);
4662		-
4663		- return 0;
4664	3869	}
4665	3870
4666	3871	static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
..	..	@@ -4690,15 +3895,14 @@
4690	3895
4691	3896	static irqreturn_t i965_irq_handler(int irq, void *arg)
4692	3897	{
4693		- struct drm_device *dev = arg;
4694		- struct drm_i915_private *dev_priv = to_i915(dev);
	3898	+ struct drm_i915_private *dev_priv = arg;
4695	3899	irqreturn_t ret = IRQ_NONE;
4696	3900
4697	3901	if (!intel_irqs_enabled(dev_priv))
4698	3902	return IRQ_NONE;
4699	3903
4700	3904	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
4701		- disable_rpm_wakeref_asserts(dev_priv);
	3905	+ disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4702	3906
4703	3907	do {
4704	3908	u32 pipe_stats[I915_MAX_PIPES] = {};
..	..	@@ -4706,7 +3910,7 @@
4706	3910	u32 hotplug_status = 0;
4707	3911	u32 iir;
4708	3912
4709		- iir = I915_READ(IIR);
	3913	+ iir = I915_READ(GEN2_IIR);
4710	3914	if (iir == 0)
4711	3915	break;
4712	3916
..	..	@@ -4722,13 +3926,13 @@
4722	3926	if (iir & I915_MASTER_ERROR_INTERRUPT)
4723	3927	i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
4724	3928
4725		- I915_WRITE(IIR, iir);
	3929	+ I915_WRITE(GEN2_IIR, iir);
4726	3930
4727	3931	if (iir & I915_USER_INTERRUPT)
4728		- notify_ring(dev_priv->engine[RCS]);
	3932	+ intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]);
4729	3933
4730	3934	if (iir & I915_BSD_USER_INTERRUPT)
4731		- notify_ring(dev_priv->engine[VCS]);
	3935	+ intel_engine_signal_breadcrumbs(dev_priv->gt.engine[VCS0]);
4732	3936
4733	3937	if (iir & I915_MASTER_ERROR_INTERRUPT)
4734	3938	i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
..	..	@@ -4739,7 +3943,7 @@
4739	3943	i965_pipestat_irq_handler(dev_priv, iir, pipe_stats);
4740	3944	} while (0);
4741	3945
4742		- enable_rpm_wakeref_asserts(dev_priv);
	3946	+ enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4743	3947
4744	3948	return ret;
4745	3949	}
..	..	@@ -4754,59 +3958,21 @@
4754	3958	void intel_irq_init(struct drm_i915_private *dev_priv)
4755	3959	{
4756	3960	struct drm_device *dev = &dev_priv->drm;
4757		- struct intel_rps *rps = &dev_priv->gt_pm.rps;
4758	3961	int i;
	3962	+
	3963	+ intel_hpd_init_pins(dev_priv);
4759	3964
4760	3965	intel_hpd_init_work(dev_priv);
4761	3966
4762		- INIT_WORK(&rps->work, gen6_pm_rps_work);
4763		-
4764		- INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
	3967	+ INIT_WORK(&dev_priv->l3_parity.error_work, ivb_parity_work);
4765	3968	for (i = 0; i < MAX_L3_SLICES; ++i)
4766	3969	dev_priv->l3_parity.remap_info[i] = NULL;
4767	3970
4768		- if (HAS_GUC_SCHED(dev_priv))
4769		- dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT;
	3971	+ /* pre-gen11 the guc irqs bits are in the upper 16 bits of the pm reg */
	3972	+ if (HAS_GT_UC(dev_priv) && INTEL_GEN(dev_priv) < 11)
	3973	+ dev_priv->gt.pm_guc_events = GUC_INTR_GUC2HOST << 16;
4770	3974
4771		- /* Let's track the enabled rps events */
4772		- if (IS_VALLEYVIEW(dev_priv))
4773		- /* WaGsvRC0ResidencyMethod:vlv */
4774		- dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
4775		- else
4776		- dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4777		-
4778		- rps->pm_intrmsk_mbz = 0;
4779		-
4780		- /*
4781		- * SNB,IVB,HSW can while VLV,CHV may hard hang on looping batchbuffer
4782		- * if GEN6_PM_UP_EI_EXPIRED is masked.
4783		- *
4784		- * TODO: verify if this can be reproduced on VLV,CHV.
4785		- */
4786		- if (INTEL_GEN(dev_priv) <= 7)
4787		- rps->pm_intrmsk_mbz \|= GEN6_PM_RP_UP_EI_EXPIRED;
4788		-
4789		- if (INTEL_GEN(dev_priv) >= 8)
4790		- rps->pm_intrmsk_mbz \|= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
4791		-
4792		- if (IS_GEN2(dev_priv)) {
4793		- /* Gen2 doesn't have a hardware frame counter */
4794		- dev->max_vblank_count = 0;
4795		- } else if (IS_G4X(dev_priv) \|\| INTEL_GEN(dev_priv) >= 5) {
4796		- dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4797		- dev->driver->get_vblank_counter = g4x_get_vblank_counter;
4798		- } else {
4799		- dev->driver->get_vblank_counter = i915_get_vblank_counter;
4800		- dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4801		- }
4802		-
4803		- /*
4804		- * Opt out of the vblank disable timer on everything except gen2.
4805		- * Gen2 doesn't have a hardware frame counter and so depends on
4806		- * vblank interrupts to produce sane vblank seuquence numbers.
4807		- */
4808		- if (!IS_GEN2(dev_priv))
4809		- dev->vblank_disable_immediate = true;
	3975	+ dev->vblank_disable_immediate = true;
4810	3976
4811	3977	/* Most platforms treat the display irq block as an always-on
4812	3978	* power domain. vlv/chv can disable it at runtime and need
..	..	@@ -4819,81 +3985,30 @@
4819	3985	dev_priv->display_irqs_enabled = false;
4820	3986
4821	3987	dev_priv->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;
	3988	+ /* If we have MST support, we want to avoid doing short HPD IRQ storm
	3989	+ * detection, as short HPD storms will occur as a natural part of
	3990	+ * sideband messaging with MST.
	3991	+ * On older platforms however, IRQ storms can occur with both long and
	3992	+ * short pulses, as seen on some G4x systems.
	3993	+ */
	3994	+ dev_priv->hotplug.hpd_short_storm_enabled = !HAS_DP_MST(dev_priv);
4822	3995
4823		- dev->driver->get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos;
4824		- dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4825		-
4826		- if (IS_CHERRYVIEW(dev_priv)) {
4827		- dev->driver->irq_handler = cherryview_irq_handler;
4828		- dev->driver->irq_preinstall = cherryview_irq_reset;
4829		- dev->driver->irq_postinstall = cherryview_irq_postinstall;
4830		- dev->driver->irq_uninstall = cherryview_irq_reset;
4831		- dev->driver->enable_vblank = i965_enable_vblank;
4832		- dev->driver->disable_vblank = i965_disable_vblank;
4833		- dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4834		- } else if (IS_VALLEYVIEW(dev_priv)) {
4835		- dev->driver->irq_handler = valleyview_irq_handler;
4836		- dev->driver->irq_preinstall = valleyview_irq_reset;
4837		- dev->driver->irq_postinstall = valleyview_irq_postinstall;
4838		- dev->driver->irq_uninstall = valleyview_irq_reset;
4839		- dev->driver->enable_vblank = i965_enable_vblank;
4840		- dev->driver->disable_vblank = i965_disable_vblank;
4841		- dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4842		- } else if (INTEL_GEN(dev_priv) >= 11) {
4843		- dev->driver->irq_handler = gen11_irq_handler;
4844		- dev->driver->irq_preinstall = gen11_irq_reset;
4845		- dev->driver->irq_postinstall = gen11_irq_postinstall;
4846		- dev->driver->irq_uninstall = gen11_irq_reset;
4847		- dev->driver->enable_vblank = gen8_enable_vblank;
4848		- dev->driver->disable_vblank = gen8_disable_vblank;
4849		- dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
4850		- } else if (INTEL_GEN(dev_priv) >= 8) {
4851		- dev->driver->irq_handler = gen8_irq_handler;
4852		- dev->driver->irq_preinstall = gen8_irq_reset;
4853		- dev->driver->irq_postinstall = gen8_irq_postinstall;
4854		- dev->driver->irq_uninstall = gen8_irq_reset;
4855		- dev->driver->enable_vblank = gen8_enable_vblank;
4856		- dev->driver->disable_vblank = gen8_disable_vblank;
4857		- if (IS_GEN9_LP(dev_priv))
	3996	+ if (HAS_GMCH(dev_priv)) {
	3997	+ if (I915_HAS_HOTPLUG(dev_priv))
	3998	+ dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
	3999	+ } else {
	4000	+ if (HAS_PCH_JSP(dev_priv))
	4001	+ dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup;
	4002	+ else if (HAS_PCH_MCC(dev_priv))
	4003	+ dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup;
	4004	+ else if (INTEL_GEN(dev_priv) >= 11)
	4005	+ dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
	4006	+ else if (IS_GEN9_LP(dev_priv))
4858	4007	dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4859		- else if (HAS_PCH_SPT(dev_priv) \|\| HAS_PCH_KBP(dev_priv) \|\|
4860		- HAS_PCH_CNP(dev_priv))
	4008	+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
4861	4009	dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4862	4010	else
4863	4011	dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4864		- } else if (HAS_PCH_SPLIT(dev_priv)) {
4865		- dev->driver->irq_handler = ironlake_irq_handler;
4866		- dev->driver->irq_preinstall = ironlake_irq_reset;
4867		- dev->driver->irq_postinstall = ironlake_irq_postinstall;
4868		- dev->driver->irq_uninstall = ironlake_irq_reset;
4869		- dev->driver->enable_vblank = ironlake_enable_vblank;
4870		- dev->driver->disable_vblank = ironlake_disable_vblank;
4871		- dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4872		- } else {
4873		- if (IS_GEN2(dev_priv)) {
4874		- dev->driver->irq_preinstall = i8xx_irq_reset;
4875		- dev->driver->irq_postinstall = i8xx_irq_postinstall;
4876		- dev->driver->irq_handler = i8xx_irq_handler;
4877		- dev->driver->irq_uninstall = i8xx_irq_reset;
4878		- dev->driver->enable_vblank = i8xx_enable_vblank;
4879		- dev->driver->disable_vblank = i8xx_disable_vblank;
4880		- } else if (IS_GEN3(dev_priv)) {
4881		- dev->driver->irq_preinstall = i915_irq_reset;
4882		- dev->driver->irq_postinstall = i915_irq_postinstall;
4883		- dev->driver->irq_uninstall = i915_irq_reset;
4884		- dev->driver->irq_handler = i915_irq_handler;
4885		- dev->driver->enable_vblank = i8xx_enable_vblank;
4886		- dev->driver->disable_vblank = i8xx_disable_vblank;
4887		- } else {
4888		- dev->driver->irq_preinstall = i965_irq_reset;
4889		- dev->driver->irq_postinstall = i965_irq_postinstall;
4890		- dev->driver->irq_uninstall = i965_irq_reset;
4891		- dev->driver->irq_handler = i965_irq_handler;
4892		- dev->driver->enable_vblank = i965_enable_vblank;
4893		- dev->driver->disable_vblank = i965_disable_vblank;
4894		- }
4895		- if (I915_HAS_HOTPLUG(dev_priv))
4896		- dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4897	4012	}
4898	4013	}
4899	4014
..	..	@@ -4911,6 +4026,77 @@
4911	4026	kfree(i915->l3_parity.remap_info[i]);
4912	4027	}
4913	4028
	4029	+static irq_handler_t intel_irq_handler(struct drm_i915_private *dev_priv)
	4030	+{
	4031	+ if (HAS_GMCH(dev_priv)) {
	4032	+ if (IS_CHERRYVIEW(dev_priv))
	4033	+ return cherryview_irq_handler;
	4034	+ else if (IS_VALLEYVIEW(dev_priv))
	4035	+ return valleyview_irq_handler;
	4036	+ else if (IS_GEN(dev_priv, 4))
	4037	+ return i965_irq_handler;
	4038	+ else if (IS_GEN(dev_priv, 3))
	4039	+ return i915_irq_handler;
	4040	+ else
	4041	+ return i8xx_irq_handler;
	4042	+ } else {
	4043	+ if (HAS_MASTER_UNIT_IRQ(dev_priv))
	4044	+ return dg1_irq_handler;
	4045	+ if (INTEL_GEN(dev_priv) >= 11)
	4046	+ return gen11_irq_handler;
	4047	+ else if (INTEL_GEN(dev_priv) >= 8)
	4048	+ return gen8_irq_handler;
	4049	+ else
	4050	+ return ilk_irq_handler;
	4051	+ }
	4052	+}
	4053	+
	4054	+static void intel_irq_reset(struct drm_i915_private *dev_priv)
	4055	+{
	4056	+ if (HAS_GMCH(dev_priv)) {
	4057	+ if (IS_CHERRYVIEW(dev_priv))
	4058	+ cherryview_irq_reset(dev_priv);
	4059	+ else if (IS_VALLEYVIEW(dev_priv))
	4060	+ valleyview_irq_reset(dev_priv);
	4061	+ else if (IS_GEN(dev_priv, 4))
	4062	+ i965_irq_reset(dev_priv);
	4063	+ else if (IS_GEN(dev_priv, 3))
	4064	+ i915_irq_reset(dev_priv);
	4065	+ else
	4066	+ i8xx_irq_reset(dev_priv);
	4067	+ } else {
	4068	+ if (INTEL_GEN(dev_priv) >= 11)
	4069	+ gen11_irq_reset(dev_priv);
	4070	+ else if (INTEL_GEN(dev_priv) >= 8)
	4071	+ gen8_irq_reset(dev_priv);
	4072	+ else
	4073	+ ilk_irq_reset(dev_priv);
	4074	+ }
	4075	+}
	4076	+
	4077	+static void intel_irq_postinstall(struct drm_i915_private *dev_priv)
	4078	+{
	4079	+ if (HAS_GMCH(dev_priv)) {
	4080	+ if (IS_CHERRYVIEW(dev_priv))
	4081	+ cherryview_irq_postinstall(dev_priv);
	4082	+ else if (IS_VALLEYVIEW(dev_priv))
	4083	+ valleyview_irq_postinstall(dev_priv);
	4084	+ else if (IS_GEN(dev_priv, 4))
	4085	+ i965_irq_postinstall(dev_priv);
	4086	+ else if (IS_GEN(dev_priv, 3))
	4087	+ i915_irq_postinstall(dev_priv);
	4088	+ else
	4089	+ i8xx_irq_postinstall(dev_priv);
	4090	+ } else {
	4091	+ if (INTEL_GEN(dev_priv) >= 11)
	4092	+ gen11_irq_postinstall(dev_priv);
	4093	+ else if (INTEL_GEN(dev_priv) >= 8)
	4094	+ gen8_irq_postinstall(dev_priv);
	4095	+ else
	4096	+ ilk_irq_postinstall(dev_priv);
	4097	+ }
	4098	+}
	4099	+
4914	4100	/**
4915	4101	* intel_irq_install - enables the hardware interrupt
4916	4102	* @dev_priv: i915 device instance
..	..	@@ -4924,6 +4110,9 @@
4924	4110	*/
4925	4111	int intel_irq_install(struct drm_i915_private *dev_priv)
4926	4112	{
	4113	+ int irq = dev_priv->drm.pdev->irq;
	4114	+ int ret;
	4115	+
4927	4116	/*
4928	4117	* We enable some interrupt sources in our postinstall hooks, so mark
4929	4118	* interrupts as enabled _before_ actually enabling them to avoid
..	..	@@ -4931,7 +4120,20 @@
4931	4120	*/
4932	4121	dev_priv->runtime_pm.irqs_enabled = true;
4933	4122
4934		- return drm_irq_install(&dev_priv->drm, dev_priv->drm.pdev->irq);
	4123	+ dev_priv->drm.irq_enabled = true;
	4124	+
	4125	+ intel_irq_reset(dev_priv);
	4126	+
	4127	+ ret = request_irq(irq, intel_irq_handler(dev_priv),
	4128	+ IRQF_SHARED, DRIVER_NAME, dev_priv);
	4129	+ if (ret < 0) {
	4130	+ dev_priv->drm.irq_enabled = false;
	4131	+ return ret;
	4132	+ }
	4133	+
	4134	+ intel_irq_postinstall(dev_priv);
	4135	+
	4136	+ return ret;
4935	4137	}
4936	4138
4937	4139	/**
..	..	@@ -4943,7 +4145,23 @@
4943	4145	*/
4944	4146	void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4945	4147	{
4946		- drm_irq_uninstall(&dev_priv->drm);
	4148	+ int irq = dev_priv->drm.pdev->irq;
	4149	+
	4150	+ /*
	4151	+ * FIXME we can get called twice during driver probe
	4152	+ * error handling as well as during driver remove due to
	4153	+ * intel_modeset_driver_remove() calling us out of sequence.
	4154	+ * Would be nice if it didn't do that...
	4155	+ */
	4156	+ if (!dev_priv->drm.irq_enabled)
	4157	+ return;
	4158	+
	4159	+ dev_priv->drm.irq_enabled = false;
	4160	+
	4161	+ intel_irq_reset(dev_priv);
	4162	+
	4163	+ free_irq(irq, dev_priv);
	4164	+
4947	4165	intel_hpd_cancel_work(dev_priv);
4948	4166	dev_priv->runtime_pm.irqs_enabled = false;
4949	4167	}
..	..	@@ -4957,9 +4175,9 @@
4957	4175	*/
4958	4176	void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4959	4177	{
4960		- dev_priv->drm.driver->irq_uninstall(&dev_priv->drm);
	4178	+ intel_irq_reset(dev_priv);
4961	4179	dev_priv->runtime_pm.irqs_enabled = false;
4962		- synchronize_irq(dev_priv->drm.irq);
	4180	+ intel_synchronize_irq(dev_priv);
4963	4181	}
4964	4182
4965	4183	/**
..	..	@@ -4972,6 +4190,20 @@
4972	4190	void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4973	4191	{
4974	4192	dev_priv->runtime_pm.irqs_enabled = true;
4975		- dev_priv->drm.driver->irq_preinstall(&dev_priv->drm);
4976		- dev_priv->drm.driver->irq_postinstall(&dev_priv->drm);
	4193	+ intel_irq_reset(dev_priv);
	4194	+ intel_irq_postinstall(dev_priv);
	4195	+}
	4196	+
	4197	+bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
	4198	+{
	4199	+ /*
	4200	+ * We only use drm_irq_uninstall() at unload and VT switch, so
	4201	+ * this is the only thing we need to check.
	4202	+ */
	4203	+ return dev_priv->runtime_pm.irqs_enabled;
	4204	+}
	4205	+
	4206	+void intel_synchronize_irq(struct drm_i915_private *i915)
	4207	+{
	4208	+ synchronize_irq(i915->drm.pdev->irq);
4977	4209	}