add dts config

hc

2023-12-06 08f87f769b595151be1afeff53e144f543faa614

 kernel/drivers/gpu/drm/armada/armada_plane.c
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@@ -1,15 +1,14 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright (C) 2012 Russell King
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  *  Rewritten from the dovefb driver, and Armada510 manuals.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  */
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-#include <drm/drmP.h>
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+
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 #include <drm/drm_atomic.h>
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 #include <drm/drm_atomic_helper.h>
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+#include <drm/drm_fourcc.h>
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 #include <drm/drm_plane_helper.h>
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+
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 #include "armada_crtc.h"
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 #include "armada_drm.h"
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 #include "armada_fb.h"
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@@ -79,23 +78,6 @@
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 	}
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 }
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80
 
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-static unsigned armada_drm_crtc_calc_fb(struct drm_plane_state *state,
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-	struct armada_regs *regs, bool interlaced)
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-{
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-	u16 pitches[3];
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-	u32 addrs[2][3];
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-	unsigned i = 0;
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-
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-	armada_drm_plane_calc(state, addrs, pitches, interlaced);
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-
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-	/* write offset, base, and pitch */
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-	armada_reg_queue_set(regs, i, addrs[0][0], LCD_CFG_GRA_START_ADDR0);
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-	armada_reg_queue_set(regs, i, addrs[1][0], LCD_CFG_GRA_START_ADDR1);
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-	armada_reg_queue_mod(regs, i, pitches[0], 0xffff, LCD_CFG_GRA_PITCH);
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-
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-	return i;
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-}
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-
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 int armada_drm_plane_prepare_fb(struct drm_plane *plane,
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 	struct drm_plane_state *state)
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 {
..
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@@ -126,20 +108,50 @@
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 int armada_drm_plane_atomic_check(struct drm_plane *plane,
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 	struct drm_plane_state *state)
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 {
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-	if (state->fb && !WARN_ON(!state->crtc)) {
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-		struct drm_crtc *crtc = state->crtc;
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-		struct drm_crtc_state *crtc_state;
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+	struct armada_plane_state *st = to_armada_plane_state(state);
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+	struct drm_crtc *crtc = state->crtc;
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+	struct drm_crtc_state *crtc_state;
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+	bool interlace;
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+	int ret;
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-		if (state->state)
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-			crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
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-		else
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-			crtc_state = crtc->state;
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-		return drm_atomic_helper_check_plane_state(state, crtc_state,
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-							   0, INT_MAX,
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-							   true, false);
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-	} else {
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+	if (!state->fb || WARN_ON(!state->crtc)) {
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 		state->visible = false;
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+		return 0;
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 	}
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+
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+	if (state->state)
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+		crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
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+	else
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+		crtc_state = crtc->state;
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+
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+	ret = drm_atomic_helper_check_plane_state(state, crtc_state, 0,
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+						  INT_MAX, true, false);
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+	if (ret)
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+		return ret;
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+
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+	interlace = crtc_state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE;
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+	if (interlace) {
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+		if ((state->dst.y1 | state->dst.y2) & 1)
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+			return -EINVAL;
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+		st->src_hw = drm_rect_height(&state->src) >> 17;
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+		st->dst_yx = state->dst.y1 >> 1;
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+		st->dst_hw = drm_rect_height(&state->dst) >> 1;
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+	} else {
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+		st->src_hw = drm_rect_height(&state->src) >> 16;
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+		st->dst_yx = state->dst.y1;
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+		st->dst_hw = drm_rect_height(&state->dst);
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+	}
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+
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+	st->src_hw <<= 16;
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+	st->src_hw |= drm_rect_width(&state->src) >> 16;
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+	st->dst_yx <<= 16;
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+	st->dst_yx |= state->dst.x1 & 0x0000ffff;
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+	st->dst_hw <<= 16;
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+	st->dst_hw |= drm_rect_width(&state->dst) & 0x0000ffff;
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+
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+	armada_drm_plane_calc(state, st->addrs, st->pitches, interlace);
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+	st->interlace = interlace;
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+
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 	return 0;
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 }
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@@ -173,21 +185,25 @@
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 			val |= CFG_PDWN256x24;
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 		armada_reg_queue_mod(regs, idx, 0, val, LCD_SPU_SRAM_PARA1);
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 	}
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-	val = armada_rect_hw_fp(&state->src);
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-	if (armada_rect_hw_fp(&old_state->src) != val)
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+	val = armada_src_hw(state);
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+	if (armada_src_hw(old_state) != val)
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 		armada_reg_queue_set(regs, idx, val, LCD_SPU_GRA_HPXL_VLN);
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-	val = armada_rect_yx(&state->dst);
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-	if (armada_rect_yx(&old_state->dst) != val)
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+	val = armada_dst_yx(state);
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+	if (armada_dst_yx(old_state) != val)
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 		armada_reg_queue_set(regs, idx, val, LCD_SPU_GRA_OVSA_HPXL_VLN);
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-	val = armada_rect_hw(&state->dst);
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-	if (armada_rect_hw(&old_state->dst) != val)
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+	val = armada_dst_hw(state);
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+	if (armada_dst_hw(old_state) != val)
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 		armada_reg_queue_set(regs, idx, val, LCD_SPU_GZM_HPXL_VLN);
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 	if (old_state->src.x1 != state->src.x1 ||
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 	    old_state->src.y1 != state->src.y1 ||
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 	    old_state->fb != state->fb ||
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 	    state->crtc->state->mode_changed) {
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-		idx += armada_drm_crtc_calc_fb(state, regs + idx,
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-					       dcrtc->interlaced);
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+		armada_reg_queue_set(regs, idx, armada_addr(state, 0, 0),
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+				     LCD_CFG_GRA_START_ADDR0);
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+		armada_reg_queue_set(regs, idx, armada_addr(state, 1, 0),
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+				     LCD_CFG_GRA_START_ADDR1);
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+		armada_reg_queue_mod(regs, idx, armada_pitch(state, 0), 0xffff,
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+				     LCD_CFG_GRA_PITCH);
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 	}
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 	if (old_state->fb != state->fb ||
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 	    state->crtc->state->mode_changed) {
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@@ -197,7 +213,7 @@
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 			cfg |= CFG_PALETTE_ENA;
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 		if (state->visible)
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 			cfg |= CFG_GRA_ENA;
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-		if (dcrtc->interlaced)
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+		if (to_armada_plane_state(state)->interlace)
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 			cfg |= CFG_GRA_FTOGGLE;
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 		cfg_mask = CFG_GRAFORMAT |
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 			   CFG_GRA_MOD(CFG_SWAPRB | CFG_SWAPUV |
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@@ -248,7 +264,7 @@
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 	/* Disable plane and power down most RAMs and FIFOs */
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 	armada_reg_queue_mod(regs, idx, 0, CFG_GRA_ENA, LCD_SPU_DMA_CTRL0);
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 	armada_reg_queue_mod(regs, idx, CFG_PDWN256x32 | CFG_PDWN256x24 |
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-			     CFG_PDWN256x8 | CFG_PDWN32x32 | CFG_PDWN64x66,
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+			     CFG_PDWN32x32 | CFG_PDWN64x66,
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 			     0, LCD_SPU_SRAM_PARA1);
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 	dcrtc->regs_idx += idx;
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@@ -262,12 +278,37 @@
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 	.atomic_disable	= armada_drm_primary_plane_atomic_disable,
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 };
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+void armada_plane_reset(struct drm_plane *plane)
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+{
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+	struct armada_plane_state *st;
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+	if (plane->state)
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+		__drm_atomic_helper_plane_destroy_state(plane->state);
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+	kfree(plane->state);
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+	st = kzalloc(sizeof(*st), GFP_KERNEL);
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+	if (st)
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+		__drm_atomic_helper_plane_reset(plane, &st->base);
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+}
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+
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+struct drm_plane_state *armada_plane_duplicate_state(struct drm_plane *plane)
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+{
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+	struct armada_plane_state *st;
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+
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+	if (WARN_ON(!plane->state))
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+		return NULL;
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+
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+	st = kmemdup(plane->state, sizeof(*st), GFP_KERNEL);
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+	if (st)
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+		__drm_atomic_helper_plane_duplicate_state(plane, &st->base);
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+
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+	return &st->base;
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+}
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+
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 static const struct drm_plane_funcs armada_primary_plane_funcs = {
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 	.update_plane	= drm_atomic_helper_update_plane,
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 	.disable_plane	= drm_atomic_helper_disable_plane,
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 	.destroy	= drm_primary_helper_destroy,
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-	.reset		= drm_atomic_helper_plane_reset,
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-	.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
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+	.reset		= armada_plane_reset,
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+	.atomic_duplicate_state = armada_plane_duplicate_state,
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 	.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
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 };
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