forked from ~ljy/RK356X_SDK_RELEASE
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hc
2023-12-06 08f87f769b595151be1afeff53e144f543faa614 
 kernel/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
....@@ -35,26 +35,25 @@
3535 	return (u64)RREG32_SOC15(GC, 0, mmMC_VM_FB_OFFSET) << 24;
3636 }
3737 
38
-static void gfxhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
38
+void gfxhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
39
+				uint64_t page_table_base)
3940 {
40
-	uint64_t value;
41
+	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
4142 
42
-	BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
43
-	value = adev->gart.table_addr - adev->gmc.vram_start
44
-		+ adev->vm_manager.vram_base_offset;
45
-	value &= 0x0000FFFFFFFFF000ULL;
46
-	value |= 0x1; /*valid bit*/
43
+	WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
44
+			    hub->ctx_addr_distance * vmid,
45
+			    lower_32_bits(page_table_base));
4746 
48
-	WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
49
-		     lower_32_bits(value));
50
-
51
-	WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
52
-		     upper_32_bits(value));
47
+	WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
48
+			    hub->ctx_addr_distance * vmid,
49
+			    upper_32_bits(page_table_base));
5350 }
5451 
5552 static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
5653 {
57
-	gfxhub_v1_0_init_gart_pt_regs(adev);
54
+	uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
55
+
56
+	gfxhub_v1_0_setup_vm_pt_regs(adev, 0, pt_base);
5857 
5958 	WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
6059 		     (u32)(adev->gmc.gart_start >> 12));
....@@ -71,33 +70,50 @@
7170 {
7271 	uint64_t value;
7372 
74
-	/* Disable AGP. */
75
-	WREG32_SOC15(GC, 0, mmMC_VM_AGP_BASE, 0);
76
-	WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0);
77
-	WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, 0xFFFFFFFF);
73
+	/* Program the AGP BAR */
74
+	WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BASE, 0);
75
+	WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
76
+	WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
7877 
79
-	/* Program the system aperture low logical page number. */
80
-	WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
81
-		     adev->gmc.vram_start >> 18);
82
-	WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
83
-		     adev->gmc.vram_end >> 18);
78
+	if (!amdgpu_sriov_vf(adev) || adev->asic_type <= CHIP_VEGA10) {
79
+		/* Program the system aperture low logical page number. */
80
+		WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
81
+			min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
8482 
85
-	/* Set default page address. */
86
-	value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start
87
-		+ adev->vm_manager.vram_base_offset;
88
-	WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
89
-		     (u32)(value >> 12));
90
-	WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
91
-		     (u32)(value >> 44));
83
+		if (adev->apu_flags & AMD_APU_IS_RAVEN2)
84
+			/*
85
+			* Raven2 has a HW issue that it is unable to use the
86
+			* vram which is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR.
87
+			* So here is the workaround that increase system
88
+			* aperture high address (add 1) to get rid of the VM
89
+			* fault and hardware hang.
90
+			*/
91
+			WREG32_SOC15_RLC(GC, 0,
92
+					 mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
93
+					 max((adev->gmc.fb_end >> 18) + 0x1,
94
+					     adev->gmc.agp_end >> 18));
95
+		else
96
+			WREG32_SOC15_RLC(
97
+				GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
98
+				max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
9299 
93
-	/* Program "protection fault". */
94
-	WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
95
-		     (u32)(adev->dummy_page_addr >> 12));
96
-	WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
97
-		     (u32)((u64)adev->dummy_page_addr >> 44));
100
+		/* Set default page address. */
101
+		value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
102
+			adev->vm_manager.vram_base_offset;
103
+		WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
104
+			     (u32)(value >> 12));
105
+		WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
106
+			     (u32)(value >> 44));
98107 
99
-	WREG32_FIELD15(GC, 0, VM_L2_PROTECTION_FAULT_CNTL2,
100
-		       ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
108
+		/* Program "protection fault". */
109
+		WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
110
+			     (u32)(adev->dummy_page_addr >> 12));
111
+		WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
112
+			     (u32)((u64)adev->dummy_page_addr >> 44));
113
+
114
+		WREG32_FIELD15(GC, 0, VM_L2_PROTECTION_FAULT_CNTL2,
115
+			       ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
116
+	}
101117 }
102118 
103119 static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
....@@ -118,7 +134,7 @@
118134 			    MTYPE, MTYPE_UC);/* XXX for emulation. */
119135 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
120136 
121
-	WREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
137
+	WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
122138 }
123139 
124140 static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
....@@ -132,15 +148,15 @@
132148 	/* XXX for emulation, Refer to closed source code.*/
133149 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
134150 			    0);
135
-	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
151
+	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
136152 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
137153 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
138
-	WREG32_SOC15(GC, 0, mmVM_L2_CNTL, tmp);
154
+	WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL, tmp);
139155 
140156 	tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2);
141157 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
142158 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
143
-	WREG32_SOC15(GC, 0, mmVM_L2_CNTL2, tmp);
159
+	WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL2, tmp);
144160 
145161 	tmp = mmVM_L2_CNTL3_DEFAULT;
146162 	if (adev->gmc.translate_further) {
....@@ -152,12 +168,12 @@
152168 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
153169 				    L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
154170 	}
155
-	WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, tmp);
171
+	WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL3, tmp);
156172 
157173 	tmp = mmVM_L2_CNTL4_DEFAULT;
158174 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
159175 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
160
-	WREG32_SOC15(GC, 0, mmVM_L2_CNTL4, tmp);
176
+	WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL4, tmp);
161177 }
162178 
163179 static void gfxhub_v1_0_enable_system_domain(struct amdgpu_device *adev)
....@@ -167,6 +183,8 @@
167183 	tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL);
168184 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
169185 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
186
+	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,
187
+			    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
170188 	WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp);
171189 }
172190 
....@@ -189,6 +207,7 @@
189207 
190208 static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
191209 {
210
+	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
192211 	unsigned num_level, block_size;
193212 	uint32_t tmp;
194213 	int i;
....@@ -225,40 +244,47 @@
225244 				    block_size);
226245 		/* Send no-retry XNACK on fault to suppress VM fault storm. */
227246 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
228
-				    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
229
-		WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i, tmp);
230
-		WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);
231
-		WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);
232
-		WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,  i*2,
233
-			lower_32_bits(adev->vm_manager.max_pfn - 1));
234
-		WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2,
235
-			upper_32_bits(adev->vm_manager.max_pfn - 1));
247
+				    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
248
+				    !adev->gmc.noretry);
249
+		WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL,
250
+				    i * hub->ctx_distance, tmp);
251
+		WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
252
+				    i * hub->ctx_addr_distance, 0);
253
+		WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
254
+				    i * hub->ctx_addr_distance, 0);
255
+		WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
256
+				    i * hub->ctx_addr_distance,
257
+				    lower_32_bits(adev->vm_manager.max_pfn - 1));
258
+		WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
259
+				    i * hub->ctx_addr_distance,
260
+				    upper_32_bits(adev->vm_manager.max_pfn - 1));
236261 	}
237262 }
238263 
239264 static void gfxhub_v1_0_program_invalidation(struct amdgpu_device *adev)
240265 {
266
+	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
241267 	unsigned i;
242268 
243269 	for (i = 0 ; i < 18; ++i) {
244270 		WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
245
-				    2 * i, 0xffffffff);
271
+				    i * hub->eng_addr_distance, 0xffffffff);
246272 		WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
247
-				    2 * i, 0x1f);
273
+				    i * hub->eng_addr_distance, 0x1f);
248274 	}
249275 }
250276 
251277 int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
252278 {
253
-	if (amdgpu_sriov_vf(adev)) {
279
+	if (amdgpu_sriov_vf(adev) && adev->asic_type != CHIP_ARCTURUS) {
254280 		/*
255281 		 * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
256282 		 * VF copy registers so vbios post doesn't program them, for
257283 		 * SRIOV driver need to program them
258284 		 */
259
-		WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_BASE,
285
+		WREG32_SOC15_RLC(GC, 0, mmMC_VM_FB_LOCATION_BASE,
260286 			     adev->gmc.vram_start >> 24);
261
-		WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_TOP,
287
+		WREG32_SOC15_RLC(GC, 0, mmMC_VM_FB_LOCATION_TOP,
262288 			     adev->gmc.vram_end >> 24);
263289 	}
264290 
....@@ -266,10 +292,12 @@
266292 	gfxhub_v1_0_init_gart_aperture_regs(adev);
267293 	gfxhub_v1_0_init_system_aperture_regs(adev);
268294 	gfxhub_v1_0_init_tlb_regs(adev);
269
-	gfxhub_v1_0_init_cache_regs(adev);
295
+	if (!amdgpu_sriov_vf(adev))
296
+		gfxhub_v1_0_init_cache_regs(adev);
270297 
271298 	gfxhub_v1_0_enable_system_domain(adev);
272
-	gfxhub_v1_0_disable_identity_aperture(adev);
299
+	if (!amdgpu_sriov_vf(adev))
300
+		gfxhub_v1_0_disable_identity_aperture(adev);
273301 	gfxhub_v1_0_setup_vmid_config(adev);
274302 	gfxhub_v1_0_program_invalidation(adev);
275303 
....@@ -278,12 +306,14 @@
278306 
279307 void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev)
280308 {
309
+	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
281310 	u32 tmp;
282311 	u32 i;
283312 
284313 	/* Disable all tables */
285314 	for (i = 0; i < 16; i++)
286
-		WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL, i, 0);
315
+		WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL,
316
+				    i * hub->ctx_distance, 0);
287317 
288318 	/* Setup TLB control */
289319 	tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
....@@ -292,7 +322,7 @@
292322 				MC_VM_MX_L1_TLB_CNTL,
293323 				ENABLE_ADVANCED_DRIVER_MODEL,
294324 				0);
295
-	WREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
325
+	WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
296326 
297327 	/* Setup L2 cache */
298328 	WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
....@@ -339,13 +369,13 @@
339369 				CRASH_ON_NO_RETRY_FAULT, 1);
340370 		tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
341371 				CRASH_ON_RETRY_FAULT, 1);
342
-    }
372
+	}
343373 	WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);
344374 }
345375 
346376 void gfxhub_v1_0_init(struct amdgpu_device *adev)
347377 {
348
-	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB];
378
+	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
349379 
350380 	hub->ctx0_ptb_addr_lo32 =
351381 		SOC15_REG_OFFSET(GC, 0,
....@@ -353,6 +383,8 @@
353383 	hub->ctx0_ptb_addr_hi32 =
354384 		SOC15_REG_OFFSET(GC, 0,
355385 				 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
386
+	hub->vm_inv_eng0_sem =
387
+		SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_SEM);
356388 	hub->vm_inv_eng0_req =
357389 		SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_REQ);
358390 	hub->vm_inv_eng0_ack =
....@@ -363,4 +395,21 @@
363395 		SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS);
364396 	hub->vm_l2_pro_fault_cntl =
365397 		SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
398
+
399
+	hub->ctx_distance = mmVM_CONTEXT1_CNTL - mmVM_CONTEXT0_CNTL;
400
+	hub->ctx_addr_distance = mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
401
+		mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
402
+	hub->eng_distance = mmVM_INVALIDATE_ENG1_REQ - mmVM_INVALIDATE_ENG0_REQ;
403
+	hub->eng_addr_distance = mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
404
+		mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
366405 }
406
+
407
+
408
+const struct amdgpu_gfxhub_funcs gfxhub_v1_0_funcs = {
409
+	.get_mc_fb_offset = gfxhub_v1_0_get_mc_fb_offset,
410
+	.setup_vm_pt_regs = gfxhub_v1_0_setup_vm_pt_regs,
411
+	.gart_enable = gfxhub_v1_0_gart_enable,
412
+	.gart_disable = gfxhub_v1_0_gart_disable,
413
+	.set_fault_enable_default = gfxhub_v1_0_set_fault_enable_default,
414
+	.init = gfxhub_v1_0_init,
415
+};