forked from ~ljy/RK356X_SDK_RELEASE

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2023-12-06 08f87f769b595151be1afeff53e144f543faa614 
 kernel/drivers/gpio/gpio-zynq.c
....@@ -1,12 +1,8 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * Xilinx Zynq GPIO device driver
34  *
45  * Copyright (C) 2009 - 2014 Xilinx, Inc.
5
- *
6
- * This program is free software; you can redistribute it and/or modify it under
7
- * the terms of the GNU General Public License as published by the Free Software
8
- * Foundation; either version 2 of the License, or (at your option) any later
9
- * version.
106  */
117 
128 #include <linux/bitops.h>
....@@ -14,6 +10,7 @@
1410 #include <linux/gpio/driver.h>
1511 #include <linux/init.h>
1612 #include <linux/interrupt.h>
13
+#include <linux/spinlock.h>
1714 #include <linux/io.h>
1815 #include <linux/module.h>
1916 #include <linux/platform_device.h>
....@@ -25,6 +22,9 @@
2522 /* Maximum banks */
2623 #define ZYNQ_GPIO_MAX_BANK	4
2724 #define ZYNQMP_GPIO_MAX_BANK	6
25
+#define VERSAL_GPIO_MAX_BANK	4
26
+#define PMC_GPIO_MAX_BANK	5
27
+#define VERSAL_UNUSED_BANKS	2
2828 
2929 #define ZYNQ_GPIO_BANK0_NGPIO	32
3030 #define ZYNQ_GPIO_BANK1_NGPIO	22
....@@ -99,6 +99,7 @@
9999 /* set to differentiate zynq from zynqmp, 0=zynqmp, 1=zynq */
100100 #define ZYNQ_GPIO_QUIRK_IS_ZYNQ	BIT(0)
101101 #define GPIO_QUIRK_DATA_RO_BUG	BIT(1)
102
+#define GPIO_QUIRK_VERSAL	BIT(2)
102103 
103104 struct gpio_regs {
104105 	u32 datamsw[ZYNQMP_GPIO_MAX_BANK];
....@@ -120,6 +121,7 @@
120121  * @irq:	interrupt for the GPIO device
121122  * @p_data:	pointer to platform data
122123  * @context:	context registers
124
+ * @dirlock:	lock used for direction in/out synchronization
123125  */
124126 struct zynq_gpio {
125127 	struct gpio_chip chip;
....@@ -128,6 +130,7 @@
128130 	int irq;
129131 	const struct zynq_platform_data *p_data;
130132 	struct gpio_regs context;
133
+	spinlock_t dirlock; /* lock */
131134 };
132135 
133136 /**
....@@ -200,6 +203,8 @@
200203 					gpio->p_data->bank_min[bank];
201204 			return;
202205 		}
206
+		if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
207
+			bank = bank + VERSAL_UNUSED_BANKS;
203208 	}
204209 
205210 	/* default */
....@@ -301,6 +306,7 @@
301306 {
302307 	u32 reg;
303308 	unsigned int bank_num, bank_pin_num;
309
+	unsigned long flags;
304310 	struct zynq_gpio *gpio = gpiochip_get_data(chip);
305311 
306312 	zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
....@@ -314,9 +320,11 @@
314320 		return -EINVAL;
315321 
316322 	/* clear the bit in direction mode reg to set the pin as input */
323
+	spin_lock_irqsave(&gpio->dirlock, flags);
317324 	reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
318325 	reg &= ~BIT(bank_pin_num);
319326 	writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
327
+	spin_unlock_irqrestore(&gpio->dirlock, flags);
320328 
321329 	return 0;
322330 }
....@@ -338,11 +346,13 @@
338346 {
339347 	u32 reg;
340348 	unsigned int bank_num, bank_pin_num;
349
+	unsigned long flags;
341350 	struct zynq_gpio *gpio = gpiochip_get_data(chip);
342351 
343352 	zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
344353 
345354 	/* set the GPIO pin as output */
355
+	spin_lock_irqsave(&gpio->dirlock, flags);
346356 	reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
347357 	reg |= BIT(bank_pin_num);
348358 	writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
....@@ -351,6 +361,7 @@
351361 	reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
352362 	reg |= BIT(bank_pin_num);
353363 	writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
364
+	spin_unlock_irqrestore(&gpio->dirlock, flags);
354365 
355366 	/* set the state of the pin */
356367 	zynq_gpio_set_value(chip, pin, state);
....@@ -364,7 +375,7 @@
364375  *
365376  * This function returns the direction of the specified GPIO.
366377  *
367
- * Return: 0 for output, 1 for input
378
+ * Return: GPIO_LINE_DIRECTION_OUT or GPIO_LINE_DIRECTION_IN
368379  */
369380 static int zynq_gpio_get_direction(struct gpio_chip *chip, unsigned int pin)
370381 {
....@@ -376,7 +387,10 @@
376387 
377388 	reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
378389 
379
-	return !(reg & BIT(bank_pin_num));
390
+	if (reg & BIT(bank_pin_num))
391
+		return GPIO_LINE_DIRECTION_OUT;
392
+
393
+	return GPIO_LINE_DIRECTION_IN;
380394 }
381395 
382396 /**
....@@ -555,6 +569,26 @@
555569 	return 0;
556570 }
557571 
572
+static int zynq_gpio_irq_reqres(struct irq_data *d)
573
+{
574
+	struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
575
+	int ret;
576
+
577
+	ret = pm_runtime_resume_and_get(chip->parent);
578
+	if (ret < 0)
579
+		return ret;
580
+
581
+	return gpiochip_reqres_irq(chip, d->hwirq);
582
+}
583
+
584
+static void zynq_gpio_irq_relres(struct irq_data *d)
585
+{
586
+	struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
587
+
588
+	gpiochip_relres_irq(chip, d->hwirq);
589
+	pm_runtime_put(chip->parent);
590
+}
591
+
558592 /* irq chip descriptor */
559593 static struct irq_chip zynq_gpio_level_irqchip = {
560594 	.name		= DRIVER_NAME,
....@@ -564,6 +598,8 @@
564598 	.irq_unmask	= zynq_gpio_irq_unmask,
565599 	.irq_set_type	= zynq_gpio_set_irq_type,
566600 	.irq_set_wake	= zynq_gpio_set_wake,
601
+	.irq_request_resources = zynq_gpio_irq_reqres,
602
+	.irq_release_resources = zynq_gpio_irq_relres,
567603 	.flags		= IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED |
568604 			  IRQCHIP_MASK_ON_SUSPEND,
569605 };
....@@ -576,6 +612,8 @@
576612 	.irq_unmask	= zynq_gpio_irq_unmask,
577613 	.irq_set_type	= zynq_gpio_set_irq_type,
578614 	.irq_set_wake	= zynq_gpio_set_wake,
615
+	.irq_request_resources = zynq_gpio_irq_reqres,
616
+	.irq_release_resources = zynq_gpio_irq_relres,
579617 	.flags		= IRQCHIP_MASK_ON_SUSPEND,
580618 };
581619 
....@@ -624,6 +662,8 @@
624662 		int_enb = readl_relaxed(gpio->base_addr +
625663 					ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
626664 		zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb);
665
+		if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
666
+			bank_num = bank_num + VERSAL_UNUSED_BANKS;
627667 	}
628668 
629669 	chained_irq_exit(irqchip, desc);
....@@ -653,6 +693,8 @@
653693 		gpio->context.int_any[bank_num] =
654694 				readl_relaxed(gpio->base_addr +
655695 				ZYNQ_GPIO_INTANY_OFFSET(bank_num));
696
+		if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
697
+			bank_num = bank_num + VERSAL_UNUSED_BANKS;
656698 	}
657699 }
658700 
....@@ -684,6 +726,8 @@
684726 		writel_relaxed(~(gpio->context.int_en[bank_num]),
685727 			       gpio->base_addr +
686728 			       ZYNQ_GPIO_INTEN_OFFSET(bank_num));
729
+		if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
730
+			bank_num = bank_num + VERSAL_UNUSED_BANKS;
687731 	}
688732 }
689733 
....@@ -691,6 +735,14 @@
691735 {
692736 	struct zynq_gpio *gpio = dev_get_drvdata(dev);
693737 	struct irq_data *data = irq_get_irq_data(gpio->irq);
738
+
739
+	if (!data) {
740
+		dev_err(dev, "irq_get_irq_data() failed\n");
741
+		return -EINVAL;
742
+	}
743
+
744
+	if (!device_may_wakeup(dev))
745
+		disable_irq(gpio->irq);
694746 
695747 	if (!irqd_is_wakeup_set(data)) {
696748 		zynq_gpio_save_context(gpio);
....@@ -706,6 +758,14 @@
706758 	struct irq_data *data = irq_get_irq_data(gpio->irq);
707759 	int ret;
708760 
761
+	if (!data) {
762
+		dev_err(dev, "irq_get_irq_data() failed\n");
763
+		return -EINVAL;
764
+	}
765
+
766
+	if (!device_may_wakeup(dev))
767
+		enable_irq(gpio->irq);
768
+
709769 	if (!irqd_is_wakeup_set(data)) {
710770 		ret = pm_runtime_force_resume(dev);
711771 		zynq_gpio_restore_context(gpio);
....@@ -717,8 +777,7 @@
717777 
718778 static int __maybe_unused zynq_gpio_runtime_suspend(struct device *dev)
719779 {
720
-	struct platform_device *pdev = to_platform_device(dev);
721
-	struct zynq_gpio *gpio = platform_get_drvdata(pdev);
780
+	struct zynq_gpio *gpio = dev_get_drvdata(dev);
722781 
723782 	clk_disable_unprepare(gpio->clk);
724783 
....@@ -727,8 +786,7 @@
727786 
728787 static int __maybe_unused zynq_gpio_runtime_resume(struct device *dev)
729788 {
730
-	struct platform_device *pdev = to_platform_device(dev);
731
-	struct zynq_gpio *gpio = platform_get_drvdata(pdev);
789
+	struct zynq_gpio *gpio = dev_get_drvdata(dev);
732790 
733791 	return clk_prepare_enable(gpio->clk);
734792 }
....@@ -755,6 +813,31 @@
755813 	SET_SYSTEM_SLEEP_PM_OPS(zynq_gpio_suspend, zynq_gpio_resume)
756814 	SET_RUNTIME_PM_OPS(zynq_gpio_runtime_suspend,
757815 			   zynq_gpio_runtime_resume, NULL)
816
+};
817
+
818
+static const struct zynq_platform_data versal_gpio_def = {
819
+	.label = "versal_gpio",
820
+	.quirks = GPIO_QUIRK_VERSAL,
821
+	.ngpio = 58,
822
+	.max_bank = VERSAL_GPIO_MAX_BANK,
823
+	.bank_min[0] = 0,
824
+	.bank_max[0] = 25, /* 0 to 25 are connected to MIOs (26 pins) */
825
+	.bank_min[3] = 26,
826
+	.bank_max[3] = 57, /* Bank 3 is connected to FMIOs (32 pins) */
827
+};
828
+
829
+static const struct zynq_platform_data pmc_gpio_def = {
830
+	.label = "pmc_gpio",
831
+	.ngpio = 116,
832
+	.max_bank = PMC_GPIO_MAX_BANK,
833
+	.bank_min[0] = 0,
834
+	.bank_max[0] = 25, /* 0 to 25 are connected to MIOs (26 pins) */
835
+	.bank_min[1] = 26,
836
+	.bank_max[1] = 51, /* Bank 1 are connected to MIOs (26 pins) */
837
+	.bank_min[3] = 52,
838
+	.bank_max[3] = 83, /* Bank 3 is connected to EMIOs (32 pins) */
839
+	.bank_min[4] = 84,
840
+	.bank_max[4] = 115, /* Bank 4 is connected to EMIOs (32 pins) */
758841 };
759842 
760843 static const struct zynq_platform_data zynqmp_gpio_def = {
....@@ -794,6 +877,8 @@
794877 static const struct of_device_id zynq_gpio_of_match[] = {
795878 	{ .compatible = "xlnx,zynq-gpio-1.0", .data = &zynq_gpio_def },
796879 	{ .compatible = "xlnx,zynqmp-gpio-1.0", .data = &zynqmp_gpio_def },
880
+	{ .compatible = "xlnx,versal-gpio-1.0", .data = &versal_gpio_def },
881
+	{ .compatible = "xlnx,pmc-gpio-1.0", .data = &pmc_gpio_def },
797882 	{ /* end of table */ }
798883 };
799884 MODULE_DEVICE_TABLE(of, zynq_gpio_of_match);
....@@ -814,7 +899,7 @@
814899 	int ret, bank_num;
815900 	struct zynq_gpio *gpio;
816901 	struct gpio_chip *chip;
817
-	struct resource *res;
902
+	struct gpio_irq_chip *girq;
818903 	const struct of_device_id *match;
819904 
820905 	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
....@@ -829,16 +914,13 @@
829914 	gpio->p_data = match->data;
830915 	platform_set_drvdata(pdev, gpio);
831916 
832
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
833
-	gpio->base_addr = devm_ioremap_resource(&pdev->dev, res);
917
+	gpio->base_addr = devm_platform_ioremap_resource(pdev, 0);
834918 	if (IS_ERR(gpio->base_addr))
835919 		return PTR_ERR(gpio->base_addr);
836920 
837921 	gpio->irq = platform_get_irq(pdev, 0);
838
-	if (gpio->irq < 0) {
839
-		dev_err(&pdev->dev, "invalid IRQ\n");
922
+	if (gpio->irq < 0)
840923 		return gpio->irq;
841
-	}
842924 
843925 	/* configure the gpio chip */
844926 	chip = &gpio->chip;
....@@ -857,21 +939,46 @@
857939 
858940 	/* Retrieve GPIO clock */
859941 	gpio->clk = devm_clk_get(&pdev->dev, NULL);
860
-	if (IS_ERR(gpio->clk)) {
861
-		dev_err(&pdev->dev, "input clock not found.\n");
862
-		return PTR_ERR(gpio->clk);
863
-	}
942
+	if (IS_ERR(gpio->clk))
943
+		return dev_err_probe(&pdev->dev, PTR_ERR(gpio->clk), "input clock not found.\n");
944
+
864945 	ret = clk_prepare_enable(gpio->clk);
865946 	if (ret) {
866947 		dev_err(&pdev->dev, "Unable to enable clock.\n");
867948 		return ret;
868949 	}
869950 
951
+	spin_lock_init(&gpio->dirlock);
952
+
870953 	pm_runtime_set_active(&pdev->dev);
871954 	pm_runtime_enable(&pdev->dev);
872
-	ret = pm_runtime_get_sync(&pdev->dev);
955
+	ret = pm_runtime_resume_and_get(&pdev->dev);
873956 	if (ret < 0)
874957 		goto err_pm_dis;
958
+
959
+	/* disable interrupts for all banks */
960
+	for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
961
+		writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
962
+			       ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
963
+		if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
964
+			bank_num = bank_num + VERSAL_UNUSED_BANKS;
965
+	}
966
+
967
+	/* Set up the GPIO irqchip */
968
+	girq = &chip->irq;
969
+	girq->chip = &zynq_gpio_edge_irqchip;
970
+	girq->parent_handler = zynq_gpio_irqhandler;
971
+	girq->num_parents = 1;
972
+	girq->parents = devm_kcalloc(&pdev->dev, 1,
973
+				     sizeof(*girq->parents),
974
+				     GFP_KERNEL);
975
+	if (!girq->parents) {
976
+		ret = -ENOMEM;
977
+		goto err_pm_put;
978
+	}
979
+	girq->parents[0] = gpio->irq;
980
+	girq->default_type = IRQ_TYPE_NONE;
981
+	girq->handler = handle_level_irq;
875982 
876983 	/* report a bug if gpio chip registration fails */
877984 	ret = gpiochip_add_data(chip, gpio);
....@@ -880,27 +987,12 @@
880987 		goto err_pm_put;
881988 	}
882989 
883
-	/* disable interrupts for all banks */
884
-	for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++)
885
-		writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
886
-			       ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
887
-
888
-	ret = gpiochip_irqchip_add(chip, &zynq_gpio_edge_irqchip, 0,
889
-				   handle_level_irq, IRQ_TYPE_NONE);
890
-	if (ret) {
891
-		dev_err(&pdev->dev, "Failed to add irq chip\n");
892
-		goto err_rm_gpiochip;
893
-	}
894
-
895
-	gpiochip_set_chained_irqchip(chip, &zynq_gpio_edge_irqchip, gpio->irq,
896
-				     zynq_gpio_irqhandler);
897
-
990
+	irq_set_status_flags(gpio->irq, IRQ_DISABLE_UNLAZY);
991
+	device_init_wakeup(&pdev->dev, 1);
898992 	pm_runtime_put(&pdev->dev);
899993 
900994 	return 0;
901995 
902
-err_rm_gpiochip:
903
-	gpiochip_remove(chip);
904996 err_pm_put:
905997 	pm_runtime_put(&pdev->dev);
906998 err_pm_dis: