add dts config

hc

2023-12-06 08f87f769b595151be1afeff53e144f543faa614

 kernel/drivers/gpio/gpio-davinci.c
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@@ -1,14 +1,11 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later
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 /*
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  * TI DaVinci GPIO Support
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  *
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  * Copyright (c) 2006-2007 David Brownell
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  * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License as published by
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- * the Free Software Foundation; either version 2 of the License, or
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- * (at your option) any later version.
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  */
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+
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 #include <linux/gpio/driver.h>
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 #include <linux/errno.h>
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 #include <linux/kernel.h>
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@@ -24,6 +21,12 @@
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 #include <linux/platform_device.h>
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 #include <linux/platform_data/gpio-davinci.h>
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 #include <linux/irqchip/chained_irq.h>
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+#include <linux/spinlock.h>
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+
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+#include <asm-generic/gpio.h>
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+
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+#define MAX_REGS_BANKS 5
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+#define MAX_INT_PER_BANK 32
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30
 
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 struct davinci_gpio_regs {
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 	u32	dir;
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@@ -41,10 +44,30 @@
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 typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq);
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45
 
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 #define BINTEN	0x8 /* GPIO Interrupt Per-Bank Enable Register */
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-#define MAX_LABEL_SIZE 20
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47
 
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 static void __iomem *gpio_base;
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 static unsigned int offset_array[5] = {0x10, 0x38, 0x60, 0x88, 0xb0};
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+
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+struct davinci_gpio_irq_data {
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+	void __iomem			*regs;
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+	struct davinci_gpio_controller	*chip;
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+	int				bank_num;
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+};
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+
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+struct davinci_gpio_controller {
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+	struct gpio_chip	chip;
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+	struct irq_domain	*irq_domain;
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+	/* Serialize access to GPIO registers */
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+	spinlock_t		lock;
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+	void __iomem		*regs[MAX_REGS_BANKS];
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+	int			gpio_unbanked;
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+	int			irqs[MAX_INT_PER_BANK];
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+};
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+
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+static inline u32 __gpio_mask(unsigned gpio)
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+{
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+	return 1 << (gpio % 32);
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+}
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71
 
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 static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d)
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 {
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@@ -166,14 +189,11 @@
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189
 
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 static int davinci_gpio_probe(struct platform_device *pdev)
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 {
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-	static int ctrl_num, bank_base;
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-	int gpio, bank, i, ret = 0;
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+	int bank, i, ret = 0;
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 	unsigned int ngpio, nbank, nirq;
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 	struct davinci_gpio_controller *chips;
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 	struct davinci_gpio_platform_data *pdata;
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 	struct device *dev = &pdev->dev;
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-	struct resource *res;
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-	char label[MAX_LABEL_SIZE];
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197
 
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 	pdata = davinci_gpio_get_pdata(pdev);
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 	if (!pdata) {
..
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@@ -207,32 +227,21 @@
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 	else
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 		nirq = DIV_ROUND_UP(ngpio, 16);
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229
 
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-	nbank = DIV_ROUND_UP(ngpio, 32);
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-	chips = devm_kcalloc(dev,
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-			     nbank, sizeof(struct davinci_gpio_controller),
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-			     GFP_KERNEL);
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+	chips = devm_kzalloc(dev, sizeof(*chips), GFP_KERNEL);
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 	if (!chips)
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 		return -ENOMEM;
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233
 
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-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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-	gpio_base = devm_ioremap_resource(dev, res);
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+	gpio_base = devm_platform_ioremap_resource(pdev, 0);
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 	if (IS_ERR(gpio_base))
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 		return PTR_ERR(gpio_base);
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 	for (i = 0; i < nirq; i++) {
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 		chips->irqs[i] = platform_get_irq(pdev, i);
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-		if (chips->irqs[i] < 0) {
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-			if (chips->irqs[i] != -EPROBE_DEFER)
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-				dev_info(dev, "IRQ not populated, err = %d\n",
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-					 chips->irqs[i]);
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-			return chips->irqs[i];
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-		}
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+		if (chips->irqs[i] < 0)
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+			return dev_err_probe(dev, chips->irqs[i], "IRQ not populated\n");
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 	}
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-	snprintf(label, MAX_LABEL_SIZE, "davinci_gpio.%d", ctrl_num++);
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-	chips->chip.label = devm_kstrdup(dev, label, GFP_KERNEL);
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-		if (!chips->chip.label)
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-			return -ENOMEM;
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+	chips->chip.label = dev_name(dev);
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 	chips->chip.direction_input = davinci_direction_in;
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 	chips->chip.get = davinci_gpio_get;
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@@ -240,41 +249,31 @@
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 	chips->chip.set = davinci_gpio_set;
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 	chips->chip.ngpio = ngpio;
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-	chips->chip.base = bank_base;
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+	chips->chip.base = pdata->no_auto_base ? pdata->base : -1;
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 #ifdef CONFIG_OF_GPIO
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 	chips->chip.of_gpio_n_cells = 2;
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 	chips->chip.parent = dev;
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 	chips->chip.of_node = dev->of_node;
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-
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-	if (of_property_read_bool(dev->of_node, "gpio-ranges")) {
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-		chips->chip.request = gpiochip_generic_request;
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-		chips->chip.free = gpiochip_generic_free;
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-	}
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+	chips->chip.request = gpiochip_generic_request;
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+	chips->chip.free = gpiochip_generic_free;
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 #endif
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 	spin_lock_init(&chips->lock);
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-	bank_base += ngpio;
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-	for (gpio = 0, bank = 0; gpio < ngpio; gpio += 32, bank++)
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+	nbank = DIV_ROUND_UP(ngpio, 32);
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+	for (bank = 0; bank < nbank; bank++)
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 		chips->regs[bank] = gpio_base + offset_array[bank];
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 	ret = devm_gpiochip_add_data(dev, &chips->chip, chips);
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 	if (ret)
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-		goto err;
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+		return ret;
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 	platform_set_drvdata(pdev, chips);
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 	ret = davinci_gpio_irq_setup(pdev);
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 	if (ret)
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-		goto err;
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+		return ret;
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 	return 0;
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-
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-err:
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-	/* Revert the static variable increments */
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-	ctrl_num--;
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-	bank_base -= ngpio;
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-
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-	return ret;
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 }
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 /*--------------------------------------------------------------------------*/
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@@ -292,7 +291,7 @@
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 static void gpio_irq_disable(struct irq_data *d)
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 {
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 	struct davinci_gpio_regs __iomem *g = irq2regs(d);
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-	u32 mask = (u32) irq_data_get_irq_handler_data(d);
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+	uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d);
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 	writel_relaxed(mask, &g->clr_falling);
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 	writel_relaxed(mask, &g->clr_rising);
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@@ -301,7 +300,7 @@
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 static void gpio_irq_enable(struct irq_data *d)
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 {
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 	struct davinci_gpio_regs __iomem *g = irq2regs(d);
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-	u32 mask = (u32) irq_data_get_irq_handler_data(d);
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+	uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d);
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 	unsigned status = irqd_get_trigger_type(d);
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 	status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
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@@ -442,7 +441,7 @@
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 				"davinci_gpio");
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 	irq_set_irq_type(irq, IRQ_TYPE_NONE);
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 	irq_set_chip_data(irq, (__force void *)g);
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-	irq_set_handler_data(irq, (void *)__gpio_mask(hw));
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+	irq_set_handler_data(irq, (void *)(uintptr_t)__gpio_mask(hw));
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 	return 0;
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 }
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@@ -627,6 +626,7 @@
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 static const struct of_device_id davinci_gpio_ids[] = {
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 	{ .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
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+	{ .compatible = "ti,am654-gpio", keystone_gpio_get_irq_chip},
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 	{ .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
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 	{ /* sentinel */ },
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 };