add dts config

hc

2023-12-06 08f87f769b595151be1afeff53e144f543faa614

 kernel/drivers/crypto/chelsio/chcr_core.h
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@@ -37,17 +37,19 @@
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 #define __CHCR_CORE_H__
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 #include <crypto/algapi.h>
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+#include <net/tls.h>
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 #include "t4_hw.h"
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 #include "cxgb4.h"
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 #include "t4_msg.h"
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 #include "cxgb4_uld.h"
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 #define DRV_MODULE_NAME "chcr"
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-#define DRV_VERSION "1.0.0.0"
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+#define DRV_VERSION "1.0.0.0-ko"
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+#define DRV_DESC "Chelsio T6 Crypto Co-processor Driver"
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 #define MAX_PENDING_REQ_TO_HW 20
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 #define CHCR_TEST_RESPONSE_TIMEOUT 1000
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-
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+#define WQ_DETACH_TM	(msecs_to_jiffies(50))
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 #define PAD_ERROR_BIT		1
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 #define CHK_PAD_ERR_BIT(x)	(((x) >> PAD_ERROR_BIT) & 1)
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@@ -61,66 +63,29 @@
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 #define HASH_WR_MIN_LEN (sizeof(struct chcr_wr) + \
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 			DUMMY_BYTES + \
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 		    sizeof(struct ulptx_sgl))
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-
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-#define padap(dev) pci_get_drvdata(dev->u_ctx->lldi.pdev)
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-
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 struct uld_ctx;
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 struct _key_ctx {
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 	__be32 ctx_hdr;
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 	u8 salt[MAX_SALT];
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 	__be64 iv_to_auth;
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-	unsigned char key[0];
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+	unsigned char key[];
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 };
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-#define KEYCTX_TX_WR_IV_S  55
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-#define KEYCTX_TX_WR_IV_M  0x1ffULL
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-#define KEYCTX_TX_WR_IV_V(x) ((x) << KEYCTX_TX_WR_IV_S)
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-#define KEYCTX_TX_WR_IV_G(x) \
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-	(((x) >> KEYCTX_TX_WR_IV_S) & KEYCTX_TX_WR_IV_M)
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+#define WQ_RETRY	5
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+struct chcr_driver_data {
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+	struct list_head act_dev;
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+	struct list_head inact_dev;
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+	atomic_t dev_count;
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+	struct mutex drv_mutex;
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+	struct uld_ctx *last_dev;
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+};
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-#define KEYCTX_TX_WR_AAD_S 47
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-#define KEYCTX_TX_WR_AAD_M 0xffULL
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-#define KEYCTX_TX_WR_AAD_V(x) ((x) << KEYCTX_TX_WR_AAD_S)
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-#define KEYCTX_TX_WR_AAD_G(x) (((x) >> KEYCTX_TX_WR_AAD_S) & \
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-				KEYCTX_TX_WR_AAD_M)
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-
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-#define KEYCTX_TX_WR_AADST_S 39
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-#define KEYCTX_TX_WR_AADST_M 0xffULL
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-#define KEYCTX_TX_WR_AADST_V(x) ((x) << KEYCTX_TX_WR_AADST_S)
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-#define KEYCTX_TX_WR_AADST_G(x) \
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-	(((x) >> KEYCTX_TX_WR_AADST_S) & KEYCTX_TX_WR_AADST_M)
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-
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-#define KEYCTX_TX_WR_CIPHER_S 30
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-#define KEYCTX_TX_WR_CIPHER_M 0x1ffULL
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-#define KEYCTX_TX_WR_CIPHER_V(x) ((x) << KEYCTX_TX_WR_CIPHER_S)
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-#define KEYCTX_TX_WR_CIPHER_G(x) \
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-	(((x) >> KEYCTX_TX_WR_CIPHER_S) & KEYCTX_TX_WR_CIPHER_M)
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-
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-#define KEYCTX_TX_WR_CIPHERST_S 23
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-#define KEYCTX_TX_WR_CIPHERST_M 0x7f
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-#define KEYCTX_TX_WR_CIPHERST_V(x) ((x) << KEYCTX_TX_WR_CIPHERST_S)
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-#define KEYCTX_TX_WR_CIPHERST_G(x) \
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-	(((x) >> KEYCTX_TX_WR_CIPHERST_S) & KEYCTX_TX_WR_CIPHERST_M)
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-
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-#define KEYCTX_TX_WR_AUTH_S 14
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-#define KEYCTX_TX_WR_AUTH_M 0x1ff
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-#define KEYCTX_TX_WR_AUTH_V(x) ((x) << KEYCTX_TX_WR_AUTH_S)
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-#define KEYCTX_TX_WR_AUTH_G(x) \
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-	(((x) >> KEYCTX_TX_WR_AUTH_S) & KEYCTX_TX_WR_AUTH_M)
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-
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-#define KEYCTX_TX_WR_AUTHST_S 7
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-#define KEYCTX_TX_WR_AUTHST_M 0x7f
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-#define KEYCTX_TX_WR_AUTHST_V(x) ((x) << KEYCTX_TX_WR_AUTHST_S)
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-#define KEYCTX_TX_WR_AUTHST_G(x) \
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-	(((x) >> KEYCTX_TX_WR_AUTHST_S) & KEYCTX_TX_WR_AUTHST_M)
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-
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-#define KEYCTX_TX_WR_AUTHIN_S 0
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-#define KEYCTX_TX_WR_AUTHIN_M 0x7f
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-#define KEYCTX_TX_WR_AUTHIN_V(x) ((x) << KEYCTX_TX_WR_AUTHIN_S)
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-#define KEYCTX_TX_WR_AUTHIN_G(x) \
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-	(((x) >> KEYCTX_TX_WR_AUTHIN_S) & KEYCTX_TX_WR_AUTHIN_M)
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-
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+enum chcr_state {
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+	CHCR_INIT = 0,
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+	CHCR_ATTACH,
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+	CHCR_DETACH,
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+};
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 struct chcr_wr {
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 	struct fw_crypto_lookaside_wr wreq;
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 	struct ulp_txpkt ulptx;
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@@ -131,42 +96,17 @@
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 struct chcr_dev {
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 	spinlock_t lock_chcr_dev;
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-	struct uld_ctx *u_ctx;
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-	unsigned char tx_channel_id;
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-	unsigned char rx_channel_id;
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+	enum chcr_state state;
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+	atomic_t inflight;
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+	int wqretry;
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+	struct delayed_work detach_work;
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+	struct completion detach_comp;
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 };
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 struct uld_ctx {
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 	struct list_head entry;
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 	struct cxgb4_lld_info lldi;
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-	struct chcr_dev *dev;
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-};
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-
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-struct sge_opaque_hdr {
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-	void *dev;
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-	dma_addr_t addr[MAX_SKB_FRAGS + 1];
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-};
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-
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-struct chcr_ipsec_req {
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-	struct ulp_txpkt ulptx;
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-	struct ulptx_idata sc_imm;
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-	struct cpl_tx_sec_pdu sec_cpl;
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-	struct _key_ctx key_ctx;
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-};
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-
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-struct chcr_ipsec_wr {
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-	struct fw_ulptx_wr wreq;
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-	struct chcr_ipsec_req req;
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-};
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-
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-struct ipsec_sa_entry {
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-	int hmac_ctrl;
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-	unsigned int enckey_len;
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-	unsigned int kctx_len;
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-	unsigned int authsize;
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-	__be32 key_ctx_hdr;
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-	char salt[MAX_SALT];
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-	char key[2 * AES_MAX_KEY_SIZE];
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+	struct chcr_dev dev;
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 };
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 /*
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@@ -181,6 +121,13 @@
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 	return (3 * n) / 2 + (n & 1) + 2;
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 }
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+static inline void *padap(struct chcr_dev *dev)
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+{
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+	struct uld_ctx *u_ctx = container_of(dev, struct uld_ctx, dev);
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+
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+	return pci_get_drvdata(u_ctx->lldi.pdev);
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+}
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+
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 struct uld_ctx *assign_chcr_device(void);
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 int chcr_send_wr(struct sk_buff *skb);
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 int start_crypto(void);
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@@ -190,6 +137,4 @@
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 int chcr_uld_tx_handler(struct sk_buff *skb, struct net_device *dev);
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 int chcr_handle_resp(struct crypto_async_request *req, unsigned char *input,
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 		     int err);
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-int chcr_ipsec_xmit(struct sk_buff *skb, struct net_device *dev);
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-void chcr_add_xfrmops(const struct cxgb4_lld_info *lld);
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 #endif /* __CHCR_CORE_H__ */