~hc/RK356X_SDK_RELEASE.git

..	..	@@ -3,27 +3,30 @@
3	3	#include "uncore.h"
4	4
5	5	/* Uncore IMC PCI IDs */
6		-#define PCI_DEVICE_ID_INTEL_SNB_IMC 0x0100
7		-#define PCI_DEVICE_ID_INTEL_IVB_IMC 0x0154
8		-#define PCI_DEVICE_ID_INTEL_IVB_E3_IMC 0x0150
9		-#define PCI_DEVICE_ID_INTEL_HSW_IMC 0x0c00
10		-#define PCI_DEVICE_ID_INTEL_HSW_U_IMC 0x0a04
11		-#define PCI_DEVICE_ID_INTEL_BDW_IMC 0x1604
12		-#define PCI_DEVICE_ID_INTEL_SKL_U_IMC 0x1904
13		-#define PCI_DEVICE_ID_INTEL_SKL_Y_IMC 0x190c
14		-#define PCI_DEVICE_ID_INTEL_SKL_HD_IMC 0x1900
15		-#define PCI_DEVICE_ID_INTEL_SKL_HQ_IMC 0x1910
16		-#define PCI_DEVICE_ID_INTEL_SKL_SD_IMC 0x190f
17		-#define PCI_DEVICE_ID_INTEL_SKL_SQ_IMC 0x191f
18		-#define PCI_DEVICE_ID_INTEL_KBL_Y_IMC 0x590c
19		-#define PCI_DEVICE_ID_INTEL_KBL_U_IMC 0x5904
20		-#define PCI_DEVICE_ID_INTEL_KBL_UQ_IMC 0x5914
21		-#define PCI_DEVICE_ID_INTEL_KBL_SD_IMC 0x590f
22		-#define PCI_DEVICE_ID_INTEL_KBL_SQ_IMC 0x591f
23		-#define PCI_DEVICE_ID_INTEL_CFL_2U_IMC 0x3ecc
24		-#define PCI_DEVICE_ID_INTEL_CFL_4U_IMC 0x3ed0
25		-#define PCI_DEVICE_ID_INTEL_CFL_4H_IMC 0x3e10
26		-#define PCI_DEVICE_ID_INTEL_CFL_6H_IMC 0x3ec4
	6	+#define PCI_DEVICE_ID_INTEL_SNB_IMC 0x0100
	7	+#define PCI_DEVICE_ID_INTEL_IVB_IMC 0x0154
	8	+#define PCI_DEVICE_ID_INTEL_IVB_E3_IMC 0x0150
	9	+#define PCI_DEVICE_ID_INTEL_HSW_IMC 0x0c00
	10	+#define PCI_DEVICE_ID_INTEL_HSW_U_IMC 0x0a04
	11	+#define PCI_DEVICE_ID_INTEL_BDW_IMC 0x1604
	12	+#define PCI_DEVICE_ID_INTEL_SKL_U_IMC 0x1904
	13	+#define PCI_DEVICE_ID_INTEL_SKL_Y_IMC 0x190c
	14	+#define PCI_DEVICE_ID_INTEL_SKL_HD_IMC 0x1900
	15	+#define PCI_DEVICE_ID_INTEL_SKL_HQ_IMC 0x1910
	16	+#define PCI_DEVICE_ID_INTEL_SKL_SD_IMC 0x190f
	17	+#define PCI_DEVICE_ID_INTEL_SKL_SQ_IMC 0x191f
	18	+#define PCI_DEVICE_ID_INTEL_SKL_E3_IMC 0x1918
	19	+#define PCI_DEVICE_ID_INTEL_KBL_Y_IMC 0x590c
	20	+#define PCI_DEVICE_ID_INTEL_KBL_U_IMC 0x5904
	21	+#define PCI_DEVICE_ID_INTEL_KBL_UQ_IMC 0x5914
	22	+#define PCI_DEVICE_ID_INTEL_KBL_SD_IMC 0x590f
	23	+#define PCI_DEVICE_ID_INTEL_KBL_SQ_IMC 0x591f
	24	+#define PCI_DEVICE_ID_INTEL_KBL_HQ_IMC 0x5910
	25	+#define PCI_DEVICE_ID_INTEL_KBL_WQ_IMC 0x5918
	26	+#define PCI_DEVICE_ID_INTEL_CFL_2U_IMC 0x3ecc
	27	+#define PCI_DEVICE_ID_INTEL_CFL_4U_IMC 0x3ed0
	28	+#define PCI_DEVICE_ID_INTEL_CFL_4H_IMC 0x3e10
	29	+#define PCI_DEVICE_ID_INTEL_CFL_6H_IMC 0x3ec4
27	30	#define PCI_DEVICE_ID_INTEL_CFL_2S_D_IMC 0x3e0f
28	31	#define PCI_DEVICE_ID_INTEL_CFL_4S_D_IMC 0x3e1f
29	32	#define PCI_DEVICE_ID_INTEL_CFL_6S_D_IMC 0x3ec2
..	..	@@ -34,6 +37,30 @@
34	37	#define PCI_DEVICE_ID_INTEL_CFL_4S_S_IMC 0x3e33
35	38	#define PCI_DEVICE_ID_INTEL_CFL_6S_S_IMC 0x3eca
36	39	#define PCI_DEVICE_ID_INTEL_CFL_8S_S_IMC 0x3e32
	40	+#define PCI_DEVICE_ID_INTEL_AML_YD_IMC 0x590c
	41	+#define PCI_DEVICE_ID_INTEL_AML_YQ_IMC 0x590d
	42	+#define PCI_DEVICE_ID_INTEL_WHL_UQ_IMC 0x3ed0
	43	+#define PCI_DEVICE_ID_INTEL_WHL_4_UQ_IMC 0x3e34
	44	+#define PCI_DEVICE_ID_INTEL_WHL_UD_IMC 0x3e35
	45	+#define PCI_DEVICE_ID_INTEL_CML_H1_IMC 0x9b44
	46	+#define PCI_DEVICE_ID_INTEL_CML_H2_IMC 0x9b54
	47	+#define PCI_DEVICE_ID_INTEL_CML_H3_IMC 0x9b64
	48	+#define PCI_DEVICE_ID_INTEL_CML_U1_IMC 0x9b51
	49	+#define PCI_DEVICE_ID_INTEL_CML_U2_IMC 0x9b61
	50	+#define PCI_DEVICE_ID_INTEL_CML_U3_IMC 0x9b71
	51	+#define PCI_DEVICE_ID_INTEL_CML_S1_IMC 0x9b33
	52	+#define PCI_DEVICE_ID_INTEL_CML_S2_IMC 0x9b43
	53	+#define PCI_DEVICE_ID_INTEL_CML_S3_IMC 0x9b53
	54	+#define PCI_DEVICE_ID_INTEL_CML_S4_IMC 0x9b63
	55	+#define PCI_DEVICE_ID_INTEL_CML_S5_IMC 0x9b73
	56	+#define PCI_DEVICE_ID_INTEL_ICL_U_IMC 0x8a02
	57	+#define PCI_DEVICE_ID_INTEL_ICL_U2_IMC 0x8a12
	58	+#define PCI_DEVICE_ID_INTEL_TGL_U1_IMC 0x9a02
	59	+#define PCI_DEVICE_ID_INTEL_TGL_U2_IMC 0x9a04
	60	+#define PCI_DEVICE_ID_INTEL_TGL_U3_IMC 0x9a12
	61	+#define PCI_DEVICE_ID_INTEL_TGL_U4_IMC 0x9a14
	62	+#define PCI_DEVICE_ID_INTEL_TGL_H_IMC 0x9a36
	63	+
37	64
38	65	/* SNB event control */
39	66	#define SNB_UNC_CTL_EV_SEL_MASK 0x000000ff
..	..	@@ -92,6 +119,16 @@
92	119	/* SKL uncore global control */
93	120	#define SKL_UNC_PERF_GLOBAL_CTL 0xe01
94	121	#define SKL_UNC_GLOBAL_CTL_CORE_ALL ((1 << 5) - 1)
	122	+
	123	+/* ICL Cbo register */
	124	+#define ICL_UNC_CBO_CONFIG 0x396
	125	+#define ICL_UNC_NUM_CBO_MASK 0xf
	126	+#define ICL_UNC_CBO_0_PER_CTR0 0x702
	127	+#define ICL_UNC_CBO_MSR_OFFSET 0x8
	128	+
	129	+/* ICL ARB register */
	130	+#define ICL_UNC_ARB_PER_CTR 0x3b1
	131	+#define ICL_UNC_ARB_PERFEVTSEL 0x3b3
95	132
96	133	DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7");
97	134	DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15");
..	..	@@ -221,6 +258,10 @@
221	258	wrmsrl(SKL_UNC_PERF_GLOBAL_CTL,
222	259	SNB_UNC_GLOBAL_CTL_EN \| SKL_UNC_GLOBAL_CTL_CORE_ALL);
223	260	}
	261	+
	262	+ /* The 8th CBOX has different MSR space */
	263	+ if (box->pmu->pmu_idx == 7)
	264	+ __set_bit(UNCORE_BOX_FLAG_CFL8_CBOX_MSR_OFFS, &box->flags);
224	265	}
225	266
226	267	static void skl_uncore_msr_enable_box(struct intel_uncore_box *box)
..	..	@@ -247,7 +288,7 @@
247	288	static struct intel_uncore_type skl_uncore_cbox = {
248	289	.name = "cbox",
249	290	.num_counters = 4,
250		- .num_boxes = 5,
	291	+ .num_boxes = 8,
251	292	.perf_ctr_bits = 44,
252	293	.fixed_ctr_bits = 48,
253	294	.perf_ctr = SNB_UNC_CBO_0_PER_CTR0,
..	..	@@ -276,6 +317,103 @@
276	317	snb_uncore_arb.ops = &skl_uncore_msr_ops;
277	318	}
278	319
	320	+static struct intel_uncore_ops icl_uncore_msr_ops = {
	321	+ .disable_event = snb_uncore_msr_disable_event,
	322	+ .enable_event = snb_uncore_msr_enable_event,
	323	+ .read_counter = uncore_msr_read_counter,
	324	+};
	325	+
	326	+static struct intel_uncore_type icl_uncore_cbox = {
	327	+ .name = "cbox",
	328	+ .num_counters = 2,
	329	+ .perf_ctr_bits = 44,
	330	+ .perf_ctr = ICL_UNC_CBO_0_PER_CTR0,
	331	+ .event_ctl = SNB_UNC_CBO_0_PERFEVTSEL0,
	332	+ .event_mask = SNB_UNC_RAW_EVENT_MASK,
	333	+ .msr_offset = ICL_UNC_CBO_MSR_OFFSET,
	334	+ .ops = &icl_uncore_msr_ops,
	335	+ .format_group = &snb_uncore_format_group,
	336	+};
	337	+
	338	+static struct uncore_event_desc icl_uncore_events[] = {
	339	+ INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff"),
	340	+ { /* end: all zeroes */ },
	341	+};
	342	+
	343	+static struct attribute *icl_uncore_clock_formats_attr[] = {
	344	+ &format_attr_event.attr,
	345	+ NULL,
	346	+};
	347	+
	348	+static struct attribute_group icl_uncore_clock_format_group = {
	349	+ .name = "format",
	350	+ .attrs = icl_uncore_clock_formats_attr,
	351	+};
	352	+
	353	+static struct intel_uncore_type icl_uncore_clockbox = {
	354	+ .name = "clock",
	355	+ .num_counters = 1,
	356	+ .num_boxes = 1,
	357	+ .fixed_ctr_bits = 48,
	358	+ .fixed_ctr = SNB_UNC_FIXED_CTR,
	359	+ .fixed_ctl = SNB_UNC_FIXED_CTR_CTRL,
	360	+ .single_fixed = 1,
	361	+ .event_mask = SNB_UNC_CTL_EV_SEL_MASK,
	362	+ .format_group = &icl_uncore_clock_format_group,
	363	+ .ops = &icl_uncore_msr_ops,
	364	+ .event_descs = icl_uncore_events,
	365	+};
	366	+
	367	+static struct intel_uncore_type icl_uncore_arb = {
	368	+ .name = "arb",
	369	+ .num_counters = 1,
	370	+ .num_boxes = 1,
	371	+ .perf_ctr_bits = 44,
	372	+ .perf_ctr = ICL_UNC_ARB_PER_CTR,
	373	+ .event_ctl = ICL_UNC_ARB_PERFEVTSEL,
	374	+ .event_mask = SNB_UNC_RAW_EVENT_MASK,
	375	+ .ops = &icl_uncore_msr_ops,
	376	+ .format_group = &snb_uncore_format_group,
	377	+};
	378	+
	379	+static struct intel_uncore_type *icl_msr_uncores[] = {
	380	+ &icl_uncore_cbox,
	381	+ &icl_uncore_arb,
	382	+ &icl_uncore_clockbox,
	383	+ NULL,
	384	+};
	385	+
	386	+static int icl_get_cbox_num(void)
	387	+{
	388	+ u64 num_boxes;
	389	+
	390	+ rdmsrl(ICL_UNC_CBO_CONFIG, num_boxes);
	391	+
	392	+ return num_boxes & ICL_UNC_NUM_CBO_MASK;
	393	+}
	394	+
	395	+void icl_uncore_cpu_init(void)
	396	+{
	397	+ uncore_msr_uncores = icl_msr_uncores;
	398	+ icl_uncore_cbox.num_boxes = icl_get_cbox_num();
	399	+}
	400	+
	401	+static struct intel_uncore_type *tgl_msr_uncores[] = {
	402	+ &icl_uncore_cbox,
	403	+ &snb_uncore_arb,
	404	+ &icl_uncore_clockbox,
	405	+ NULL,
	406	+};
	407	+
	408	+void tgl_uncore_cpu_init(void)
	409	+{
	410	+ uncore_msr_uncores = tgl_msr_uncores;
	411	+ icl_uncore_cbox.num_boxes = icl_get_cbox_num();
	412	+ icl_uncore_cbox.ops = &skl_uncore_msr_ops;
	413	+ icl_uncore_clockbox.ops = &skl_uncore_msr_ops;
	414	+ snb_uncore_arb.ops = &skl_uncore_msr_ops;
	415	+}
	416	+
279	417	enum {
280	418	SNB_PCI_UNCORE_IMC,
281	419	};
..	..	@@ -288,6 +426,18 @@
288	426	INTEL_UNCORE_EVENT_DESC(data_writes, "event=0x02"),
289	427	INTEL_UNCORE_EVENT_DESC(data_writes.scale, "6.103515625e-5"),
290	428	INTEL_UNCORE_EVENT_DESC(data_writes.unit, "MiB"),
	429	+
	430	+ INTEL_UNCORE_EVENT_DESC(gt_requests, "event=0x03"),
	431	+ INTEL_UNCORE_EVENT_DESC(gt_requests.scale, "6.103515625e-5"),
	432	+ INTEL_UNCORE_EVENT_DESC(gt_requests.unit, "MiB"),
	433	+
	434	+ INTEL_UNCORE_EVENT_DESC(ia_requests, "event=0x04"),
	435	+ INTEL_UNCORE_EVENT_DESC(ia_requests.scale, "6.103515625e-5"),
	436	+ INTEL_UNCORE_EVENT_DESC(ia_requests.unit, "MiB"),
	437	+
	438	+ INTEL_UNCORE_EVENT_DESC(io_requests, "event=0x05"),
	439	+ INTEL_UNCORE_EVENT_DESC(io_requests.scale, "6.103515625e-5"),
	440	+ INTEL_UNCORE_EVENT_DESC(io_requests.unit, "MiB"),
291	441
292	442	{ /* end: all zeroes */ },
293	443	};
..	..	@@ -304,13 +454,35 @@
304	454	#define SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE 0x5054
305	455	#define SNB_UNCORE_PCI_IMC_CTR_BASE SNB_UNCORE_PCI_IMC_DATA_READS_BASE
306	456
	457	+/* BW break down- legacy counters */
	458	+#define SNB_UNCORE_PCI_IMC_GT_REQUESTS 0x3
	459	+#define SNB_UNCORE_PCI_IMC_GT_REQUESTS_BASE 0x5040
	460	+#define SNB_UNCORE_PCI_IMC_IA_REQUESTS 0x4
	461	+#define SNB_UNCORE_PCI_IMC_IA_REQUESTS_BASE 0x5044
	462	+#define SNB_UNCORE_PCI_IMC_IO_REQUESTS 0x5
	463	+#define SNB_UNCORE_PCI_IMC_IO_REQUESTS_BASE 0x5048
	464	+
307	465	enum perf_snb_uncore_imc_freerunning_types {
308		- SNB_PCI_UNCORE_IMC_DATA = 0,
	466	+ SNB_PCI_UNCORE_IMC_DATA_READS = 0,
	467	+ SNB_PCI_UNCORE_IMC_DATA_WRITES,
	468	+ SNB_PCI_UNCORE_IMC_GT_REQUESTS,
	469	+ SNB_PCI_UNCORE_IMC_IA_REQUESTS,
	470	+ SNB_PCI_UNCORE_IMC_IO_REQUESTS,
	471	+
309	472	SNB_PCI_UNCORE_IMC_FREERUNNING_TYPE_MAX,
310	473	};
311	474
312	475	static struct freerunning_counters snb_uncore_imc_freerunning[] = {
313		- [SNB_PCI_UNCORE_IMC_DATA] = { SNB_UNCORE_PCI_IMC_DATA_READS_BASE, 0x4, 0x0, 2, 32 },
	476	+ [SNB_PCI_UNCORE_IMC_DATA_READS] = { SNB_UNCORE_PCI_IMC_DATA_READS_BASE,
	477	+ 0x0, 0x0, 1, 32 },
	478	+ [SNB_PCI_UNCORE_IMC_DATA_WRITES] = { SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE,
	479	+ 0x0, 0x0, 1, 32 },
	480	+ [SNB_PCI_UNCORE_IMC_GT_REQUESTS] = { SNB_UNCORE_PCI_IMC_GT_REQUESTS_BASE,
	481	+ 0x0, 0x0, 1, 32 },
	482	+ [SNB_PCI_UNCORE_IMC_IA_REQUESTS] = { SNB_UNCORE_PCI_IMC_IA_REQUESTS_BASE,
	483	+ 0x0, 0x0, 1, 32 },
	484	+ [SNB_PCI_UNCORE_IMC_IO_REQUESTS] = { SNB_UNCORE_PCI_IMC_IO_REQUESTS_BASE,
	485	+ 0x0, 0x0, 1, 32 },
314	486	};
315	487
316	488	static struct attribute *snb_uncore_imc_formats_attr[] = {
..	..	@@ -325,6 +497,7 @@
325	497
326	498	static void snb_uncore_imc_init_box(struct intel_uncore_box *box)
327	499	{
	500	+ struct intel_uncore_type *type = box->pmu->type;
328	501	struct pci_dev *pdev = box->pci_dev;
329	502	int where = SNB_UNCORE_PCI_IMC_BAR_OFFSET;
330	503	resource_size_t addr;
..	..	@@ -340,13 +513,11 @@
340	513
341	514	addr &= ~(PAGE_SIZE - 1);
342	515
343		- box->io_addr = ioremap(addr, SNB_UNCORE_PCI_IMC_MAP_SIZE);
344		- box->hrtimer_duration = UNCORE_SNB_IMC_HRTIMER_INTERVAL;
345		-}
	516	+ box->io_addr = ioremap(addr, type->mmio_map_size);
	517	+ if (!box->io_addr)
	518	+ pr_warn("perf uncore: Failed to ioremap for %s.\n", type->name);
346	519
347		-static void snb_uncore_imc_exit_box(struct intel_uncore_box *box)
348		-{
349		- iounmap(box->io_addr);
	520	+ box->hrtimer_duration = UNCORE_SNB_IMC_HRTIMER_INTERVAL;
350	521	}
351	522
352	523	static void snb_uncore_imc_enable_box(struct intel_uncore_box *box)
..	..	@@ -360,13 +531,6 @@
360	531
361	532	static void snb_uncore_imc_disable_event(struct intel_uncore_box box, struct perf_event event)
362	533	{}
363		-
364		-static u64 snb_uncore_imc_read_counter(struct intel_uncore_box box, struct perf_event event)
365		-{
366		- struct hw_perf_event *hwc = &event->hw;
367		-
368		- return (u64)(unsigned int )(box->io_addr + hwc->event_base);
369		-}
370	534
371	535	/*
372	536	* Keep the custom event_init() function compatible with old event
..	..	@@ -393,13 +557,7 @@
393	557	return -EINVAL;
394	558
395	559	/* unsupported modes and filters */
396		- if (event->attr.exclude_user \|\|
397		- event->attr.exclude_kernel \|\|
398		- event->attr.exclude_hv \|\|
399		- event->attr.exclude_idle \|\|
400		- event->attr.exclude_host \|\|
401		- event->attr.exclude_guest \|\|
402		- event->attr.sample_period) /* no sampling */
	560	+ if (event->attr.sample_period) /* no sampling */
403	561	return -EINVAL;
404	562
405	563	/*
..	..	@@ -436,6 +594,18 @@
436	594	break;
437	595	case SNB_UNCORE_PCI_IMC_DATA_WRITES:
438	596	base = SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE;
	597	+ idx = UNCORE_PMC_IDX_FREERUNNING;
	598	+ break;
	599	+ case SNB_UNCORE_PCI_IMC_GT_REQUESTS:
	600	+ base = SNB_UNCORE_PCI_IMC_GT_REQUESTS_BASE;
	601	+ idx = UNCORE_PMC_IDX_FREERUNNING;
	602	+ break;
	603	+ case SNB_UNCORE_PCI_IMC_IA_REQUESTS:
	604	+ base = SNB_UNCORE_PCI_IMC_IA_REQUESTS_BASE;
	605	+ idx = UNCORE_PMC_IDX_FREERUNNING;
	606	+ break;
	607	+ case SNB_UNCORE_PCI_IMC_IO_REQUESTS:
	608	+ base = SNB_UNCORE_PCI_IMC_IO_REQUESTS_BASE;
439	609	idx = UNCORE_PMC_IDX_FREERUNNING;
440	610	break;
441	611	default:
..	..	@@ -487,6 +657,22 @@
487	657	return 0;
488	658	}
489	659
	660	+static u64 snb_uncore_imc_read_counter(struct intel_uncore_box box, struct perf_event event)
	661	+{
	662	+ struct hw_perf_event *hwc = &event->hw;
	663	+
	664	+ /*
	665	+ * SNB IMC counters are 32-bit and are laid out back to back
	666	+ * in MMIO space. Therefore we must use a 32-bit accessor function
	667	+ * using readq() from uncore_mmio_read_counter() causes problems
	668	+ * because it is reading 64-bit at a time. This is okay for the
	669	+ * uncore_perf_event_update() function because it drops the upper
	670	+ * 32-bits but not okay for plain uncore_read_counter() as invoked
	671	+ * in uncore_pmu_event_start().
	672	+ */
	673	+ return (u64)readl(box->io_addr + hwc->event_base);
	674	+}
	675	+
490	676	static struct pmu snb_uncore_imc_pmu = {
491	677	.task_ctx_nr = perf_invalid_context,
492	678	.event_init = snb_uncore_imc_event_init,
..	..	@@ -495,11 +681,12 @@
495	681	.start = uncore_pmu_event_start,
496	682	.stop = uncore_pmu_event_stop,
497	683	.read = uncore_pmu_event_read,
	684	+ .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
498	685	};
499	686
500	687	static struct intel_uncore_ops snb_uncore_imc_ops = {
501	688	.init_box = snb_uncore_imc_init_box,
502		- .exit_box = snb_uncore_imc_exit_box,
	689	+ .exit_box = uncore_mmio_exit_box,
503	690	.enable_box = snb_uncore_imc_enable_box,
504	691	.disable_box = snb_uncore_imc_disable_box,
505	692	.disable_event = snb_uncore_imc_disable_event,
..	..	@@ -510,9 +697,10 @@
510	697
511	698	static struct intel_uncore_type snb_uncore_imc = {
512	699	.name = "imc",
513		- .num_counters = 2,
	700	+ .num_counters = 5,
514	701	.num_boxes = 1,
515	702	.num_freerunning_types = SNB_PCI_UNCORE_IMC_FREERUNNING_TYPE_MAX,
	703	+ .mmio_map_size = SNB_UNCORE_PCI_IMC_MAP_SIZE,
516	704	.freerunning = snb_uncore_imc_freerunning,
517	705	.event_descs = snb_uncore_imc_events,
518	706	.format_group = &snb_uncore_imc_format_group,
..	..	@@ -591,6 +779,10 @@
591	779	.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
592	780	},
593	781	{ /* IMC */
	782	+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_E3_IMC),
	783	+ .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
	784	+ },
	785	+ { /* IMC */
594	786	PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_Y_IMC),
595	787	.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
596	788	},
..	..	@@ -608,6 +800,14 @@
608	800	},
609	801	{ /* IMC */
610	802	PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_SQ_IMC),
	803	+ .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
	804	+ },
	805	+ { /* IMC */
	806	+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_HQ_IMC),
	807	+ .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
	808	+ },
	809	+ { /* IMC */
	810	+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_WQ_IMC),
611	811	.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
612	812	},
613	813	{ /* IMC */
..	..	@@ -666,6 +866,82 @@
666	866	PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_8S_S_IMC),
667	867	.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
668	868	},
	869	+ { /* IMC */
	870	+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AML_YD_IMC),
	871	+ .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
	872	+ },
	873	+ { /* IMC */
	874	+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AML_YQ_IMC),
	875	+ .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
	876	+ },
	877	+ { /* IMC */
	878	+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WHL_UQ_IMC),
	879	+ .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
	880	+ },
	881	+ { /* IMC */
	882	+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WHL_4_UQ_IMC),
	883	+ .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
	884	+ },
	885	+ { /* IMC */
	886	+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WHL_UD_IMC),
	887	+ .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
	888	+ },
	889	+ { /* IMC */
	890	+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_H1_IMC),
	891	+ .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
	892	+ },
	893	+ { /* IMC */
	894	+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_H2_IMC),
	895	+ .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
	896	+ },
	897	+ { /* IMC */
	898	+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_H3_IMC),
	899	+ .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
	900	+ },
	901	+ { /* IMC */
	902	+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_U1_IMC),
	903	+ .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
	904	+ },
	905	+ { /* IMC */
	906	+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_U2_IMC),
	907	+ .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
	908	+ },
	909	+ { /* IMC */
	910	+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_U3_IMC),
	911	+ .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
	912	+ },
	913	+ { /* IMC */
	914	+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_S1_IMC),
	915	+ .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
	916	+ },
	917	+ { /* IMC */
	918	+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_S2_IMC),
	919	+ .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
	920	+ },
	921	+ { /* IMC */
	922	+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_S3_IMC),
	923	+ .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
	924	+ },
	925	+ { /* IMC */
	926	+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_S4_IMC),
	927	+ .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
	928	+ },
	929	+ { /* IMC */
	930	+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_S5_IMC),
	931	+ .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
	932	+ },
	933	+ { /* end: all zeroes */ },
	934	+};
	935	+
	936	+static const struct pci_device_id icl_uncore_pci_ids[] = {
	937	+ { /* IMC */
	938	+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICL_U_IMC),
	939	+ .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
	940	+ },
	941	+ { /* IMC */
	942	+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICL_U2_IMC),
	943	+ .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
	944	+ },
669	945	{ /* end: all zeroes */ },
670	946	};
671	947
..	..	@@ -694,6 +970,11 @@
694	970	.id_table = skl_uncore_pci_ids,
695	971	};
696	972
	973	+static struct pci_driver icl_uncore_pci_driver = {
	974	+ .name = "icl_uncore",
	975	+ .id_table = icl_uncore_pci_ids,
	976	+};
	977	+
697	978	struct imc_uncore_pci_dev {
698	979	__u32 pci_id;
699	980	struct pci_driver *driver;
..	..	@@ -714,11 +995,14 @@
714	995	IMC_DEV(SKL_HQ_IMC, &skl_uncore_pci_driver), /* 6th Gen Core H Quad Core */
715	996	IMC_DEV(SKL_SD_IMC, &skl_uncore_pci_driver), /* 6th Gen Core S Dual Core */
716	997	IMC_DEV(SKL_SQ_IMC, &skl_uncore_pci_driver), /* 6th Gen Core S Quad Core */
	998	+ IMC_DEV(SKL_E3_IMC, &skl_uncore_pci_driver), /* Xeon E3 V5 Gen Core processor */
717	999	IMC_DEV(KBL_Y_IMC, &skl_uncore_pci_driver), /* 7th Gen Core Y */
718	1000	IMC_DEV(KBL_U_IMC, &skl_uncore_pci_driver), /* 7th Gen Core U */
719	1001	IMC_DEV(KBL_UQ_IMC, &skl_uncore_pci_driver), /* 7th Gen Core U Quad Core */
720	1002	IMC_DEV(KBL_SD_IMC, &skl_uncore_pci_driver), /* 7th Gen Core S Dual Core */
721	1003	IMC_DEV(KBL_SQ_IMC, &skl_uncore_pci_driver), /* 7th Gen Core S Quad Core */
	1004	+ IMC_DEV(KBL_HQ_IMC, &skl_uncore_pci_driver), /* 7th Gen Core H Quad Core */
	1005	+ IMC_DEV(KBL_WQ_IMC, &skl_uncore_pci_driver), /* 7th Gen Core S 4 cores Work Station */
722	1006	IMC_DEV(CFL_2U_IMC, &skl_uncore_pci_driver), /* 8th Gen Core U 2 Cores */
723	1007	IMC_DEV(CFL_4U_IMC, &skl_uncore_pci_driver), /* 8th Gen Core U 4 Cores */
724	1008	IMC_DEV(CFL_4H_IMC, &skl_uncore_pci_driver), /* 8th Gen Core H 4 Cores */
..	..	@@ -733,6 +1017,24 @@
733	1017	IMC_DEV(CFL_4S_S_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 4 Cores Server */
734	1018	IMC_DEV(CFL_6S_S_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 6 Cores Server */
735	1019	IMC_DEV(CFL_8S_S_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 8 Cores Server */
	1020	+ IMC_DEV(AML_YD_IMC, &skl_uncore_pci_driver), /* 8th Gen Core Y Mobile Dual Core */
	1021	+ IMC_DEV(AML_YQ_IMC, &skl_uncore_pci_driver), /* 8th Gen Core Y Mobile Quad Core */
	1022	+ IMC_DEV(WHL_UQ_IMC, &skl_uncore_pci_driver), /* 8th Gen Core U Mobile Quad Core */
	1023	+ IMC_DEV(WHL_4_UQ_IMC, &skl_uncore_pci_driver), /* 8th Gen Core U Mobile Quad Core */
	1024	+ IMC_DEV(WHL_UD_IMC, &skl_uncore_pci_driver), /* 8th Gen Core U Mobile Dual Core */
	1025	+ IMC_DEV(CML_H1_IMC, &skl_uncore_pci_driver),
	1026	+ IMC_DEV(CML_H2_IMC, &skl_uncore_pci_driver),
	1027	+ IMC_DEV(CML_H3_IMC, &skl_uncore_pci_driver),
	1028	+ IMC_DEV(CML_U1_IMC, &skl_uncore_pci_driver),
	1029	+ IMC_DEV(CML_U2_IMC, &skl_uncore_pci_driver),
	1030	+ IMC_DEV(CML_U3_IMC, &skl_uncore_pci_driver),
	1031	+ IMC_DEV(CML_S1_IMC, &skl_uncore_pci_driver),
	1032	+ IMC_DEV(CML_S2_IMC, &skl_uncore_pci_driver),
	1033	+ IMC_DEV(CML_S3_IMC, &skl_uncore_pci_driver),
	1034	+ IMC_DEV(CML_S4_IMC, &skl_uncore_pci_driver),
	1035	+ IMC_DEV(CML_S5_IMC, &skl_uncore_pci_driver),
	1036	+ IMC_DEV(ICL_U_IMC, &icl_uncore_pci_driver), /* 10th Gen Core Mobile */
	1037	+ IMC_DEV(ICL_U2_IMC, &icl_uncore_pci_driver), /* 10th Gen Core Mobile */
736	1038	{ /* end marker */ }
737	1039	};
738	1040
..	..	@@ -875,3 +1177,162 @@
875	1177	}
876	1178
877	1179	/* end of Nehalem uncore support */
	1180	+
	1181	+/* Tiger Lake MMIO uncore support */
	1182	+
	1183	+static const struct pci_device_id tgl_uncore_pci_ids[] = {
	1184	+ { /* IMC */
	1185	+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_U1_IMC),
	1186	+ .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
	1187	+ },
	1188	+ { /* IMC */
	1189	+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_U2_IMC),
	1190	+ .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
	1191	+ },
	1192	+ { /* IMC */
	1193	+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_U3_IMC),
	1194	+ .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
	1195	+ },
	1196	+ { /* IMC */
	1197	+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_U4_IMC),
	1198	+ .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
	1199	+ },
	1200	+ { /* IMC */
	1201	+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_H_IMC),
	1202	+ .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
	1203	+ },
	1204	+ { /* end: all zeroes */ }
	1205	+};
	1206	+
	1207	+enum perf_tgl_uncore_imc_freerunning_types {
	1208	+ TGL_MMIO_UNCORE_IMC_DATA_TOTAL,
	1209	+ TGL_MMIO_UNCORE_IMC_DATA_READ,
	1210	+ TGL_MMIO_UNCORE_IMC_DATA_WRITE,
	1211	+ TGL_MMIO_UNCORE_IMC_FREERUNNING_TYPE_MAX
	1212	+};
	1213	+
	1214	+static struct freerunning_counters tgl_l_uncore_imc_freerunning[] = {
	1215	+ [TGL_MMIO_UNCORE_IMC_DATA_TOTAL] = { 0x5040, 0x0, 0x0, 1, 64 },
	1216	+ [TGL_MMIO_UNCORE_IMC_DATA_READ] = { 0x5058, 0x0, 0x0, 1, 64 },
	1217	+ [TGL_MMIO_UNCORE_IMC_DATA_WRITE] = { 0x50A0, 0x0, 0x0, 1, 64 },
	1218	+};
	1219	+
	1220	+static struct freerunning_counters tgl_uncore_imc_freerunning[] = {
	1221	+ [TGL_MMIO_UNCORE_IMC_DATA_TOTAL] = { 0xd840, 0x0, 0x0, 1, 64 },
	1222	+ [TGL_MMIO_UNCORE_IMC_DATA_READ] = { 0xd858, 0x0, 0x0, 1, 64 },
	1223	+ [TGL_MMIO_UNCORE_IMC_DATA_WRITE] = { 0xd8A0, 0x0, 0x0, 1, 64 },
	1224	+};
	1225	+
	1226	+static struct uncore_event_desc tgl_uncore_imc_events[] = {
	1227	+ INTEL_UNCORE_EVENT_DESC(data_total, "event=0xff,umask=0x10"),
	1228	+ INTEL_UNCORE_EVENT_DESC(data_total.scale, "6.103515625e-5"),
	1229	+ INTEL_UNCORE_EVENT_DESC(data_total.unit, "MiB"),
	1230	+
	1231	+ INTEL_UNCORE_EVENT_DESC(data_read, "event=0xff,umask=0x20"),
	1232	+ INTEL_UNCORE_EVENT_DESC(data_read.scale, "6.103515625e-5"),
	1233	+ INTEL_UNCORE_EVENT_DESC(data_read.unit, "MiB"),
	1234	+
	1235	+ INTEL_UNCORE_EVENT_DESC(data_write, "event=0xff,umask=0x30"),
	1236	+ INTEL_UNCORE_EVENT_DESC(data_write.scale, "6.103515625e-5"),
	1237	+ INTEL_UNCORE_EVENT_DESC(data_write.unit, "MiB"),
	1238	+
	1239	+ { /* end: all zeroes */ }
	1240	+};
	1241	+
	1242	+static struct pci_dev *tgl_uncore_get_mc_dev(void)
	1243	+{
	1244	+ const struct pci_device_id *ids = tgl_uncore_pci_ids;
	1245	+ struct pci_dev *mc_dev = NULL;
	1246	+
	1247	+ while (ids && ids->vendor) {
	1248	+ mc_dev = pci_get_device(PCI_VENDOR_ID_INTEL, ids->device, NULL);
	1249	+ if (mc_dev)
	1250	+ return mc_dev;
	1251	+ ids++;
	1252	+ }
	1253	+
	1254	+ return mc_dev;
	1255	+}
	1256	+
	1257	+#define TGL_UNCORE_MMIO_IMC_MEM_OFFSET 0x10000
	1258	+#define TGL_UNCORE_PCI_IMC_MAP_SIZE 0xe000
	1259	+
	1260	+static void tgl_uncore_imc_freerunning_init_box(struct intel_uncore_box *box)
	1261	+{
	1262	+ struct pci_dev *pdev = tgl_uncore_get_mc_dev();
	1263	+ struct intel_uncore_pmu *pmu = box->pmu;
	1264	+ struct intel_uncore_type *type = pmu->type;
	1265	+ resource_size_t addr;
	1266	+ u32 mch_bar;
	1267	+
	1268	+ if (!pdev) {
	1269	+ pr_warn("perf uncore: Cannot find matched IMC device.\n");
	1270	+ return;
	1271	+ }
	1272	+
	1273	+ pci_read_config_dword(pdev, SNB_UNCORE_PCI_IMC_BAR_OFFSET, &mch_bar);
	1274	+ /* MCHBAR is disabled */
	1275	+ if (!(mch_bar & BIT(0))) {
	1276	+ pr_warn("perf uncore: MCHBAR is disabled. Failed to map IMC free-running counters.\n");
	1277	+ return;
	1278	+ }
	1279	+ mch_bar &= ~BIT(0);
	1280	+ addr = (resource_size_t)(mch_bar + TGL_UNCORE_MMIO_IMC_MEM_OFFSET * pmu->pmu_idx);
	1281	+
	1282	+#ifdef CONFIG_PHYS_ADDR_T_64BIT
	1283	+ pci_read_config_dword(pdev, SNB_UNCORE_PCI_IMC_BAR_OFFSET + 4, &mch_bar);
	1284	+ addr \|= ((resource_size_t)mch_bar << 32);
	1285	+#endif
	1286	+
	1287	+ box->io_addr = ioremap(addr, type->mmio_map_size);
	1288	+ if (!box->io_addr)
	1289	+ pr_warn("perf uncore: Failed to ioremap for %s.\n", type->name);
	1290	+}
	1291	+
	1292	+static struct intel_uncore_ops tgl_uncore_imc_freerunning_ops = {
	1293	+ .init_box = tgl_uncore_imc_freerunning_init_box,
	1294	+ .exit_box = uncore_mmio_exit_box,
	1295	+ .read_counter = uncore_mmio_read_counter,
	1296	+ .hw_config = uncore_freerunning_hw_config,
	1297	+};
	1298	+
	1299	+static struct attribute *tgl_uncore_imc_formats_attr[] = {
	1300	+ &format_attr_event.attr,
	1301	+ &format_attr_umask.attr,
	1302	+ NULL
	1303	+};
	1304	+
	1305	+static const struct attribute_group tgl_uncore_imc_format_group = {
	1306	+ .name = "format",
	1307	+ .attrs = tgl_uncore_imc_formats_attr,
	1308	+};
	1309	+
	1310	+static struct intel_uncore_type tgl_uncore_imc_free_running = {
	1311	+ .name = "imc_free_running",
	1312	+ .num_counters = 3,
	1313	+ .num_boxes = 2,
	1314	+ .num_freerunning_types = TGL_MMIO_UNCORE_IMC_FREERUNNING_TYPE_MAX,
	1315	+ .mmio_map_size = TGL_UNCORE_PCI_IMC_MAP_SIZE,
	1316	+ .freerunning = tgl_uncore_imc_freerunning,
	1317	+ .ops = &tgl_uncore_imc_freerunning_ops,
	1318	+ .event_descs = tgl_uncore_imc_events,
	1319	+ .format_group = &tgl_uncore_imc_format_group,
	1320	+};
	1321	+
	1322	+static struct intel_uncore_type *tgl_mmio_uncores[] = {
	1323	+ &tgl_uncore_imc_free_running,
	1324	+ NULL
	1325	+};
	1326	+
	1327	+void tgl_l_uncore_mmio_init(void)
	1328	+{
	1329	+ tgl_uncore_imc_free_running.freerunning = tgl_l_uncore_imc_freerunning;
	1330	+ uncore_mmio_uncores = tgl_mmio_uncores;
	1331	+}
	1332	+
	1333	+void tgl_uncore_mmio_init(void)
	1334	+{
	1335	+ uncore_mmio_uncores = tgl_mmio_uncores;
	1336	+}
	1337	+
	1338	+/* end of Tiger Lake MMIO uncore support */