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hc
2023-12-06 08f87f769b595151be1afeff53e144f543faa614 
 kernel/arch/x86/events/intel/cstate.c
....@@ -40,51 +40,57 @@
4040  * Model specific counters:
4141  *	MSR_CORE_C1_RES: CORE C1 Residency Counter
4242  *			 perf code: 0x00
43
- *			 Available model: SLM,AMT,GLM,CNL
43
+ *			 Available model: SLM,AMT,GLM,CNL,TNT
4444  *			 Scope: Core (each processor core has a MSR)
4545  *	MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
4646  *			       perf code: 0x01
4747  *			       Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM,
48
-						CNL
48
+ *						CNL,KBL,CML,TNT
4949  *			       Scope: Core
5050  *	MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter
5151  *			       perf code: 0x02
5252  *			       Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
53
- *						SKL,KNL,GLM,CNL
53
+ *						SKL,KNL,GLM,CNL,KBL,CML,ICL,TGL,
54
+ *						TNT
5455  *			       Scope: Core
5556  *	MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
5657  *			       perf code: 0x03
57
- *			       Available model: SNB,IVB,HSW,BDW,SKL,CNL
58
+ *			       Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML,
59
+ *						ICL,TGL
5860  *			       Scope: Core
5961  *	MSR_PKG_C2_RESIDENCY:  Package C2 Residency Counter.
6062  *			       perf code: 0x00
61
- *			       Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL
63
+ *			       Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL,
64
+ *						KBL,CML,ICL,TGL,TNT
6265  *			       Scope: Package (physical package)
6366  *	MSR_PKG_C3_RESIDENCY:  Package C3 Residency Counter.
6467  *			       perf code: 0x01
6568  *			       Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL,
66
- *						GLM,CNL
69
+ *						GLM,CNL,KBL,CML,ICL,TGL,TNT
6770  *			       Scope: Package (physical package)
6871  *	MSR_PKG_C6_RESIDENCY:  Package C6 Residency Counter.
6972  *			       perf code: 0x02
70
- *			       Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW
71
- *						SKL,KNL,GLM,CNL
73
+ *			       Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
74
+ *						SKL,KNL,GLM,CNL,KBL,CML,ICL,TGL,
75
+ *						TNT
7276  *			       Scope: Package (physical package)
7377  *	MSR_PKG_C7_RESIDENCY:  Package C7 Residency Counter.
7478  *			       perf code: 0x03
75
- *			       Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL
79
+ *			       Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL,
80
+ *						KBL,CML,ICL,TGL
7681  *			       Scope: Package (physical package)
7782  *	MSR_PKG_C8_RESIDENCY:  Package C8 Residency Counter.
7883  *			       perf code: 0x04
79
- *			       Available model: HSW ULT,KBL,CNL
84
+ *			       Available model: HSW ULT,KBL,CNL,CML,ICL,TGL
8085  *			       Scope: Package (physical package)
8186  *	MSR_PKG_C9_RESIDENCY:  Package C9 Residency Counter.
8287  *			       perf code: 0x05
83
- *			       Available model: HSW ULT,KBL,CNL
88
+ *			       Available model: HSW ULT,KBL,CNL,CML,ICL,TGL
8489  *			       Scope: Package (physical package)
8590  *	MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
8691  *			       perf code: 0x06
87
- *			       Available model: HSW ULT,KBL,GLM,CNL
92
+ *			       Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL,
93
+ *						TNT
8894  *			       Scope: Package (physical package)
8995  *
9096  */
....@@ -96,6 +102,7 @@
96102 #include <asm/cpu_device_id.h>
97103 #include <asm/intel-family.h>
98104 #include "../perf_event.h"
105
+#include "../probe.h"
99106 
100107 MODULE_LICENSE("GPL");
101108 
....@@ -144,25 +151,42 @@
144151 	PERF_CSTATE_CORE_EVENT_MAX,
145152 };
146153 
147
-PMU_EVENT_ATTR_STRING(c1-residency, evattr_cstate_core_c1, "event=0x00");
148
-PMU_EVENT_ATTR_STRING(c3-residency, evattr_cstate_core_c3, "event=0x01");
149
-PMU_EVENT_ATTR_STRING(c6-residency, evattr_cstate_core_c6, "event=0x02");
150
-PMU_EVENT_ATTR_STRING(c7-residency, evattr_cstate_core_c7, "event=0x03");
154
+PMU_EVENT_ATTR_STRING(c1-residency, attr_cstate_core_c1, "event=0x00");
155
+PMU_EVENT_ATTR_STRING(c3-residency, attr_cstate_core_c3, "event=0x01");
156
+PMU_EVENT_ATTR_STRING(c6-residency, attr_cstate_core_c6, "event=0x02");
157
+PMU_EVENT_ATTR_STRING(c7-residency, attr_cstate_core_c7, "event=0x03");
151158 
152
-static struct perf_cstate_msr core_msr[] = {
153
-	[PERF_CSTATE_CORE_C1_RES] = { MSR_CORE_C1_RES,		&evattr_cstate_core_c1 },
154
-	[PERF_CSTATE_CORE_C3_RES] = { MSR_CORE_C3_RESIDENCY,	&evattr_cstate_core_c3 },
155
-	[PERF_CSTATE_CORE_C6_RES] = { MSR_CORE_C6_RESIDENCY,	&evattr_cstate_core_c6 },
156
-	[PERF_CSTATE_CORE_C7_RES] = { MSR_CORE_C7_RESIDENCY,	&evattr_cstate_core_c7 },
159
+static unsigned long core_msr_mask;
160
+
161
+PMU_EVENT_GROUP(events, cstate_core_c1);
162
+PMU_EVENT_GROUP(events, cstate_core_c3);
163
+PMU_EVENT_GROUP(events, cstate_core_c6);
164
+PMU_EVENT_GROUP(events, cstate_core_c7);
165
+
166
+static bool test_msr(int idx, void *data)
167
+{
168
+	return test_bit(idx, (unsigned long *) data);
169
+}
170
+
171
+static struct perf_msr core_msr[] = {
172
+	[PERF_CSTATE_CORE_C1_RES] = { MSR_CORE_C1_RES,		&group_cstate_core_c1,	test_msr },
173
+	[PERF_CSTATE_CORE_C3_RES] = { MSR_CORE_C3_RESIDENCY,	&group_cstate_core_c3,	test_msr },
174
+	[PERF_CSTATE_CORE_C6_RES] = { MSR_CORE_C6_RESIDENCY,	&group_cstate_core_c6,	test_msr },
175
+	[PERF_CSTATE_CORE_C7_RES] = { MSR_CORE_C7_RESIDENCY,	&group_cstate_core_c7,	test_msr },
157176 };
158177 
159
-static struct attribute *core_events_attrs[PERF_CSTATE_CORE_EVENT_MAX + 1] = {
178
+static struct attribute *attrs_empty[] = {
160179 	NULL,
161180 };
162181 
182
+/*
183
+ * There are no default events, but we need to create
184
+ * "events" group (with empty attrs) before updating
185
+ * it with detected events.
186
+ */
163187 static struct attribute_group core_events_attr_group = {
164188 	.name = "events",
165
-	.attrs = core_events_attrs,
189
+	.attrs = attrs_empty,
166190 };
167191 
168192 DEFINE_CSTATE_FORMAT_ATTR(core_event, event, "config:0-63");
....@@ -211,31 +235,37 @@
211235 	PERF_CSTATE_PKG_EVENT_MAX,
212236 };
213237 
214
-PMU_EVENT_ATTR_STRING(c2-residency, evattr_cstate_pkg_c2, "event=0x00");
215
-PMU_EVENT_ATTR_STRING(c3-residency, evattr_cstate_pkg_c3, "event=0x01");
216
-PMU_EVENT_ATTR_STRING(c6-residency, evattr_cstate_pkg_c6, "event=0x02");
217
-PMU_EVENT_ATTR_STRING(c7-residency, evattr_cstate_pkg_c7, "event=0x03");
218
-PMU_EVENT_ATTR_STRING(c8-residency, evattr_cstate_pkg_c8, "event=0x04");
219
-PMU_EVENT_ATTR_STRING(c9-residency, evattr_cstate_pkg_c9, "event=0x05");
220
-PMU_EVENT_ATTR_STRING(c10-residency, evattr_cstate_pkg_c10, "event=0x06");
238
+PMU_EVENT_ATTR_STRING(c2-residency,  attr_cstate_pkg_c2,  "event=0x00");
239
+PMU_EVENT_ATTR_STRING(c3-residency,  attr_cstate_pkg_c3,  "event=0x01");
240
+PMU_EVENT_ATTR_STRING(c6-residency,  attr_cstate_pkg_c6,  "event=0x02");
241
+PMU_EVENT_ATTR_STRING(c7-residency,  attr_cstate_pkg_c7,  "event=0x03");
242
+PMU_EVENT_ATTR_STRING(c8-residency,  attr_cstate_pkg_c8,  "event=0x04");
243
+PMU_EVENT_ATTR_STRING(c9-residency,  attr_cstate_pkg_c9,  "event=0x05");
244
+PMU_EVENT_ATTR_STRING(c10-residency, attr_cstate_pkg_c10, "event=0x06");
221245 
222
-static struct perf_cstate_msr pkg_msr[] = {
223
-	[PERF_CSTATE_PKG_C2_RES] = { MSR_PKG_C2_RESIDENCY,	&evattr_cstate_pkg_c2 },
224
-	[PERF_CSTATE_PKG_C3_RES] = { MSR_PKG_C3_RESIDENCY,	&evattr_cstate_pkg_c3 },
225
-	[PERF_CSTATE_PKG_C6_RES] = { MSR_PKG_C6_RESIDENCY,	&evattr_cstate_pkg_c6 },
226
-	[PERF_CSTATE_PKG_C7_RES] = { MSR_PKG_C7_RESIDENCY,	&evattr_cstate_pkg_c7 },
227
-	[PERF_CSTATE_PKG_C8_RES] = { MSR_PKG_C8_RESIDENCY,	&evattr_cstate_pkg_c8 },
228
-	[PERF_CSTATE_PKG_C9_RES] = { MSR_PKG_C9_RESIDENCY,	&evattr_cstate_pkg_c9 },
229
-	[PERF_CSTATE_PKG_C10_RES] = { MSR_PKG_C10_RESIDENCY,	&evattr_cstate_pkg_c10 },
230
-};
246
+static unsigned long pkg_msr_mask;
231247 
232
-static struct attribute *pkg_events_attrs[PERF_CSTATE_PKG_EVENT_MAX + 1] = {
233
-	NULL,
248
+PMU_EVENT_GROUP(events, cstate_pkg_c2);
249
+PMU_EVENT_GROUP(events, cstate_pkg_c3);
250
+PMU_EVENT_GROUP(events, cstate_pkg_c6);
251
+PMU_EVENT_GROUP(events, cstate_pkg_c7);
252
+PMU_EVENT_GROUP(events, cstate_pkg_c8);
253
+PMU_EVENT_GROUP(events, cstate_pkg_c9);
254
+PMU_EVENT_GROUP(events, cstate_pkg_c10);
255
+
256
+static struct perf_msr pkg_msr[] = {
257
+	[PERF_CSTATE_PKG_C2_RES]  = { MSR_PKG_C2_RESIDENCY,	&group_cstate_pkg_c2,	test_msr },
258
+	[PERF_CSTATE_PKG_C3_RES]  = { MSR_PKG_C3_RESIDENCY,	&group_cstate_pkg_c3,	test_msr },
259
+	[PERF_CSTATE_PKG_C6_RES]  = { MSR_PKG_C6_RESIDENCY,	&group_cstate_pkg_c6,	test_msr },
260
+	[PERF_CSTATE_PKG_C7_RES]  = { MSR_PKG_C7_RESIDENCY,	&group_cstate_pkg_c7,	test_msr },
261
+	[PERF_CSTATE_PKG_C8_RES]  = { MSR_PKG_C8_RESIDENCY,	&group_cstate_pkg_c8,	test_msr },
262
+	[PERF_CSTATE_PKG_C9_RES]  = { MSR_PKG_C9_RESIDENCY,	&group_cstate_pkg_c9,	test_msr },
263
+	[PERF_CSTATE_PKG_C10_RES] = { MSR_PKG_C10_RESIDENCY,	&group_cstate_pkg_c10,	test_msr },
234264 };
235265 
236266 static struct attribute_group pkg_events_attr_group = {
237267 	.name = "events",
238
-	.attrs = pkg_events_attrs,
268
+	.attrs = attrs_empty,
239269 };
240270 
241271 DEFINE_CSTATE_FORMAT_ATTR(pkg_event, event, "config:0-63");
....@@ -280,13 +310,7 @@
280310 		return -ENOENT;
281311 
282312 	/* unsupported modes and filters */
283
-	if (event->attr.exclude_user   ||
284
-	    event->attr.exclude_kernel ||
285
-	    event->attr.exclude_hv     ||
286
-	    event->attr.exclude_idle   ||
287
-	    event->attr.exclude_host   ||
288
-	    event->attr.exclude_guest  ||
289
-	    event->attr.sample_period) /* no sampling */
313
+	if (event->attr.sample_period) /* no sampling */
290314 		return -EINVAL;
291315 
292316 	if (event->cpu < 0)
....@@ -295,7 +319,8 @@
295319 	if (event->pmu == &cstate_core_pmu) {
296320 		if (cfg >= PERF_CSTATE_CORE_EVENT_MAX)
297321 			return -EINVAL;
298
-		if (!core_msr[cfg].attr)
322
+		cfg = array_index_nospec((unsigned long)cfg, PERF_CSTATE_CORE_EVENT_MAX);
323
+		if (!(core_msr_mask & (1 << cfg)))
299324 			return -EINVAL;
300325 		event->hw.event_base = core_msr[cfg].msr;
301326 		cpu = cpumask_any_and(&cstate_core_cpu_mask,
....@@ -304,11 +329,11 @@
304329 		if (cfg >= PERF_CSTATE_PKG_EVENT_MAX)
305330 			return -EINVAL;
306331 		cfg = array_index_nospec((unsigned long)cfg, PERF_CSTATE_PKG_EVENT_MAX);
307
-		if (!pkg_msr[cfg].attr)
332
+		if (!(pkg_msr_mask & (1 << cfg)))
308333 			return -EINVAL;
309334 		event->hw.event_base = pkg_msr[cfg].msr;
310335 		cpu = cpumask_any_and(&cstate_pkg_cpu_mask,
311
-				      topology_core_cpumask(event->cpu));
336
+				      topology_die_cpumask(event->cpu));
312337 	} else {
313338 		return -ENOENT;
314339 	}
....@@ -391,7 +416,7 @@
391416 	if (has_cstate_pkg &&
392417 	    cpumask_test_and_clear_cpu(cpu, &cstate_pkg_cpu_mask)) {
393418 
394
-		target = cpumask_any_but(topology_core_cpumask(cpu), cpu);
419
+		target = cpumask_any_but(topology_die_cpumask(cpu), cpu);
395420 		/* Migrate events if there is a valid target */
396421 		if (target < nr_cpu_ids) {
397422 			cpumask_set_cpu(target, &cstate_pkg_cpu_mask);
....@@ -420,15 +445,35 @@
420445 	 * in the package cpu mask as the designated reader.
421446 	 */
422447 	target = cpumask_any_and(&cstate_pkg_cpu_mask,
423
-				 topology_core_cpumask(cpu));
448
+				 topology_die_cpumask(cpu));
424449 	if (has_cstate_pkg && target >= nr_cpu_ids)
425450 		cpumask_set_cpu(cpu, &cstate_pkg_cpu_mask);
426451 
427452 	return 0;
428453 }
429454 
455
+static const struct attribute_group *core_attr_update[] = {
456
+	&group_cstate_core_c1,
457
+	&group_cstate_core_c3,
458
+	&group_cstate_core_c6,
459
+	&group_cstate_core_c7,
460
+	NULL,
461
+};
462
+
463
+static const struct attribute_group *pkg_attr_update[] = {
464
+	&group_cstate_pkg_c2,
465
+	&group_cstate_pkg_c3,
466
+	&group_cstate_pkg_c6,
467
+	&group_cstate_pkg_c7,
468
+	&group_cstate_pkg_c8,
469
+	&group_cstate_pkg_c9,
470
+	&group_cstate_pkg_c10,
471
+	NULL,
472
+};
473
+
430474 static struct pmu cstate_core_pmu = {
431475 	.attr_groups	= core_attr_groups,
476
+	.attr_update	= core_attr_update,
432477 	.name		= "cstate_core",
433478 	.task_ctx_nr	= perf_invalid_context,
434479 	.event_init	= cstate_pmu_event_init,
....@@ -437,12 +482,13 @@
437482 	.start		= cstate_pmu_event_start,
438483 	.stop		= cstate_pmu_event_stop,
439484 	.read		= cstate_pmu_event_update,
440
-	.capabilities	= PERF_PMU_CAP_NO_INTERRUPT,
485
+	.capabilities	= PERF_PMU_CAP_NO_INTERRUPT | PERF_PMU_CAP_NO_EXCLUDE,
441486 	.module		= THIS_MODULE,
442487 };
443488 
444489 static struct pmu cstate_pkg_pmu = {
445490 	.attr_groups	= pkg_attr_groups,
491
+	.attr_update	= pkg_attr_update,
446492 	.name		= "cstate_pkg",
447493 	.task_ctx_nr	= perf_invalid_context,
448494 	.event_init	= cstate_pmu_event_init,
....@@ -451,7 +497,7 @@
451497 	.start		= cstate_pmu_event_start,
452498 	.stop		= cstate_pmu_event_stop,
453499 	.read		= cstate_pmu_event_update,
454
-	.capabilities	= PERF_PMU_CAP_NO_INTERRUPT,
500
+	.capabilities	= PERF_PMU_CAP_NO_INTERRUPT | PERF_PMU_CAP_NO_EXCLUDE,
455501 	.module		= THIS_MODULE,
456502 };
457503 
....@@ -504,6 +550,19 @@
504550 				  BIT(PERF_CSTATE_PKG_C10_RES),
505551 };
506552 
553
+static const struct cstate_model icl_cstates __initconst = {
554
+	.core_events		= BIT(PERF_CSTATE_CORE_C6_RES) |
555
+				  BIT(PERF_CSTATE_CORE_C7_RES),
556
+
557
+	.pkg_events		= BIT(PERF_CSTATE_PKG_C2_RES) |
558
+				  BIT(PERF_CSTATE_PKG_C3_RES) |
559
+				  BIT(PERF_CSTATE_PKG_C6_RES) |
560
+				  BIT(PERF_CSTATE_PKG_C7_RES) |
561
+				  BIT(PERF_CSTATE_PKG_C8_RES) |
562
+				  BIT(PERF_CSTATE_PKG_C9_RES) |
563
+				  BIT(PERF_CSTATE_PKG_C10_RES),
564
+};
565
+
507566 static const struct cstate_model slm_cstates __initconst = {
508567 	.core_events		= BIT(PERF_CSTATE_CORE_C1_RES) |
509568 				  BIT(PERF_CSTATE_CORE_C6_RES),
....@@ -535,85 +594,64 @@
535594 };
536595 
537596 
538
-#define X86_CSTATES_MODEL(model, states)				\
539
-	{ X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long) &(states) }
540
-
541597 static const struct x86_cpu_id intel_cstates_match[] __initconst = {
542
-	X86_CSTATES_MODEL(INTEL_FAM6_NEHALEM,    nhm_cstates),
543
-	X86_CSTATES_MODEL(INTEL_FAM6_NEHALEM_EP, nhm_cstates),
544
-	X86_CSTATES_MODEL(INTEL_FAM6_NEHALEM_EX, nhm_cstates),
598
+	X86_MATCH_INTEL_FAM6_MODEL(NEHALEM,		&nhm_cstates),
599
+	X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_EP,		&nhm_cstates),
600
+	X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_EX,		&nhm_cstates),
545601 
546
-	X86_CSTATES_MODEL(INTEL_FAM6_WESTMERE,    nhm_cstates),
547
-	X86_CSTATES_MODEL(INTEL_FAM6_WESTMERE_EP, nhm_cstates),
548
-	X86_CSTATES_MODEL(INTEL_FAM6_WESTMERE_EX, nhm_cstates),
602
+	X86_MATCH_INTEL_FAM6_MODEL(WESTMERE,		&nhm_cstates),
603
+	X86_MATCH_INTEL_FAM6_MODEL(WESTMERE_EP,		&nhm_cstates),
604
+	X86_MATCH_INTEL_FAM6_MODEL(WESTMERE_EX,		&nhm_cstates),
549605 
550
-	X86_CSTATES_MODEL(INTEL_FAM6_SANDYBRIDGE,   snb_cstates),
551
-	X86_CSTATES_MODEL(INTEL_FAM6_SANDYBRIDGE_X, snb_cstates),
606
+	X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE,		&snb_cstates),
607
+	X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE_X,	&snb_cstates),
552608 
553
-	X86_CSTATES_MODEL(INTEL_FAM6_IVYBRIDGE,   snb_cstates),
554
-	X86_CSTATES_MODEL(INTEL_FAM6_IVYBRIDGE_X, snb_cstates),
609
+	X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE,		&snb_cstates),
610
+	X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X,		&snb_cstates),
555611 
556
-	X86_CSTATES_MODEL(INTEL_FAM6_HASWELL_CORE, snb_cstates),
557
-	X86_CSTATES_MODEL(INTEL_FAM6_HASWELL_X,	   snb_cstates),
558
-	X86_CSTATES_MODEL(INTEL_FAM6_HASWELL_GT3E, snb_cstates),
612
+	X86_MATCH_INTEL_FAM6_MODEL(HASWELL,		&snb_cstates),
613
+	X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X,		&snb_cstates),
614
+	X86_MATCH_INTEL_FAM6_MODEL(HASWELL_G,		&snb_cstates),
559615 
560
-	X86_CSTATES_MODEL(INTEL_FAM6_HASWELL_ULT, hswult_cstates),
616
+	X86_MATCH_INTEL_FAM6_MODEL(HASWELL_L,		&hswult_cstates),
561617 
562
-	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_SILVERMONT, slm_cstates),
563
-	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_SILVERMONT_X, slm_cstates),
564
-	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_AIRMONT,     slm_cstates),
618
+	X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT,	&slm_cstates),
619
+	X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_D,	&slm_cstates),
620
+	X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT,	&slm_cstates),
565621 
566
-	X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_CORE,   snb_cstates),
567
-	X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_XEON_D, snb_cstates),
568
-	X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_GT3E,   snb_cstates),
569
-	X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_X,      snb_cstates),
622
+	X86_MATCH_INTEL_FAM6_MODEL(BROADWELL,		&snb_cstates),
623
+	X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D,		&snb_cstates),
624
+	X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_G,		&snb_cstates),
625
+	X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X,		&snb_cstates),
570626 
571
-	X86_CSTATES_MODEL(INTEL_FAM6_SKYLAKE_MOBILE,  snb_cstates),
572
-	X86_CSTATES_MODEL(INTEL_FAM6_SKYLAKE_DESKTOP, snb_cstates),
573
-	X86_CSTATES_MODEL(INTEL_FAM6_SKYLAKE_X, snb_cstates),
627
+	X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L,		&snb_cstates),
628
+	X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE,		&snb_cstates),
629
+	X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X,		&snb_cstates),
574630 
575
-	X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_MOBILE,  hswult_cstates),
576
-	X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_DESKTOP, hswult_cstates),
631
+	X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L,		&hswult_cstates),
632
+	X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE,		&hswult_cstates),
633
+	X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE_L,		&hswult_cstates),
634
+	X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE,		&hswult_cstates),
577635 
578
-	X86_CSTATES_MODEL(INTEL_FAM6_CANNONLAKE_MOBILE, cnl_cstates),
636
+	X86_MATCH_INTEL_FAM6_MODEL(CANNONLAKE_L,	&cnl_cstates),
579637 
580
-	X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNL, knl_cstates),
581
-	X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNM, knl_cstates),
638
+	X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL,	&knl_cstates),
639
+	X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM,	&knl_cstates),
582640 
583
-	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT, glm_cstates),
584
-	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT_X, glm_cstates),
641
+	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT,	&glm_cstates),
642
+	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_D,	&glm_cstates),
643
+	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_PLUS,	&glm_cstates),
644
+	X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D,	&glm_cstates),
645
+	X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT,	&glm_cstates),
646
+	X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L,	&glm_cstates),
585647 
586
-	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT_PLUS, glm_cstates),
587
-
588
-	X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE_MOBILE, snb_cstates),
648
+	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L,		&icl_cstates),
649
+	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE,		&icl_cstates),
650
+	X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L,		&icl_cstates),
651
+	X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE,		&icl_cstates),
589652 	{ },
590653 };
591654 MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);
592
-
593
-/*
594
- * Probe the cstate events and insert the available one into sysfs attrs
595
- * Return false if there are no available events.
596
- */
597
-static bool __init cstate_probe_msr(const unsigned long evmsk, int max,
598
-                                   struct perf_cstate_msr *msr,
599
-                                   struct attribute **attrs)
600
-{
601
-	bool found = false;
602
-	unsigned int bit;
603
-	u64 val;
604
-
605
-	for (bit = 0; bit < max; bit++) {
606
-		if (test_bit(bit, &evmsk) && !rdmsrl_safe(msr[bit].msr, &val)) {
607
-			*attrs++ = &msr[bit].attr->attr.attr;
608
-			found = true;
609
-		} else {
610
-			msr[bit].attr = NULL;
611
-		}
612
-	}
613
-	*attrs = NULL;
614
-
615
-	return found;
616
-}
617655 
618656 static int __init cstate_probe(const struct cstate_model *cm)
619657 {
....@@ -626,13 +664,14 @@
626664 		pkg_msr[PERF_CSTATE_CORE_C6_RES].msr = MSR_KNL_CORE_C6_RESIDENCY;
627665 
628666 
629
-	has_cstate_core = cstate_probe_msr(cm->core_events,
630
-					   PERF_CSTATE_CORE_EVENT_MAX,
631
-					   core_msr, core_events_attrs);
667
+	core_msr_mask = perf_msr_probe(core_msr, PERF_CSTATE_CORE_EVENT_MAX,
668
+				       true, (void *) &cm->core_events);
632669 
633
-	has_cstate_pkg = cstate_probe_msr(cm->pkg_events,
634
-					  PERF_CSTATE_PKG_EVENT_MAX,
635
-					  pkg_msr, pkg_events_attrs);
670
+	pkg_msr_mask = perf_msr_probe(pkg_msr, PERF_CSTATE_PKG_EVENT_MAX,
671
+				      true, (void *) &cm->pkg_events);
672
+
673
+	has_cstate_core = !!core_msr_mask;
674
+	has_cstate_pkg  = !!pkg_msr_mask;
636675 
637676 	return (has_cstate_core || has_cstate_pkg) ? 0 : -ENODEV;
638677 }
....@@ -669,7 +708,13 @@
669708 	}
670709 
671710 	if (has_cstate_pkg) {
672
-		err = perf_pmu_register(&cstate_pkg_pmu, cstate_pkg_pmu.name, -1);
711
+		if (topology_max_die_per_package() > 1) {
712
+			err = perf_pmu_register(&cstate_pkg_pmu,
713
+						"cstate_die", -1);
714
+		} else {
715
+			err = perf_pmu_register(&cstate_pkg_pmu,
716
+						cstate_pkg_pmu.name, -1);
717
+		}
673718 		if (err) {
674719 			has_cstate_pkg = false;
675720 			pr_info("Failed to register cstate pkg pmu\n");