add dts config

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2023-12-06 08f87f769b595151be1afeff53e144f543faa614

 kernel/arch/x86/events/amd/iommu.c
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@@ -1,3 +1,4 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright (C) 2013 Advanced Micro Devices, Inc.
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  *
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@@ -5,10 +6,6 @@
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  * Author: Suravee Suthikulpanit <Suraveee.Suthikulpanit@amd.com>
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  *
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  * Perf: amd_iommu - AMD IOMMU Performance Counter PMU implementation
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  */
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 #define pr_fmt(fmt)	"perf/amd_iommu: " fmt
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@@ -20,8 +17,6 @@
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 #include "../perf_event.h"
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 #include "iommu.h"
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-
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-#define COUNTER_SHIFT		16
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 /* iommu pmu conf masks */
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 #define GET_CSOURCE(x)     ((x)->conf & 0xFFULL)
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@@ -223,11 +218,6 @@
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 	if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
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 		return -EINVAL;
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-	/* IOMMU counters do not have usr/os/guest/host bits */
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-	if (event->attr.exclude_user || event->attr.exclude_kernel ||
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-	    event->attr.exclude_host || event->attr.exclude_guest)
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-		return -EINVAL;
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-
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 	if (event->cpu < 0)
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 		return -EINVAL;
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@@ -293,22 +283,31 @@
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 	WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
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 	hwc->state = 0;
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+	/*
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+	 * To account for power-gating, which prevents write to
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+	 * the counter, we need to enable the counter
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+	 * before setting up counter register.
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+	 */
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+	perf_iommu_enable_event(event);
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+
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 	if (flags & PERF_EF_RELOAD) {
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-		u64 prev_raw_count = local64_read(&hwc->prev_count);
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+		u64 count = 0;
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 		struct amd_iommu *iommu = perf_event_2_iommu(event);
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+		/*
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+		 * Since the IOMMU PMU only support counting mode,
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+		 * the counter always start with value zero.
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+		 */
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 		amd_iommu_pc_set_reg(iommu, hwc->iommu_bank, hwc->iommu_cntr,
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-				     IOMMU_PC_COUNTER_REG, &prev_raw_count);
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+				     IOMMU_PC_COUNTER_REG, &count);
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 	}
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-	perf_iommu_enable_event(event);
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 	perf_event_update_userpage(event);
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-
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 }
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 static void perf_iommu_read(struct perf_event *event)
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 {
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-	u64 count, prev, delta;
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+	u64 count;
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 	struct hw_perf_event *hwc = &event->hw;
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 	struct amd_iommu *iommu = perf_event_2_iommu(event);
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@@ -319,14 +318,11 @@
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 	/* IOMMU pc counter register is only 48 bits */
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 	count &= GENMASK_ULL(47, 0);
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-	prev = local64_read(&hwc->prev_count);
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-	if (local64_cmpxchg(&hwc->prev_count, prev, count) != prev)
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-		return;
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-
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-	/* Handle 48-bit counter overflow */
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-	delta = (count << COUNTER_SHIFT) - (prev << COUNTER_SHIFT);
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-	delta >>= COUNTER_SHIFT;
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-	local64_add(delta, &event->count);
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+	/*
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+	 * Since the counter always start with value zero,
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+	 * simply just accumulate the count for the event.
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+	 */
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+	local64_add(count, &event->count);
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 }
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 static void perf_iommu_stop(struct perf_event *event, int flags)
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@@ -336,15 +332,16 @@
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 	if (hwc->state & PERF_HES_UPTODATE)
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 		return;
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+	/*
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+	 * To account for power-gating, in which reading the counter would
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+	 * return zero, we need to read the register before disabling.
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+	 */
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+	perf_iommu_read(event);
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+	hwc->state |= PERF_HES_UPTODATE;
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+
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 	perf_iommu_disable_event(event);
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 	WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
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 	hwc->state |= PERF_HES_STOPPED;
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-
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-	if (hwc->state & PERF_HES_UPTODATE)
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-		return;
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-
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-	perf_iommu_read(event);
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-	hwc->state |= PERF_HES_UPTODATE;
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 }
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 static int perf_iommu_add(struct perf_event *event, int flags)
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@@ -398,7 +395,7 @@
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 	return 0;
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 }
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-const struct attribute_group *amd_iommu_attr_groups[] = {
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+static const struct attribute_group *amd_iommu_attr_groups[] = {
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 	&amd_iommu_format_group,
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 	&amd_iommu_cpumask_group,
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 	&amd_iommu_events_group,
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@@ -414,6 +411,7 @@
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 	.read		= perf_iommu_read,
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 	.task_ctx_nr	= perf_invalid_context,
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 	.attr_groups	= amd_iommu_attr_groups,
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+	.capabilities	= PERF_PMU_CAP_NO_EXCLUDE,
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 };
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 static __init int init_one_iommu(unsigned int idx)