add dts config

hc

2023-12-06 08f87f769b595151be1afeff53e144f543faa614

 kernel/arch/powerpc/sysdev/xive/native.c
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@@ -1,10 +1,6 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later
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 /*
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  * Copyright 2016,2017 IBM Corporation.
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- *
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- * This program is free software; you can redistribute it and/or
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- * modify it under the terms of the GNU General Public License
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- * as published by the Free Software Foundation; either version
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- * 2 of the License, or (at your option) any later version.
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  */
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5
 
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 #define pr_fmt(fmt) "xive: " fmt
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@@ -24,6 +20,7 @@
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20
 #include <linux/mm.h>
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 #include <linux/kmemleak.h>
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22
 
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+#include <asm/machdep.h>
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 #include <asm/prom.h>
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 #include <asm/io.h>
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 #include <asm/smp.h>
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@@ -116,6 +113,20 @@
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 }
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 EXPORT_SYMBOL_GPL(xive_native_configure_irq);
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115
 
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+static int xive_native_get_irq_config(u32 hw_irq, u32 *target, u8 *prio,
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+				      u32 *sw_irq)
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+{
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+	s64 rc;
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+	__be64 vp;
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+	__be32 lirq;
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+
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+	rc = opal_xive_get_irq_config(hw_irq, &vp, prio, &lirq);
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+
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+	*target = be64_to_cpu(vp);
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+	*sw_irq = be32_to_cpu(lirq);
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+
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+	return rc == 0 ? 0 : -ENXIO;
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+}
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 /* This can be called multiple time to change a queue configuration */
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 int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio,
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@@ -250,20 +261,11 @@
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 #ifdef CONFIG_SMP
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 static int xive_native_get_ipi(unsigned int cpu, struct xive_cpu *xc)
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 {
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-	struct device_node *np;
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-	unsigned int chip_id;
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 	s64 irq;
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-
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-	/* Find the chip ID */
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-	np = of_get_cpu_node(cpu, NULL);
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-	if (np) {
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-		if (of_property_read_u32(np, "ibm,chip-id", &chip_id) < 0)
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-			chip_id = 0;
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-	}
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 	/* Allocate an IPI and populate info about it */
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 	for (;;) {
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-		irq = opal_xive_allocate_irq(chip_id);
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+		irq = opal_xive_allocate_irq(xc->chip_id);
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 		if (irq == OPAL_BUSY) {
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 			msleep(OPAL_BUSY_DELAY_MS);
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 			continue;
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@@ -279,12 +281,12 @@
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 }
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 #endif /* CONFIG_SMP */
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283
 
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-u32 xive_native_alloc_irq(void)
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+u32 xive_native_alloc_irq_on_chip(u32 chip_id)
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 {
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 	s64 rc;
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 	for (;;) {
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-		rc = opal_xive_allocate_irq(OPAL_XIVE_ANY_CHIP);
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+		rc = opal_xive_allocate_irq(chip_id);
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 		if (rc != OPAL_BUSY)
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 			break;
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 		msleep(OPAL_BUSY_DELAY_MS);
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@@ -293,7 +295,7 @@
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 		return 0;
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 	return rc;
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 }
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-EXPORT_SYMBOL_GPL(xive_native_alloc_irq);
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+EXPORT_SYMBOL_GPL(xive_native_alloc_irq_on_chip);
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 void xive_native_free_irq(u32 irq)
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 {
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@@ -458,9 +460,16 @@
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 }
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 EXPORT_SYMBOL_GPL(xive_native_sync_source);
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462
 
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+void xive_native_sync_queue(u32 hw_irq)
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+{
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+	opal_xive_sync(XIVE_SYNC_QUEUE, hw_irq);
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+}
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+EXPORT_SYMBOL_GPL(xive_native_sync_queue);
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+
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 static const struct xive_ops xive_native_ops = {
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 	.populate_irq_data	= xive_native_populate_irq_data,
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 	.configure_irq		= xive_native_configure_irq,
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+	.get_irq_config		= xive_native_get_irq_config,
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 	.setup_queue		= xive_native_setup_queue,
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 	.cleanup_queue		= xive_native_cleanup_queue,
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 	.match			= xive_native_match,
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@@ -536,6 +545,9 @@
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 }
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 EXPORT_SYMBOL_GPL(xive_native_default_eq_shift);
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547
 
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+unsigned long xive_tima_os;
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+EXPORT_SYMBOL_GPL(xive_tima_os);
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+
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 bool __init xive_native_init(void)
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 {
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 	struct device_node *np;
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@@ -587,6 +599,14 @@
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 	/* Configure Thread Management areas for KVM */
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 	for_each_possible_cpu(cpu)
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 		kvmppc_set_xive_tima(cpu, r.start, tima);
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+
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+	/* Resource 2 is OS window */
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+	if (of_address_to_resource(np, 2, &r)) {
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+		pr_err("Failed to get thread mgmnt area resource\n");
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+		return false;
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+	}
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+
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+	xive_tima_os = r.start;
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610
 
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 	/* Grab size of provisionning pages */
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 	xive_parse_provisioning(np);
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@@ -733,3 +753,105 @@
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 	return xive_has_single_esc;
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 }
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 EXPORT_SYMBOL_GPL(xive_native_has_single_escalation);
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+
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+int xive_native_get_queue_info(u32 vp_id, u32 prio,
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+			       u64 *out_qpage,
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+			       u64 *out_qsize,
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+			       u64 *out_qeoi_page,
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+			       u32 *out_escalate_irq,
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+			       u64 *out_qflags)
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+{
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+	__be64 qpage;
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+	__be64 qsize;
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+	__be64 qeoi_page;
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+	__be32 escalate_irq;
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+	__be64 qflags;
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+	s64 rc;
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+
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+	rc = opal_xive_get_queue_info(vp_id, prio, &qpage, &qsize,
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+				      &qeoi_page, &escalate_irq, &qflags);
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+	if (rc) {
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+		pr_err("OPAL failed to get queue info for VCPU %d/%d : %lld\n",
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+		       vp_id, prio, rc);
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+		return -EIO;
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+	}
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+
779
+	if (out_qpage)
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+		*out_qpage = be64_to_cpu(qpage);
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+	if (out_qsize)
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+		*out_qsize = be32_to_cpu(qsize);
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+	if (out_qeoi_page)
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+		*out_qeoi_page = be64_to_cpu(qeoi_page);
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+	if (out_escalate_irq)
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+		*out_escalate_irq = be32_to_cpu(escalate_irq);
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+	if (out_qflags)
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+		*out_qflags = be64_to_cpu(qflags);
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+
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+	return 0;
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+}
792
+EXPORT_SYMBOL_GPL(xive_native_get_queue_info);
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+
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+int xive_native_get_queue_state(u32 vp_id, u32 prio, u32 *qtoggle, u32 *qindex)
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+{
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+	__be32 opal_qtoggle;
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+	__be32 opal_qindex;
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+	s64 rc;
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+
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+	rc = opal_xive_get_queue_state(vp_id, prio, &opal_qtoggle,
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+				       &opal_qindex);
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+	if (rc) {
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+		pr_err("OPAL failed to get queue state for VCPU %d/%d : %lld\n",
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+		       vp_id, prio, rc);
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+		return -EIO;
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+	}
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+
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+	if (qtoggle)
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+		*qtoggle = be32_to_cpu(opal_qtoggle);
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+	if (qindex)
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+		*qindex = be32_to_cpu(opal_qindex);
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+
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+	return 0;
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+}
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+EXPORT_SYMBOL_GPL(xive_native_get_queue_state);
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+
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+int xive_native_set_queue_state(u32 vp_id, u32 prio, u32 qtoggle, u32 qindex)
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+{
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+	s64 rc;
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+
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+	rc = opal_xive_set_queue_state(vp_id, prio, qtoggle, qindex);
822
+	if (rc) {
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+		pr_err("OPAL failed to set queue state for VCPU %d/%d : %lld\n",
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+		       vp_id, prio, rc);
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+		return -EIO;
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+	}
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+
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+	return 0;
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+}
830
+EXPORT_SYMBOL_GPL(xive_native_set_queue_state);
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+
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+bool xive_native_has_queue_state_support(void)
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+{
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+	return opal_check_token(OPAL_XIVE_GET_QUEUE_STATE) &&
835
+		opal_check_token(OPAL_XIVE_SET_QUEUE_STATE);
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+}
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+EXPORT_SYMBOL_GPL(xive_native_has_queue_state_support);
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+
839
+int xive_native_get_vp_state(u32 vp_id, u64 *out_state)
840
+{
841
+	__be64 state;
842
+	s64 rc;
843
+
844
+	rc = opal_xive_get_vp_state(vp_id, &state);
845
+	if (rc) {
846
+		pr_err("OPAL failed to get vp state for VCPU %d : %lld\n",
847
+		       vp_id, rc);
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+		return -EIO;
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+	}
850
+
851
+	if (out_state)
852
+		*out_state = be64_to_cpu(state);
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+	return 0;
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+}
855
+EXPORT_SYMBOL_GPL(xive_native_get_vp_state);
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+
857
+machine_arch_initcall(powernv, xive_core_debug_init);