add dts config

hc

2023-12-06 08f87f769b595151be1afeff53e144f543faa614

 kernel/arch/powerpc/platforms/85xx/smp.c
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@@ -1,13 +1,9 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later
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 /*
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  * Author: Andy Fleming <afleming@freescale.com>
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  * 	   Kumar Gala <galak@kernel.crashing.org>
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  *
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  * Copyright 2006-2008, 2011-2012, 2015 Freescale Semiconductor Inc.
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- *
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- * This program is free software; you can redistribute  it and/or modify it
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- * under  the terms of  the GNU General  Public License as published by the
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- * Free Software Foundation;  either version 2 of the  License, or (at your
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- * option) any later version.
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  */
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 #include <linux/stddef.h>
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@@ -20,9 +16,9 @@
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 #include <linux/highmem.h>
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 #include <linux/cpu.h>
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 #include <linux/fsl/guts.h>
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+#include <linux/pgtable.h>
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 #include <asm/machdep.h>
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-#include <asm/pgtable.h>
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 #include <asm/page.h>
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 #include <asm/mpic.h>
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 #include <asm/cacheflush.h>
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@@ -44,7 +40,6 @@
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 	u32	pir;
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 };
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-#ifdef CONFIG_HOTPLUG_CPU
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 static u64 timebase;
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 static int tb_req;
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 static int tb_valid;
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@@ -116,7 +111,8 @@
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 	local_irq_restore(flags);
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 }
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-static void smp_85xx_mach_cpu_die(void)
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+#ifdef CONFIG_HOTPLUG_CPU
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+static void smp_85xx_cpu_offline_self(void)
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 {
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 	unsigned int cpu = smp_processor_id();
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@@ -216,15 +212,15 @@
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 	/* Map the spin table */
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 	if (ioremappable)
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-		spin_table = ioremap_prot(*cpu_rel_addr,
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-			sizeof(struct epapr_spin_table), _PAGE_COHERENT);
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+		spin_table = ioremap_coherent(*cpu_rel_addr,
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+					      sizeof(struct epapr_spin_table));
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 	else
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 		spin_table = phys_to_virt(*cpu_rel_addr);
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 	local_irq_save(flags);
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 	hard_irq_disable();
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-	if (qoriq_pm_ops)
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+	if (qoriq_pm_ops && qoriq_pm_ops->cpu_up_prepare)
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 		qoriq_pm_ops->cpu_up_prepare(cpu);
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 	/* if cpu is not spinning, reset it */
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@@ -256,6 +252,15 @@
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 	out_be64((u64 *)(&spin_table->addr_h),
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 		__pa(ppc_function_entry(generic_secondary_smp_init)));
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 #else
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+#ifdef CONFIG_PHYS_ADDR_T_64BIT
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+	/*
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+	 * We need also to write addr_h to spin table for systems
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+	 * in which their physical memory start address was configured
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+	 * to above 4G, otherwise the secondary core can not get
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+	 * correct entry to start from.
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+	 */
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+	out_be32(&spin_table->addr_h, __pa(__early_start) >> 32);
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+#endif
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 	out_be32(&spin_table->addr_l, __pa(__early_start));
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 #endif
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 	flush_spin_table(spin_table);
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@@ -287,7 +292,7 @@
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 		booting_thread_hwid = cpu_thread_in_core(nr);
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 		primary = cpu_first_thread_sibling(nr);
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-		if (qoriq_pm_ops)
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+		if (qoriq_pm_ops && qoriq_pm_ops->cpu_up_prepare)
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 			qoriq_pm_ops->cpu_up_prepare(nr);
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 		/*
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@@ -490,21 +495,21 @@
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 		smp_85xx_ops.probe = NULL;
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 	}
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-#ifdef CONFIG_HOTPLUG_CPU
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 #ifdef CONFIG_FSL_CORENET_RCPM
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+	/* Assign a value to qoriq_pm_ops on PPC_E500MC */
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 	fsl_rcpm_init();
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-#endif
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-
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-#ifdef CONFIG_FSL_PMC
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+#else
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+	/* Assign a value to qoriq_pm_ops on !PPC_E500MC */
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 	mpc85xx_setup_pmc();
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 #endif
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 	if (qoriq_pm_ops) {
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 		smp_85xx_ops.give_timebase = mpc85xx_give_timebase;
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 		smp_85xx_ops.take_timebase = mpc85xx_take_timebase;
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-		ppc_md.cpu_die = smp_85xx_mach_cpu_die;
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+#ifdef CONFIG_HOTPLUG_CPU
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+		smp_85xx_ops.cpu_offline_self = smp_85xx_cpu_offline_self;
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 		smp_85xx_ops.cpu_die = qoriq_cpu_kill;
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-	}
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 #endif
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+	}
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 	smp_ops = &smp_85xx_ops;
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 #ifdef CONFIG_KEXEC_CORE