| .. | .. |
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| 39 | 39 | d-cache-size = <32768>; |
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| 40 | 40 | dcr-controller; |
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| 41 | 41 | dcr-access-method = "native"; |
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| 42 | | - status = "ok"; |
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| 42 | + status = "okay"; |
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| 43 | 43 | }; |
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| 44 | 44 | cpu@1 { |
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| 45 | 45 | device_type = "cpu"; |
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| .. | .. |
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| 122 | 122 | }; |
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| 123 | 123 | }; |
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| 124 | 124 | |
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| 125 | | - PCIE0: pciex@10100000000 { // 4xGBIF1 |
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| 125 | + PCIE0: pcie@10100000000 { // 4xGBIF1 |
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| 126 | 126 | device_type = "pci"; |
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| 127 | 127 | #interrupt-cells = <1>; |
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| 128 | 128 | #size-cells = <2>; |
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| .. | .. |
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| 160 | 160 | 0x0 0x0 0x0 0x4 &MPIC 49 0x2 /* int D */>; |
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| 161 | 161 | }; |
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| 162 | 162 | |
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| 163 | | - PCIE1: pciex@30100000000 { // 4xGBIF0 |
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| 163 | + PCIE1: pcie@30100000000 { // 4xGBIF0 |
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| 164 | 164 | device_type = "pci"; |
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| 165 | 165 | #interrupt-cells = <1>; |
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| 166 | 166 | #size-cells = <2>; |
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| .. | .. |
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| 197 | 197 | 0x0 0x0 0x0 0x4 &MPIC 41 0x2 /* int D */>; |
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| 198 | 198 | }; |
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| 199 | 199 | |
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| 200 | | - PCIE2: pciex@38100000000 { // 2xGBIF0 |
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| 200 | + PCIE2: pcie@38100000000 { // 2xGBIF0 |
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| 201 | 201 | device_type = "pci"; |
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| 202 | 202 | #interrupt-cells = <1>; |
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| 203 | 203 | #size-cells = <2>; |
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