| .. | .. |
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| 40 | 40 | d-cache-size = <32768>; |
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| 41 | 41 | dcr-controller; |
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| 42 | 42 | dcr-access-method = "native"; |
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| 43 | | - status = "ok"; |
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| 43 | + status = "okay"; |
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| 44 | 44 | }; |
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| 45 | 45 | cpu@1 { |
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| 46 | 46 | device_type = "cpu"; |
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| .. | .. |
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| 248 | 248 | }; |
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| 249 | 249 | }; |
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| 250 | 250 | |
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| 251 | | - PCIE0: pciex@10100000000 { |
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| 251 | + PCIE0: pcie@10100000000 { |
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| 252 | 252 | device_type = "pci"; |
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| 253 | 253 | #interrupt-cells = <1>; |
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| 254 | 254 | #size-cells = <2>; |
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| .. | .. |
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| 288 | 288 | 0x0 0x0 0x0 0x4 &MPIC 48 0x2 /* int D */>; |
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| 289 | 289 | }; |
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| 290 | 290 | |
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| 291 | | - PCIE1: pciex@20100000000 { |
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| 291 | + PCIE1: pcie@20100000000 { |
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| 292 | 292 | device_type = "pci"; |
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| 293 | 293 | #interrupt-cells = <1>; |
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| 294 | 294 | #size-cells = <2>; |
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| .. | .. |
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| 328 | 328 | 0x0 0x0 0x0 0x4 &MPIC 56 0x2 /* int D */>; |
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| 329 | 329 | }; |
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| 330 | 330 | |
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| 331 | | - PCIE2: pciex@18100000000 { |
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| 331 | + PCIE2: pcie@18100000000 { |
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| 332 | 332 | device_type = "pci"; |
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| 333 | 333 | #interrupt-cells = <1>; |
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| 334 | 334 | #size-cells = <2>; |
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| .. | .. |
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| 368 | 368 | 0x0 0x0 0x0 0x4 &MPIC 64 0x2 /* int D */>; |
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| 369 | 369 | }; |
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| 370 | 370 | |
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| 371 | | - PCIE3: pciex@28100000000 { |
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| 371 | + PCIE3: pcie@28100000000 { |
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| 372 | 372 | device_type = "pci"; |
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| 373 | 373 | #interrupt-cells = <1>; |
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| 374 | 374 | #size-cells = <2>; |
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