~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,23 +1,14 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
1	2	/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
2		- *
3		- * This program is free software; you can redistribute it and/or modify
4		- * it under the terms of the GNU General Public License version 2 and
5		- * only version 2 as published by the Free Software Foundation.
6		- *
7		- * This program is distributed in the hope that it will be useful,
8		- * but WITHOUT ANY WARRANTY; without even the implied warranty of
9		- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10		- * GNU General Public License for more details.
11	3	*/
12	4
13	5	#include <dt-bindings/interrupt-controller/arm-gic.h>
14	6	#include <dt-bindings/clock/qcom,gcc-msm8996.h>
15	7	#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
16	8	#include <dt-bindings/clock/qcom,rpmcc.h>
	9	+#include <dt-bindings/soc/qcom,apr.h>
17	10
18	11	/ {
19		- model = "Qualcomm Technologies, Inc. MSM8996";
20		-
21	12	interrupt-parent = <&intc>;
22	13
23	14	#address-cells = <2>;
..	..	@@ -25,10 +16,132 @@
25	16
26	17	chosen { };
27	18
	19	+ clocks {
	20	+ xo_board: xo-board {
	21	+ compatible = "fixed-clock";
	22	+ #clock-cells = <0>;
	23	+ clock-frequency = <19200000>;
	24	+ clock-output-names = "xo_board";
	25	+ };
	26	+
	27	+ sleep_clk: sleep-clk {
	28	+ compatible = "fixed-clock";
	29	+ #clock-cells = <0>;
	30	+ clock-frequency = <32764>;
	31	+ clock-output-names = "sleep_clk";
	32	+ };
	33	+ };
	34	+
	35	+ cpus {
	36	+ #address-cells = <2>;
	37	+ #size-cells = <0>;
	38	+
	39	+ CPU0: cpu@0 {
	40	+ device_type = "cpu";
	41	+ compatible = "qcom,kryo";
	42	+ reg = <0x0 0x0>;
	43	+ enable-method = "psci";
	44	+ cpu-idle-states = <&CPU_SLEEP_0>;
	45	+ capacity-dmips-mhz = <1024>;
	46	+ next-level-cache = <&L2_0>;
	47	+ L2_0: l2-cache {
	48	+ compatible = "cache";
	49	+ cache-level = <2>;
	50	+ };
	51	+ };
	52	+
	53	+ CPU1: cpu@1 {
	54	+ device_type = "cpu";
	55	+ compatible = "qcom,kryo";
	56	+ reg = <0x0 0x1>;
	57	+ enable-method = "psci";
	58	+ cpu-idle-states = <&CPU_SLEEP_0>;
	59	+ capacity-dmips-mhz = <1024>;
	60	+ next-level-cache = <&L2_0>;
	61	+ };
	62	+
	63	+ CPU2: cpu@100 {
	64	+ device_type = "cpu";
	65	+ compatible = "qcom,kryo";
	66	+ reg = <0x0 0x100>;
	67	+ enable-method = "psci";
	68	+ cpu-idle-states = <&CPU_SLEEP_0>;
	69	+ capacity-dmips-mhz = <1024>;
	70	+ next-level-cache = <&L2_1>;
	71	+ L2_1: l2-cache {
	72	+ compatible = "cache";
	73	+ cache-level = <2>;
	74	+ };
	75	+ };
	76	+
	77	+ CPU3: cpu@101 {
	78	+ device_type = "cpu";
	79	+ compatible = "qcom,kryo";
	80	+ reg = <0x0 0x101>;
	81	+ enable-method = "psci";
	82	+ cpu-idle-states = <&CPU_SLEEP_0>;
	83	+ capacity-dmips-mhz = <1024>;
	84	+ next-level-cache = <&L2_1>;
	85	+ };
	86	+
	87	+ cpu-map {
	88	+ cluster0 {
	89	+ core0 {
	90	+ cpu = <&CPU0>;
	91	+ };
	92	+
	93	+ core1 {
	94	+ cpu = <&CPU1>;
	95	+ };
	96	+ };
	97	+
	98	+ cluster1 {
	99	+ core0 {
	100	+ cpu = <&CPU2>;
	101	+ };
	102	+
	103	+ core1 {
	104	+ cpu = <&CPU3>;
	105	+ };
	106	+ };
	107	+ };
	108	+
	109	+ idle-states {
	110	+ entry-method = "psci";
	111	+
	112	+ CPU_SLEEP_0: cpu-sleep-0 {
	113	+ compatible = "arm,idle-state";
	114	+ idle-state-name = "standalone-power-collapse";
	115	+ arm,psci-suspend-param = <0x00000004>;
	116	+ entry-latency-us = <130>;
	117	+ exit-latency-us = <80>;
	118	+ min-residency-us = <300>;
	119	+ };
	120	+ };
	121	+ };
	122	+
	123	+ firmware {
	124	+ scm {
	125	+ compatible = "qcom,scm-msm8996";
	126	+ qcom,dload-mode = <&tcsr 0x13000>;
	127	+ };
	128	+ };
	129	+
	130	+ tcsr_mutex: hwlock {
	131	+ compatible = "qcom,tcsr-mutex";
	132	+ syscon = <&tcsr_mutex_regs 0 0x1000>;
	133	+ #hwlock-cells = <1>;
	134	+ };
	135	+
28	136	memory {
29	137	device_type = "memory";
30	138	/* We expect the bootloader to fill in the reg */
31	139	reg = <0 0 0 0>;
	140	+ };
	141	+
	142	+ psci {
	143	+ compatible = "arm,psci-1.0";
	144	+ method = "smc";
32	145	};
33	146
34	147	reserved-memory {
..	..	@@ -86,208 +199,12 @@
86	199	qcom,client-id = <1>;
87	200	qcom,vmid = <15>;
88	201	};
89		- };
90	202
91		- cpus {
92		- #address-cells = <2>;
93		- #size-cells = <0>;
94		-
95		- CPU0: cpu@0 {
96		- device_type = "cpu";
97		- compatible = "qcom,kryo";
98		- reg = <0x0 0x0>;
99		- enable-method = "psci";
100		- next-level-cache = <&L2_0>;
101		- L2_0: l2-cache {
102		- compatible = "cache";
103		- cache-level = <2>;
104		- };
	203	+ zap_shader_region: gpu@8f200000 {
	204	+ compatible = "shared-dma-pool";
	205	+ reg = <0x0 0x90b00000 0x0 0xa00000>;
	206	+ no-map;
105	207	};
106		-
107		- CPU1: cpu@1 {
108		- device_type = "cpu";
109		- compatible = "qcom,kryo";
110		- reg = <0x0 0x1>;
111		- enable-method = "psci";
112		- next-level-cache = <&L2_0>;
113		- };
114		-
115		- CPU2: cpu@100 {
116		- device_type = "cpu";
117		- compatible = "qcom,kryo";
118		- reg = <0x0 0x100>;
119		- enable-method = "psci";
120		- next-level-cache = <&L2_1>;
121		- L2_1: l2-cache {
122		- compatible = "cache";
123		- cache-level = <2>;
124		- };
125		- };
126		-
127		- CPU3: cpu@101 {
128		- device_type = "cpu";
129		- compatible = "qcom,kryo";
130		- reg = <0x0 0x101>;
131		- enable-method = "psci";
132		- next-level-cache = <&L2_1>;
133		- };
134		-
135		- cpu-map {
136		- cluster0 {
137		- core0 {
138		- cpu = <&CPU0>;
139		- };
140		-
141		- core1 {
142		- cpu = <&CPU1>;
143		- };
144		- };
145		-
146		- cluster1 {
147		- core0 {
148		- cpu = <&CPU2>;
149		- };
150		-
151		- core1 {
152		- cpu = <&CPU3>;
153		- };
154		- };
155		- };
156		- };
157		-
158		- thermal-zones {
159		- cpu-thermal0 {
160		- polling-delay-passive = <250>;
161		- polling-delay = <1000>;
162		-
163		- thermal-sensors = <&tsens0 3>;
164		-
165		- trips {
166		- cpu_alert0: trip0 {
167		- temperature = <75000>;
168		- hysteresis = <2000>;
169		- type = "passive";
170		- };
171		-
172		- cpu_crit0: trip1 {
173		- temperature = <110000>;
174		- hysteresis = <2000>;
175		- type = "critical";
176		- };
177		- };
178		- };
179		-
180		- cpu-thermal1 {
181		- polling-delay-passive = <250>;
182		- polling-delay = <1000>;
183		-
184		- thermal-sensors = <&tsens0 5>;
185		-
186		- trips {
187		- cpu_alert1: trip0 {
188		- temperature = <75000>;
189		- hysteresis = <2000>;
190		- type = "passive";
191		- };
192		-
193		- cpu_crit1: trip1 {
194		- temperature = <110000>;
195		- hysteresis = <2000>;
196		- type = "critical";
197		- };
198		- };
199		- };
200		-
201		- cpu-thermal2 {
202		- polling-delay-passive = <250>;
203		- polling-delay = <1000>;
204		-
205		- thermal-sensors = <&tsens0 8>;
206		-
207		- trips {
208		- cpu_alert2: trip0 {
209		- temperature = <75000>;
210		- hysteresis = <2000>;
211		- type = "passive";
212		- };
213		-
214		- cpu_crit2: trip1 {
215		- temperature = <110000>;
216		- hysteresis = <2000>;
217		- type = "critical";
218		- };
219		- };
220		- };
221		-
222		- cpu-thermal3 {
223		- polling-delay-passive = <250>;
224		- polling-delay = <1000>;
225		-
226		- thermal-sensors = <&tsens0 10>;
227		-
228		- trips {
229		- cpu_alert3: trip0 {
230		- temperature = <75000>;
231		- hysteresis = <2000>;
232		- type = "passive";
233		- };
234		-
235		- cpu_crit3: trip1 {
236		- temperature = <110000>;
237		- hysteresis = <2000>;
238		- type = "critical";
239		- };
240		- };
241		- };
242		- };
243		-
244		- timer {
245		- compatible = "arm,armv8-timer";
246		- interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
247		- <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
248		- <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
249		- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
250		- };
251		-
252		- clocks {
253		- xo_board: xo_board {
254		- compatible = "fixed-clock";
255		- #clock-cells = <0>;
256		- clock-frequency = <19200000>;
257		- clock-output-names = "xo_board";
258		- };
259		-
260		- sleep_clk: sleep_clk {
261		- compatible = "fixed-clock";
262		- #clock-cells = <0>;
263		- clock-frequency = <32764>;
264		- clock-output-names = "sleep_clk";
265		- };
266		- };
267		-
268		- psci {
269		- compatible = "arm,psci-1.0";
270		- method = "smc";
271		- };
272		-
273		- firmware {
274		- scm {
275		- compatible = "qcom,scm-msm8996";
276		-
277		- qcom,dload-mode = <&tcsr 0x13000>;
278		- };
279		- };
280		-
281		- tcsr_mutex: hwlock {
282		- compatible = "qcom,tcsr-mutex";
283		- syscon = <&tcsr_mutex_regs 0 0x1000>;
284		- #hwlock-cells = <1>;
285		- };
286		-
287		- smem {
288		- compatible = "qcom,smem";
289		- memory-region = <&smem_mem>;
290		- hwlocks = <&tcsr_mutex 3>;
291	208	};
292	209
293	210	rpm-glink {
..	..	@@ -299,7 +216,7 @@
299	216
300	217	mboxes = <&apcs_glb 0>;
301	218
302		- rpm_requests {
	219	+ rpm_requests: rpm-requests {
303	220	compatible = "qcom,rpm-msm8996";
304	221	qcom,glink-channels = "rpm_requests";
305	222
..	..	@@ -308,56 +225,116 @@
308	225	#clock-cells = <1>;
309	226	};
310	227
311		- pm8994-regulators {
312		- compatible = "qcom,rpm-pm8994-regulators";
	228	+ rpmpd: power-controller {
	229	+ compatible = "qcom,msm8996-rpmpd";
	230	+ #power-domain-cells = <1>;
	231	+ operating-points-v2 = <&rpmpd_opp_table>;
313	232
314		- pm8994_s1: s1 {};
315		- pm8994_s2: s2 {};
316		- pm8994_s3: s3 {};
317		- pm8994_s4: s4 {};
318		- pm8994_s5: s5 {};
319		- pm8994_s6: s6 {};
320		- pm8994_s7: s7 {};
321		- pm8994_s8: s8 {};
322		- pm8994_s9: s9 {};
323		- pm8994_s10: s10 {};
324		- pm8994_s11: s11 {};
325		- pm8994_s12: s12 {};
	233	+ rpmpd_opp_table: opp-table {
	234	+ compatible = "operating-points-v2";
326	235
327		- pm8994_l1: l1 {};
328		- pm8994_l2: l2 {};
329		- pm8994_l3: l3 {};
330		- pm8994_l4: l4 {};
331		- pm8994_l5: l5 {};
332		- pm8994_l6: l6 {};
333		- pm8994_l7: l7 {};
334		- pm8994_l8: l8 {};
335		- pm8994_l9: l9 {};
336		- pm8994_l10: l10 {};
337		- pm8994_l11: l11 {};
338		- pm8994_l12: l12 {};
339		- pm8994_l13: l13 {};
340		- pm8994_l14: l14 {};
341		- pm8994_l15: l15 {};
342		- pm8994_l16: l16 {};
343		- pm8994_l17: l17 {};
344		- pm8994_l18: l18 {};
345		- pm8994_l19: l19 {};
346		- pm8994_l20: l20 {};
347		- pm8994_l21: l21 {};
348		- pm8994_l22: l22 {};
349		- pm8994_l23: l23 {};
350		- pm8994_l24: l24 {};
351		- pm8994_l25: l25 {};
352		- pm8994_l26: l26 {};
353		- pm8994_l27: l27 {};
354		- pm8994_l28: l28 {};
355		- pm8994_l29: l29 {};
356		- pm8994_l30: l30 {};
357		- pm8994_l31: l31 {};
358		- pm8994_l32: l32 {};
	236	+ rpmpd_opp1: opp1 {
	237	+ opp-level = <1>;
	238	+ };
	239	+
	240	+ rpmpd_opp2: opp2 {
	241	+ opp-level = <2>;
	242	+ };
	243	+
	244	+ rpmpd_opp3: opp3 {
	245	+ opp-level = <3>;
	246	+ };
	247	+
	248	+ rpmpd_opp4: opp4 {
	249	+ opp-level = <4>;
	250	+ };
	251	+
	252	+ rpmpd_opp5: opp5 {
	253	+ opp-level = <5>;
	254	+ };
	255	+
	256	+ rpmpd_opp6: opp6 {
	257	+ opp-level = <6>;
	258	+ };
	259	+ };
359	260	};
	261	+ };
	262	+ };
360	263
	264	+ smem {
	265	+ compatible = "qcom,smem";
	266	+ memory-region = <&smem_mem>;
	267	+ hwlocks = <&tcsr_mutex 3>;
	268	+ };
	269	+
	270	+ smp2p-adsp {
	271	+ compatible = "qcom,smp2p";
	272	+ qcom,smem = <443>, <429>;
	273	+
	274	+ interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
	275	+
	276	+ mboxes = <&apcs_glb 10>;
	277	+
	278	+ qcom,local-pid = <0>;
	279	+ qcom,remote-pid = <2>;
	280	+
	281	+ smp2p_adsp_out: master-kernel {
	282	+ qcom,entry-name = "master-kernel";
	283	+ #qcom,smem-state-cells = <1>;
	284	+ };
	285	+
	286	+ smp2p_adsp_in: slave-kernel {
	287	+ qcom,entry-name = "slave-kernel";
	288	+
	289	+ interrupt-controller;
	290	+ #interrupt-cells = <2>;
	291	+ };
	292	+ };
	293	+
	294	+ smp2p-modem {
	295	+ compatible = "qcom,smp2p";
	296	+ qcom,smem = <435>, <428>;
	297	+
	298	+ interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
	299	+
	300	+ mboxes = <&apcs_glb 14>;
	301	+
	302	+ qcom,local-pid = <0>;
	303	+ qcom,remote-pid = <1>;
	304	+
	305	+ modem_smp2p_out: master-kernel {
	306	+ qcom,entry-name = "master-kernel";
	307	+ #qcom,smem-state-cells = <1>;
	308	+ };
	309	+
	310	+ modem_smp2p_in: slave-kernel {
	311	+ qcom,entry-name = "slave-kernel";
	312	+
	313	+ interrupt-controller;
	314	+ #interrupt-cells = <2>;
	315	+ };
	316	+ };
	317	+
	318	+ smp2p-slpi {
	319	+ compatible = "qcom,smp2p";
	320	+ qcom,smem = <481>, <430>;
	321	+
	322	+ interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
	323	+
	324	+ mboxes = <&apcs_glb 26>;
	325	+
	326	+ qcom,local-pid = <0>;
	327	+ qcom,remote-pid = <3>;
	328	+
	329	+ smp2p_slpi_in: slave-kernel {
	330	+ qcom,entry-name = "slave-kernel";
	331	+ interrupt-controller;
	332	+ #interrupt-cells = <2>;
	333	+ };
	334	+
	335	+ smp2p_slpi_out: master-kernel {
	336	+ qcom,entry-name = "master-kernel";
	337	+ #qcom,smem-state-cells = <1>;
361	338	};
362	339	};
363	340
..	..	@@ -367,58 +344,97 @@
367	344	ranges = <0 0 0 0xffffffff>;
368	345	compatible = "simple-bus";
369	346
	347	+ pcie_phy: phy@34000 {
	348	+ compatible = "qcom,msm8996-qmp-pcie-phy";
	349	+ reg = <0x00034000 0x488>;
	350	+ #clock-cells = <1>;
	351	+ #address-cells = <1>;
	352	+ #size-cells = <1>;
	353	+ ranges;
	354	+
	355	+ clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
	356	+ <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
	357	+ <&gcc GCC_PCIE_CLKREF_CLK>;
	358	+ clock-names = "aux", "cfg_ahb", "ref";
	359	+
	360	+ resets = <&gcc GCC_PCIE_PHY_BCR>,
	361	+ <&gcc GCC_PCIE_PHY_COM_BCR>,
	362	+ <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
	363	+ reset-names = "phy", "common", "cfg";
	364	+ status = "disabled";
	365	+
	366	+ pciephy_0: lane@35000 {
	367	+ reg = <0x00035000 0x130>,
	368	+ <0x00035200 0x200>,
	369	+ <0x00035400 0x1dc>;
	370	+ #phy-cells = <0>;
	371	+
	372	+ clock-output-names = "pcie_0_pipe_clk_src";
	373	+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
	374	+ clock-names = "pipe0";
	375	+ resets = <&gcc GCC_PCIE_0_PHY_BCR>;
	376	+ reset-names = "lane0";
	377	+ };
	378	+
	379	+ pciephy_1: lane@36000 {
	380	+ reg = <0x00036000 0x130>,
	381	+ <0x00036200 0x200>,
	382	+ <0x00036400 0x1dc>;
	383	+ #phy-cells = <0>;
	384	+
	385	+ clock-output-names = "pcie_1_pipe_clk_src";
	386	+ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
	387	+ clock-names = "pipe1";
	388	+ resets = <&gcc GCC_PCIE_1_PHY_BCR>;
	389	+ reset-names = "lane1";
	390	+ };
	391	+
	392	+ pciephy_2: lane@37000 {
	393	+ reg = <0x00037000 0x130>,
	394	+ <0x00037200 0x200>,
	395	+ <0x00037400 0x1dc>;
	396	+ #phy-cells = <0>;
	397	+
	398	+ clock-output-names = "pcie_2_pipe_clk_src";
	399	+ clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
	400	+ clock-names = "pipe2";
	401	+ resets = <&gcc GCC_PCIE_2_PHY_BCR>;
	402	+ reset-names = "lane2";
	403	+ };
	404	+ };
	405	+
370	406	rpm_msg_ram: memory@68000 {
371	407	compatible = "qcom,rpm-msg-ram";
372		- reg = <0x68000 0x6000>;
	408	+ reg = <0x00068000 0x6000>;
373	409	};
374	410
375		- tcsr_mutex_regs: syscon@740000 {
376		- compatible = "syscon";
377		- reg = <0x740000 0x20000>;
	411	+ qfprom@74000 {
	412	+ compatible = "qcom,qfprom";
	413	+ reg = <0x00074000 0x8ff>;
	414	+ #address-cells = <1>;
	415	+ #size-cells = <1>;
	416	+
	417	+ qusb2p_hstx_trim: hstx_trim@24e {
	418	+ reg = <0x24e 0x2>;
	419	+ bits = <5 4>;
	420	+ };
	421	+
	422	+ qusb2s_hstx_trim: hstx_trim@24f {
	423	+ reg = <0x24f 0x1>;
	424	+ bits = <1 4>;
	425	+ };
	426	+
	427	+ gpu_speed_bin: gpu_speed_bin@133 {
	428	+ reg = <0x133 0x1>;
	429	+ bits = <5 3>;
	430	+ };
378	431	};
379	432
380		- tsens0: thermal-sensor@4a9000 {
381		- compatible = "qcom,msm8996-tsens";
382		- reg = <0x4a9000 0x1000>, /* TM */
383		- <0x4a8000 0x1000>; /* SROT */
384		- #qcom,sensors = <13>;
385		- #thermal-sensor-cells = <1>;
386		- };
387		-
388		- tsens1: thermal-sensor@4ad000 {
389		- compatible = "qcom,msm8996-tsens";
390		- reg = <0x4ad000 0x1000>, /* TM */
391		- <0x4ac000 0x1000>; /* SROT */
392		- #qcom,sensors = <8>;
393		- #thermal-sensor-cells = <1>;
394		- };
395		-
396		- tcsr: syscon@7a0000 {
397		- compatible = "qcom,tcsr-msm8996", "syscon";
398		- reg = <0x7a0000 0x18000>;
399		- };
400		-
401		- intc: interrupt-controller@9bc0000 {
402		- compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
403		- #interrupt-cells = <3>;
404		- interrupt-controller;
405		- #redistributor-regions = <1>;
406		- redistributor-stride = <0x0 0x40000>;
407		- reg = <0x09bc0000 0x10000>,
408		- <0x09c00000 0x100000>;
409		- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
410		- };
411		-
412		- apcs: syscon@9820000 {
413		- compatible = "syscon";
414		- reg = <0x9820000 0x1000>;
415		- };
416		-
417		- apcs_glb: mailbox@9820000 {
418		- compatible = "qcom,msm8996-apcs-hmss-global";
419		- reg = <0x9820000 0x1000>;
420		-
421		- #mbox-cells = <1>;
	433	+ rng: rng@83000 {
	434	+ compatible = "qcom,prng-ee";
	435	+ reg = <0x00083000 0x1000>;
	436	+ clocks = <&gcc GCC_PRNG_AHB_CLK>;
	437	+ clock-names = "core";
422	438	};
423	439
424	440	gcc: clock-controller@300000 {
..	..	@@ -426,14 +442,1414 @@
426	442	#clock-cells = <1>;
427	443	#reset-cells = <1>;
428	444	#power-domain-cells = <1>;
429		- reg = <0x300000 0x90000>;
	445	+ reg = <0x00300000 0x90000>;
	446	+
	447	+ clocks = <&rpmcc RPM_SMD_LN_BB_CLK>;
	448	+ clock-names = "cxo2";
430	449	};
431	450
	451	+ tsens0: thermal-sensor@4a9000 {
	452	+ compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
	453	+ reg = <0x004a9000 0x1000>, /* TM */
	454	+ <0x004a8000 0x1000>; /* SROT */
	455	+ #qcom,sensors = <13>;
	456	+ interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
	457	+ <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
	458	+ interrupt-names = "uplow", "critical";
	459	+ #thermal-sensor-cells = <1>;
	460	+ };
	461	+
	462	+ tsens1: thermal-sensor@4ad000 {
	463	+ compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
	464	+ reg = <0x004ad000 0x1000>, /* TM */
	465	+ <0x004ac000 0x1000>; /* SROT */
	466	+ #qcom,sensors = <8>;
	467	+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
	468	+ <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
	469	+ interrupt-names = "uplow", "critical";
	470	+ #thermal-sensor-cells = <1>;
	471	+ };
	472	+
	473	+ tcsr_mutex_regs: syscon@740000 {
	474	+ compatible = "syscon";
	475	+ reg = <0x00740000 0x20000>;
	476	+ };
	477	+
	478	+ tcsr: syscon@7a0000 {
	479	+ compatible = "qcom,tcsr-msm8996", "syscon";
	480	+ reg = <0x007a0000 0x18000>;
	481	+ };
	482	+
	483	+ mmcc: clock-controller@8c0000 {
	484	+ compatible = "qcom,mmcc-msm8996";
	485	+ #clock-cells = <1>;
	486	+ #reset-cells = <1>;
	487	+ #power-domain-cells = <1>;
	488	+ reg = <0x008c0000 0x40000>;
	489	+ assigned-clocks = <&mmcc MMPLL9_PLL>,
	490	+ <&mmcc MMPLL1_PLL>,
	491	+ <&mmcc MMPLL3_PLL>,
	492	+ <&mmcc MMPLL4_PLL>,
	493	+ <&mmcc MMPLL5_PLL>;
	494	+ assigned-clock-rates = <624000000>,
	495	+ <810000000>,
	496	+ <980000000>,
	497	+ <960000000>,
	498	+ <825000000>;
	499	+ };
	500	+
	501	+ mdss: mdss@900000 {
	502	+ compatible = "qcom,mdss";
	503	+
	504	+ reg = <0x00900000 0x1000>,
	505	+ <0x009b0000 0x1040>,
	506	+ <0x009b8000 0x1040>;
	507	+ reg-names = "mdss_phys",
	508	+ "vbif_phys",
	509	+ "vbif_nrt_phys";
	510	+
	511	+ power-domains = <&mmcc MDSS_GDSC>;
	512	+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	513	+
	514	+ interrupt-controller;
	515	+ #interrupt-cells = <1>;
	516	+
	517	+ clocks = <&mmcc MDSS_AHB_CLK>;
	518	+ clock-names = "iface";
	519	+
	520	+ #address-cells = <1>;
	521	+ #size-cells = <1>;
	522	+ ranges;
	523	+
	524	+ mdp: mdp@901000 {
	525	+ compatible = "qcom,mdp5";
	526	+ reg = <0x00901000 0x90000>;
	527	+ reg-names = "mdp_phys";
	528	+
	529	+ interrupt-parent = <&mdss>;
	530	+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
	531	+
	532	+ clocks = <&mmcc MDSS_AHB_CLK>,
	533	+ <&mmcc MDSS_AXI_CLK>,
	534	+ <&mmcc MDSS_MDP_CLK>,
	535	+ <&mmcc SMMU_MDP_AXI_CLK>,
	536	+ <&mmcc MDSS_VSYNC_CLK>;
	537	+ clock-names = "iface",
	538	+ "bus",
	539	+ "core",
	540	+ "iommu",
	541	+ "vsync";
	542	+
	543	+ iommus = <&mdp_smmu 0>;
	544	+
	545	+ ports {
	546	+ #address-cells = <1>;
	547	+ #size-cells = <0>;
	548	+
	549	+ port@0 {
	550	+ reg = <0>;
	551	+ mdp5_intf3_out: endpoint {
	552	+ remote-endpoint = <&hdmi_in>;
	553	+ };
	554	+ };
	555	+ };
	556	+ };
	557	+
	558	+ hdmi: hdmi-tx@9a0000 {
	559	+ compatible = "qcom,hdmi-tx-8996";
	560	+ reg = <0x009a0000 0x50c>,
	561	+ <0x00070000 0x6158>,
	562	+ <0x009e0000 0xfff>;
	563	+ reg-names = "core_physical",
	564	+ "qfprom_physical",
	565	+ "hdcp_physical";
	566	+
	567	+ interrupt-parent = <&mdss>;
	568	+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
	569	+
	570	+ clocks = <&mmcc MDSS_MDP_CLK>,
	571	+ <&mmcc MDSS_AHB_CLK>,
	572	+ <&mmcc MDSS_HDMI_CLK>,
	573	+ <&mmcc MDSS_HDMI_AHB_CLK>,
	574	+ <&mmcc MDSS_EXTPCLK_CLK>;
	575	+ clock-names =
	576	+ "mdp_core",
	577	+ "iface",
	578	+ "core",
	579	+ "alt_iface",
	580	+ "extp";
	581	+
	582	+ phys = <&hdmi_phy>;
	583	+ phy-names = "hdmi_phy";
	584	+ #sound-dai-cells = <1>;
	585	+
	586	+ ports {
	587	+ #address-cells = <1>;
	588	+ #size-cells = <0>;
	589	+
	590	+ port@0 {
	591	+ reg = <0>;
	592	+ hdmi_in: endpoint {
	593	+ remote-endpoint = <&mdp5_intf3_out>;
	594	+ };
	595	+ };
	596	+ };
	597	+ };
	598	+
	599	+ hdmi_phy: hdmi-phy@9a0600 {
	600	+ #phy-cells = <0>;
	601	+ compatible = "qcom,hdmi-phy-8996";
	602	+ reg = <0x009a0600 0x1c4>,
	603	+ <0x009a0a00 0x124>,
	604	+ <0x009a0c00 0x124>,
	605	+ <0x009a0e00 0x124>,
	606	+ <0x009a1000 0x124>,
	607	+ <0x009a1200 0x0c8>;
	608	+ reg-names = "hdmi_pll",
	609	+ "hdmi_tx_l0",
	610	+ "hdmi_tx_l1",
	611	+ "hdmi_tx_l2",
	612	+ "hdmi_tx_l3",
	613	+ "hdmi_phy";
	614	+
	615	+ clocks = <&mmcc MDSS_AHB_CLK>,
	616	+ <&gcc GCC_HDMI_CLKREF_CLK>;
	617	+ clock-names = "iface",
	618	+ "ref";
	619	+ };
	620	+ };
	621	+ gpu@b00000 {
	622	+ compatible = "qcom,adreno-530.2", "qcom,adreno";
	623	+ #stream-id-cells = <16>;
	624	+
	625	+ reg = <0x00b00000 0x3f000>;
	626	+ reg-names = "kgsl_3d0_reg_memory";
	627	+
	628	+ interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
	629	+
	630	+ clocks = <&mmcc GPU_GX_GFX3D_CLK>,
	631	+ <&mmcc GPU_AHB_CLK>,
	632	+ <&mmcc GPU_GX_RBBMTIMER_CLK>,
	633	+ <&gcc GCC_BIMC_GFX_CLK>,
	634	+ <&gcc GCC_MMSS_BIMC_GFX_CLK>;
	635	+
	636	+ clock-names = "core",
	637	+ "iface",
	638	+ "rbbmtimer",
	639	+ "mem",
	640	+ "mem_iface";
	641	+
	642	+ power-domains = <&mmcc GPU_GX_GDSC>;
	643	+ iommus = <&adreno_smmu 0>;
	644	+
	645	+ nvmem-cells = <&gpu_speed_bin>;
	646	+ nvmem-cell-names = "speed_bin";
	647	+
	648	+ operating-points-v2 = <&gpu_opp_table>;
	649	+
	650	+ gpu_opp_table: opp-table {
	651	+ compatible ="operating-points-v2";
	652	+
	653	+ /*
	654	+ * 624Mhz and 560Mhz are only available on speed
	655	+ * bin (1 << 0). All the rest are available on
	656	+ * all bins of the hardware
	657	+ */
	658	+ opp-624000000 {
	659	+ opp-hz = /bits/ 64 <624000000>;
	660	+ opp-supported-hw = <0x01>;
	661	+ };
	662	+ opp-560000000 {
	663	+ opp-hz = /bits/ 64 <560000000>;
	664	+ opp-supported-hw = <0x01>;
	665	+ };
	666	+ opp-510000000 {
	667	+ opp-hz = /bits/ 64 <510000000>;
	668	+ opp-supported-hw = <0xFF>;
	669	+ };
	670	+ opp-401800000 {
	671	+ opp-hz = /bits/ 64 <401800000>;
	672	+ opp-supported-hw = <0xFF>;
	673	+ };
	674	+ opp-315000000 {
	675	+ opp-hz = /bits/ 64 <315000000>;
	676	+ opp-supported-hw = <0xFF>;
	677	+ };
	678	+ opp-214000000 {
	679	+ opp-hz = /bits/ 64 <214000000>;
	680	+ opp-supported-hw = <0xFF>;
	681	+ };
	682	+ opp-133000000 {
	683	+ opp-hz = /bits/ 64 <133000000>;
	684	+ opp-supported-hw = <0xFF>;
	685	+ };
	686	+ };
	687	+
	688	+ zap-shader {
	689	+ memory-region = <&zap_shader_region>;
	690	+ };
	691	+ };
	692	+
	693	+ msmgpio: pinctrl@1010000 {
	694	+ compatible = "qcom,msm8996-pinctrl";
	695	+ reg = <0x01010000 0x300000>;
	696	+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
	697	+ gpio-controller;
	698	+ gpio-ranges = <&msmgpio 0 0 150>;
	699	+ #gpio-cells = <2>;
	700	+ interrupt-controller;
	701	+ #interrupt-cells = <2>;
	702	+ };
	703	+
	704	+ spmi_bus: qcom,spmi@400f000 {
	705	+ compatible = "qcom,spmi-pmic-arb";
	706	+ reg = <0x0400f000 0x1000>,
	707	+ <0x04400000 0x800000>,
	708	+ <0x04c00000 0x800000>,
	709	+ <0x05800000 0x200000>,
	710	+ <0x0400a000 0x002100>;
	711	+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
	712	+ interrupt-names = "periph_irq";
	713	+ interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
	714	+ qcom,ee = <0>;
	715	+ qcom,channel = <0>;
	716	+ #address-cells = <2>;
	717	+ #size-cells = <0>;
	718	+ interrupt-controller;
	719	+ #interrupt-cells = <4>;
	720	+ };
	721	+
	722	+ agnoc@0 {
	723	+ power-domains = <&gcc AGGRE0_NOC_GDSC>;
	724	+ compatible = "simple-pm-bus";
	725	+ #address-cells = <1>;
	726	+ #size-cells = <1>;
	727	+ ranges;
	728	+
	729	+ pcie0: pcie@600000 {
	730	+ compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
	731	+ status = "disabled";
	732	+ power-domains = <&gcc PCIE0_GDSC>;
	733	+ bus-range = <0x00 0xff>;
	734	+ num-lanes = <1>;
	735	+
	736	+ reg = <0x00600000 0x2000>,
	737	+ <0x0c000000 0xf1d>,
	738	+ <0x0c000f20 0xa8>,
	739	+ <0x0c100000 0x100000>;
	740	+ reg-names = "parf", "dbi", "elbi","config";
	741	+
	742	+ phys = <&pciephy_0>;
	743	+ phy-names = "pciephy";
	744	+
	745	+ #address-cells = <3>;
	746	+ #size-cells = <2>;
	747	+ ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
	748	+ <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
	749	+
	750	+ interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
	751	+ interrupt-names = "msi";
	752	+ #interrupt-cells = <1>;
	753	+ interrupt-map-mask = <0 0 0 0x7>;
	754	+ interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
	755	+ <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
	756	+ <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
	757	+ <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
	758	+
	759	+ pinctrl-names = "default", "sleep";
	760	+ pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>;
	761	+ pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>;
	762	+
	763	+ linux,pci-domain = <0>;
	764	+
	765	+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
	766	+ <&gcc GCC_PCIE_0_AUX_CLK>,
	767	+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
	768	+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
	769	+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
	770	+
	771	+ clock-names = "pipe",
	772	+ "aux",
	773	+ "cfg",
	774	+ "bus_master",
	775	+ "bus_slave";
	776	+
	777	+ };
	778	+
	779	+ pcie1: pcie@608000 {
	780	+ compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
	781	+ power-domains = <&gcc PCIE1_GDSC>;
	782	+ bus-range = <0x00 0xff>;
	783	+ num-lanes = <1>;
	784	+
	785	+ status = "disabled";
	786	+
	787	+ reg = <0x00608000 0x2000>,
	788	+ <0x0d000000 0xf1d>,
	789	+ <0x0d000f20 0xa8>,
	790	+ <0x0d100000 0x100000>;
	791	+
	792	+ reg-names = "parf", "dbi", "elbi","config";
	793	+
	794	+ phys = <&pciephy_1>;
	795	+ phy-names = "pciephy";
	796	+
	797	+ #address-cells = <3>;
	798	+ #size-cells = <2>;
	799	+ ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
	800	+ <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
	801	+
	802	+ interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
	803	+ interrupt-names = "msi";
	804	+ #interrupt-cells = <1>;
	805	+ interrupt-map-mask = <0 0 0 0x7>;
	806	+ interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
	807	+ <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
	808	+ <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
	809	+ <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
	810	+
	811	+ pinctrl-names = "default", "sleep";
	812	+ pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>;
	813	+ pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>;
	814	+
	815	+ linux,pci-domain = <1>;
	816	+
	817	+ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
	818	+ <&gcc GCC_PCIE_1_AUX_CLK>,
	819	+ <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
	820	+ <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
	821	+ <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
	822	+
	823	+ clock-names = "pipe",
	824	+ "aux",
	825	+ "cfg",
	826	+ "bus_master",
	827	+ "bus_slave";
	828	+ };
	829	+
	830	+ pcie2: pcie@610000 {
	831	+ compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
	832	+ power-domains = <&gcc PCIE2_GDSC>;
	833	+ bus-range = <0x00 0xff>;
	834	+ num-lanes = <1>;
	835	+ status = "disabled";
	836	+ reg = <0x00610000 0x2000>,
	837	+ <0x0e000000 0xf1d>,
	838	+ <0x0e000f20 0xa8>,
	839	+ <0x0e100000 0x100000>;
	840	+
	841	+ reg-names = "parf", "dbi", "elbi","config";
	842	+
	843	+ phys = <&pciephy_2>;
	844	+ phy-names = "pciephy";
	845	+
	846	+ #address-cells = <3>;
	847	+ #size-cells = <2>;
	848	+ ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
	849	+ <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
	850	+
	851	+ device_type = "pci";
	852	+
	853	+ interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
	854	+ interrupt-names = "msi";
	855	+ #interrupt-cells = <1>;
	856	+ interrupt-map-mask = <0 0 0 0x7>;
	857	+ interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
	858	+ <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
	859	+ <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
	860	+ <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
	861	+
	862	+ pinctrl-names = "default", "sleep";
	863	+ pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>;
	864	+ pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >;
	865	+
	866	+ linux,pci-domain = <2>;
	867	+ clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
	868	+ <&gcc GCC_PCIE_2_AUX_CLK>,
	869	+ <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
	870	+ <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
	871	+ <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
	872	+
	873	+ clock-names = "pipe",
	874	+ "aux",
	875	+ "cfg",
	876	+ "bus_master",
	877	+ "bus_slave";
	878	+ };
	879	+ };
	880	+
	881	+ ufshc: ufshc@624000 {
	882	+ compatible = "qcom,ufshc";
	883	+ reg = <0x00624000 0x2500>;
	884	+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
	885	+
	886	+ phys = <&ufsphy_lane>;
	887	+ phy-names = "ufsphy";
	888	+
	889	+ power-domains = <&gcc UFS_GDSC>;
	890	+
	891	+ clock-names =
	892	+ "core_clk_src",
	893	+ "core_clk",
	894	+ "bus_clk",
	895	+ "bus_aggr_clk",
	896	+ "iface_clk",
	897	+ "core_clk_unipro_src",
	898	+ "core_clk_unipro",
	899	+ "core_clk_ice",
	900	+ "ref_clk",
	901	+ "tx_lane0_sync_clk",
	902	+ "rx_lane0_sync_clk";
	903	+ clocks =
	904	+ <&gcc UFS_AXI_CLK_SRC>,
	905	+ <&gcc GCC_UFS_AXI_CLK>,
	906	+ <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
	907	+ <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
	908	+ <&gcc GCC_UFS_AHB_CLK>,
	909	+ <&gcc UFS_ICE_CORE_CLK_SRC>,
	910	+ <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
	911	+ <&gcc GCC_UFS_ICE_CORE_CLK>,
	912	+ <&rpmcc RPM_SMD_LN_BB_CLK>,
	913	+ <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
	914	+ <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
	915	+ freq-table-hz =
	916	+ <100000000 200000000>,
	917	+ <0 0>,
	918	+ <0 0>,
	919	+ <0 0>,
	920	+ <0 0>,
	921	+ <150000000 300000000>,
	922	+ <0 0>,
	923	+ <0 0>,
	924	+ <0 0>,
	925	+ <0 0>,
	926	+ <0 0>;
	927	+
	928	+ lanes-per-direction = <1>;
	929	+ #reset-cells = <1>;
	930	+ status = "disabled";
	931	+
	932	+ ufs_variant {
	933	+ compatible = "qcom,ufs_variant";
	934	+ };
	935	+ };
	936	+
	937	+ ufsphy: phy@627000 {
	938	+ compatible = "qcom,msm8996-qmp-ufs-phy";
	939	+ reg = <0x00627000 0x1c4>;
	940	+ #address-cells = <1>;
	941	+ #size-cells = <1>;
	942	+ ranges;
	943	+
	944	+ clocks = <&gcc GCC_UFS_CLKREF_CLK>;
	945	+ clock-names = "ref";
	946	+
	947	+ resets = <&ufshc 0>;
	948	+ reset-names = "ufsphy";
	949	+ status = "disabled";
	950	+
	951	+ ufsphy_lane: lanes@627400 {
	952	+ reg = <0x627400 0x12c>,
	953	+ <0x627600 0x200>,
	954	+ <0x627c00 0x1b4>;
	955	+ #phy-cells = <0>;
	956	+ };
	957	+ };
	958	+
	959	+ camss: camss@a00000 {
	960	+ compatible = "qcom,msm8996-camss";
	961	+ reg = <0x00a34000 0x1000>,
	962	+ <0x00a00030 0x4>,
	963	+ <0x00a35000 0x1000>,
	964	+ <0x00a00038 0x4>,
	965	+ <0x00a36000 0x1000>,
	966	+ <0x00a00040 0x4>,
	967	+ <0x00a30000 0x100>,
	968	+ <0x00a30400 0x100>,
	969	+ <0x00a30800 0x100>,
	970	+ <0x00a30c00 0x100>,
	971	+ <0x00a31000 0x500>,
	972	+ <0x00a00020 0x10>,
	973	+ <0x00a10000 0x1000>,
	974	+ <0x00a14000 0x1000>;
	975	+ reg-names = "csiphy0",
	976	+ "csiphy0_clk_mux",
	977	+ "csiphy1",
	978	+ "csiphy1_clk_mux",
	979	+ "csiphy2",
	980	+ "csiphy2_clk_mux",
	981	+ "csid0",
	982	+ "csid1",
	983	+ "csid2",
	984	+ "csid3",
	985	+ "ispif",
	986	+ "csi_clk_mux",
	987	+ "vfe0",
	988	+ "vfe1";
	989	+ interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
	990	+ <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
	991	+ <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
	992	+ <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
	993	+ <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
	994	+ <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
	995	+ <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
	996	+ <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
	997	+ <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
	998	+ <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
	999	+ interrupt-names = "csiphy0",
	1000	+ "csiphy1",
	1001	+ "csiphy2",
	1002	+ "csid0",
	1003	+ "csid1",
	1004	+ "csid2",
	1005	+ "csid3",
	1006	+ "ispif",
	1007	+ "vfe0",
	1008	+ "vfe1";
	1009	+ power-domains = <&mmcc VFE0_GDSC>,
	1010	+ <&mmcc VFE1_GDSC>;
	1011	+ clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
	1012	+ <&mmcc CAMSS_ISPIF_AHB_CLK>,
	1013	+ <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
	1014	+ <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
	1015	+ <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
	1016	+ <&mmcc CAMSS_CSI0_AHB_CLK>,
	1017	+ <&mmcc CAMSS_CSI0_CLK>,
	1018	+ <&mmcc CAMSS_CSI0PHY_CLK>,
	1019	+ <&mmcc CAMSS_CSI0PIX_CLK>,
	1020	+ <&mmcc CAMSS_CSI0RDI_CLK>,
	1021	+ <&mmcc CAMSS_CSI1_AHB_CLK>,
	1022	+ <&mmcc CAMSS_CSI1_CLK>,
	1023	+ <&mmcc CAMSS_CSI1PHY_CLK>,
	1024	+ <&mmcc CAMSS_CSI1PIX_CLK>,
	1025	+ <&mmcc CAMSS_CSI1RDI_CLK>,
	1026	+ <&mmcc CAMSS_CSI2_AHB_CLK>,
	1027	+ <&mmcc CAMSS_CSI2_CLK>,
	1028	+ <&mmcc CAMSS_CSI2PHY_CLK>,
	1029	+ <&mmcc CAMSS_CSI2PIX_CLK>,
	1030	+ <&mmcc CAMSS_CSI2RDI_CLK>,
	1031	+ <&mmcc CAMSS_CSI3_AHB_CLK>,
	1032	+ <&mmcc CAMSS_CSI3_CLK>,
	1033	+ <&mmcc CAMSS_CSI3PHY_CLK>,
	1034	+ <&mmcc CAMSS_CSI3PIX_CLK>,
	1035	+ <&mmcc CAMSS_CSI3RDI_CLK>,
	1036	+ <&mmcc CAMSS_AHB_CLK>,
	1037	+ <&mmcc CAMSS_VFE0_CLK>,
	1038	+ <&mmcc CAMSS_CSI_VFE0_CLK>,
	1039	+ <&mmcc CAMSS_VFE0_AHB_CLK>,
	1040	+ <&mmcc CAMSS_VFE0_STREAM_CLK>,
	1041	+ <&mmcc CAMSS_VFE1_CLK>,
	1042	+ <&mmcc CAMSS_CSI_VFE1_CLK>,
	1043	+ <&mmcc CAMSS_VFE1_AHB_CLK>,
	1044	+ <&mmcc CAMSS_VFE1_STREAM_CLK>,
	1045	+ <&mmcc CAMSS_VFE_AHB_CLK>,
	1046	+ <&mmcc CAMSS_VFE_AXI_CLK>;
	1047	+ clock-names = "top_ahb",
	1048	+ "ispif_ahb",
	1049	+ "csiphy0_timer",
	1050	+ "csiphy1_timer",
	1051	+ "csiphy2_timer",
	1052	+ "csi0_ahb",
	1053	+ "csi0",
	1054	+ "csi0_phy",
	1055	+ "csi0_pix",
	1056	+ "csi0_rdi",
	1057	+ "csi1_ahb",
	1058	+ "csi1",
	1059	+ "csi1_phy",
	1060	+ "csi1_pix",
	1061	+ "csi1_rdi",
	1062	+ "csi2_ahb",
	1063	+ "csi2",
	1064	+ "csi2_phy",
	1065	+ "csi2_pix",
	1066	+ "csi2_rdi",
	1067	+ "csi3_ahb",
	1068	+ "csi3",
	1069	+ "csi3_phy",
	1070	+ "csi3_pix",
	1071	+ "csi3_rdi",
	1072	+ "ahb",
	1073	+ "vfe0",
	1074	+ "csi_vfe0",
	1075	+ "vfe0_ahb",
	1076	+ "vfe0_stream",
	1077	+ "vfe1",
	1078	+ "csi_vfe1",
	1079	+ "vfe1_ahb",
	1080	+ "vfe1_stream",
	1081	+ "vfe_ahb",
	1082	+ "vfe_axi";
	1083	+ iommus = <&vfe_smmu 0>,
	1084	+ <&vfe_smmu 1>,
	1085	+ <&vfe_smmu 2>,
	1086	+ <&vfe_smmu 3>;
	1087	+ status = "disabled";
	1088	+ ports {
	1089	+ #address-cells = <1>;
	1090	+ #size-cells = <0>;
	1091	+ };
	1092	+ };
	1093	+
	1094	+ cci: cci@a0c000 {
	1095	+ compatible = "qcom,msm8996-cci";
	1096	+ #address-cells = <1>;
	1097	+ #size-cells = <0>;
	1098	+ reg = <0xa0c000 0x1000>;
	1099	+ interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
	1100	+ power-domains = <&mmcc CAMSS_GDSC>;
	1101	+ clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
	1102	+ <&mmcc CAMSS_CCI_AHB_CLK>,
	1103	+ <&mmcc CAMSS_CCI_CLK>,
	1104	+ <&mmcc CAMSS_AHB_CLK>;
	1105	+ clock-names = "camss_top_ahb",
	1106	+ "cci_ahb",
	1107	+ "cci",
	1108	+ "camss_ahb";
	1109	+ assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
	1110	+ <&mmcc CAMSS_CCI_CLK>;
	1111	+ assigned-clock-rates = <80000000>, <37500000>;
	1112	+ pinctrl-names = "default";
	1113	+ pinctrl-0 = <&cci0_default &cci1_default>;
	1114	+ status = "disabled";
	1115	+
	1116	+ cci_i2c0: i2c-bus@0 {
	1117	+ reg = <0>;
	1118	+ clock-frequency = <400000>;
	1119	+ #address-cells = <1>;
	1120	+ #size-cells = <0>;
	1121	+ };
	1122	+
	1123	+ cci_i2c1: i2c-bus@1 {
	1124	+ reg = <1>;
	1125	+ clock-frequency = <400000>;
	1126	+ #address-cells = <1>;
	1127	+ #size-cells = <0>;
	1128	+ };
	1129	+ };
	1130	+
	1131	+ adreno_smmu: iommu@b40000 {
	1132	+ compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
	1133	+ reg = <0x00b40000 0x10000>;
	1134	+
	1135	+ #global-interrupts = <1>;
	1136	+ interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
	1137	+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
	1138	+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
	1139	+ #iommu-cells = <1>;
	1140	+
	1141	+ clocks = <&mmcc GPU_AHB_CLK>,
	1142	+ <&gcc GCC_MMSS_BIMC_GFX_CLK>;
	1143	+ clock-names = "iface", "bus";
	1144	+
	1145	+ power-domains = <&mmcc GPU_GDSC>;
	1146	+ };
	1147	+
	1148	+ video-codec@c00000 {
	1149	+ compatible = "qcom,msm8996-venus";
	1150	+ reg = <0x00c00000 0xff000>;
	1151	+ interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
	1152	+ power-domains = <&mmcc VENUS_GDSC>;
	1153	+ clocks = <&mmcc VIDEO_CORE_CLK>,
	1154	+ <&mmcc VIDEO_AHB_CLK>,
	1155	+ <&mmcc VIDEO_AXI_CLK>,
	1156	+ <&mmcc VIDEO_MAXI_CLK>;
	1157	+ clock-names = "core", "iface", "bus", "mbus";
	1158	+ iommus = <&venus_smmu 0x00>,
	1159	+ <&venus_smmu 0x01>,
	1160	+ <&venus_smmu 0x0a>,
	1161	+ <&venus_smmu 0x07>,
	1162	+ <&venus_smmu 0x0e>,
	1163	+ <&venus_smmu 0x0f>,
	1164	+ <&venus_smmu 0x08>,
	1165	+ <&venus_smmu 0x09>,
	1166	+ <&venus_smmu 0x0b>,
	1167	+ <&venus_smmu 0x0c>,
	1168	+ <&venus_smmu 0x0d>,
	1169	+ <&venus_smmu 0x10>,
	1170	+ <&venus_smmu 0x11>,
	1171	+ <&venus_smmu 0x21>,
	1172	+ <&venus_smmu 0x28>,
	1173	+ <&venus_smmu 0x29>,
	1174	+ <&venus_smmu 0x2b>,
	1175	+ <&venus_smmu 0x2c>,
	1176	+ <&venus_smmu 0x2d>,
	1177	+ <&venus_smmu 0x31>;
	1178	+ memory-region = <&venus_region>;
	1179	+ status = "okay";
	1180	+
	1181	+ video-decoder {
	1182	+ compatible = "venus-decoder";
	1183	+ clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
	1184	+ clock-names = "core";
	1185	+ power-domains = <&mmcc VENUS_CORE0_GDSC>;
	1186	+ };
	1187	+
	1188	+ video-encoder {
	1189	+ compatible = "venus-encoder";
	1190	+ clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
	1191	+ clock-names = "core";
	1192	+ power-domains = <&mmcc VENUS_CORE1_GDSC>;
	1193	+ };
	1194	+ };
	1195	+
	1196	+ mdp_smmu: iommu@d00000 {
	1197	+ compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
	1198	+ reg = <0x00d00000 0x10000>;
	1199	+
	1200	+ #global-interrupts = <1>;
	1201	+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
	1202	+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
	1203	+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
	1204	+ #iommu-cells = <1>;
	1205	+ clocks = <&mmcc SMMU_MDP_AHB_CLK>,
	1206	+ <&mmcc SMMU_MDP_AXI_CLK>;
	1207	+ clock-names = "iface", "bus";
	1208	+
	1209	+ power-domains = <&mmcc MDSS_GDSC>;
	1210	+ };
	1211	+
	1212	+ venus_smmu: iommu@d40000 {
	1213	+ compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
	1214	+ reg = <0x00d40000 0x20000>;
	1215	+ #global-interrupts = <1>;
	1216	+ interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
	1217	+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
	1218	+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
	1219	+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
	1220	+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
	1221	+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
	1222	+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
	1223	+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
	1224	+ power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
	1225	+ clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
	1226	+ <&mmcc SMMU_VIDEO_AXI_CLK>;
	1227	+ clock-names = "iface", "bus";
	1228	+ #iommu-cells = <1>;
	1229	+ status = "okay";
	1230	+ };
	1231	+
	1232	+ vfe_smmu: iommu@da0000 {
	1233	+ compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
	1234	+ reg = <0x00da0000 0x10000>;
	1235	+
	1236	+ #global-interrupts = <1>;
	1237	+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
	1238	+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
	1239	+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
	1240	+ power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
	1241	+ clocks = <&mmcc SMMU_VFE_AHB_CLK>,
	1242	+ <&mmcc SMMU_VFE_AXI_CLK>;
	1243	+ clock-names = "iface",
	1244	+ "bus";
	1245	+ #iommu-cells = <1>;
	1246	+ };
	1247	+
	1248	+ lpass_q6_smmu: iommu@1600000 {
	1249	+ compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
	1250	+ reg = <0x01600000 0x20000>;
	1251	+ #iommu-cells = <1>;
	1252	+ power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
	1253	+
	1254	+ #global-interrupts = <1>;
	1255	+ interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
	1256	+ <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
	1257	+ <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
	1258	+ <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
	1259	+ <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
	1260	+ <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
	1261	+ <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
	1262	+ <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
	1263	+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
	1264	+ <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
	1265	+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
	1266	+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
	1267	+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
	1268	+
	1269	+ clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
	1270	+ <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
	1271	+ clock-names = "iface", "bus";
	1272	+ };
	1273	+
	1274	+ stm@3002000 {
	1275	+ compatible = "arm,coresight-stm", "arm,primecell";
	1276	+ reg = <0x3002000 0x1000>,
	1277	+ <0x8280000 0x180000>;
	1278	+ reg-names = "stm-base", "stm-stimulus-base";
	1279	+
	1280	+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	1281	+ clock-names = "apb_pclk", "atclk";
	1282	+
	1283	+ out-ports {
	1284	+ port {
	1285	+ stm_out: endpoint {
	1286	+ remote-endpoint =
	1287	+ <&funnel0_in>;
	1288	+ };
	1289	+ };
	1290	+ };
	1291	+ };
	1292	+
	1293	+ tpiu@3020000 {
	1294	+ compatible = "arm,coresight-tpiu", "arm,primecell";
	1295	+ reg = <0x3020000 0x1000>;
	1296	+
	1297	+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	1298	+ clock-names = "apb_pclk", "atclk";
	1299	+
	1300	+ in-ports {
	1301	+ port {
	1302	+ tpiu_in: endpoint {
	1303	+ remote-endpoint =
	1304	+ <&replicator_out1>;
	1305	+ };
	1306	+ };
	1307	+ };
	1308	+ };
	1309	+
	1310	+ funnel@3021000 {
	1311	+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	1312	+ reg = <0x3021000 0x1000>;
	1313	+
	1314	+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	1315	+ clock-names = "apb_pclk", "atclk";
	1316	+
	1317	+ in-ports {
	1318	+ #address-cells = <1>;
	1319	+ #size-cells = <0>;
	1320	+
	1321	+ port@7 {
	1322	+ reg = <7>;
	1323	+ funnel0_in: endpoint {
	1324	+ remote-endpoint =
	1325	+ <&stm_out>;
	1326	+ };
	1327	+ };
	1328	+ };
	1329	+
	1330	+ out-ports {
	1331	+ port {
	1332	+ funnel0_out: endpoint {
	1333	+ remote-endpoint =
	1334	+ <&merge_funnel_in0>;
	1335	+ };
	1336	+ };
	1337	+ };
	1338	+ };
	1339	+
	1340	+ funnel@3022000 {
	1341	+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	1342	+ reg = <0x3022000 0x1000>;
	1343	+
	1344	+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	1345	+ clock-names = "apb_pclk", "atclk";
	1346	+
	1347	+ in-ports {
	1348	+ #address-cells = <1>;
	1349	+ #size-cells = <0>;
	1350	+
	1351	+ port@6 {
	1352	+ reg = <6>;
	1353	+ funnel1_in: endpoint {
	1354	+ remote-endpoint =
	1355	+ <&apss_merge_funnel_out>;
	1356	+ };
	1357	+ };
	1358	+ };
	1359	+
	1360	+ out-ports {
	1361	+ port {
	1362	+ funnel1_out: endpoint {
	1363	+ remote-endpoint =
	1364	+ <&merge_funnel_in1>;
	1365	+ };
	1366	+ };
	1367	+ };
	1368	+ };
	1369	+
	1370	+ funnel@3023000 {
	1371	+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	1372	+ reg = <0x3023000 0x1000>;
	1373	+
	1374	+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	1375	+ clock-names = "apb_pclk", "atclk";
	1376	+
	1377	+
	1378	+ out-ports {
	1379	+ port {
	1380	+ funnel2_out: endpoint {
	1381	+ remote-endpoint =
	1382	+ <&merge_funnel_in2>;
	1383	+ };
	1384	+ };
	1385	+ };
	1386	+ };
	1387	+
	1388	+ funnel@3025000 {
	1389	+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	1390	+ reg = <0x3025000 0x1000>;
	1391	+
	1392	+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	1393	+ clock-names = "apb_pclk", "atclk";
	1394	+
	1395	+ in-ports {
	1396	+ #address-cells = <1>;
	1397	+ #size-cells = <0>;
	1398	+
	1399	+ port@0 {
	1400	+ reg = <0>;
	1401	+ merge_funnel_in0: endpoint {
	1402	+ remote-endpoint =
	1403	+ <&funnel0_out>;
	1404	+ };
	1405	+ };
	1406	+
	1407	+ port@1 {
	1408	+ reg = <1>;
	1409	+ merge_funnel_in1: endpoint {
	1410	+ remote-endpoint =
	1411	+ <&funnel1_out>;
	1412	+ };
	1413	+ };
	1414	+
	1415	+ port@2 {
	1416	+ reg = <2>;
	1417	+ merge_funnel_in2: endpoint {
	1418	+ remote-endpoint =
	1419	+ <&funnel2_out>;
	1420	+ };
	1421	+ };
	1422	+ };
	1423	+
	1424	+ out-ports {
	1425	+ port {
	1426	+ merge_funnel_out: endpoint {
	1427	+ remote-endpoint =
	1428	+ <&etf_in>;
	1429	+ };
	1430	+ };
	1431	+ };
	1432	+ };
	1433	+
	1434	+ replicator@3026000 {
	1435	+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
	1436	+ reg = <0x3026000 0x1000>;
	1437	+
	1438	+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	1439	+ clock-names = "apb_pclk", "atclk";
	1440	+
	1441	+ in-ports {
	1442	+ port {
	1443	+ replicator_in: endpoint {
	1444	+ remote-endpoint =
	1445	+ <&etf_out>;
	1446	+ };
	1447	+ };
	1448	+ };
	1449	+
	1450	+ out-ports {
	1451	+ #address-cells = <1>;
	1452	+ #size-cells = <0>;
	1453	+
	1454	+ port@0 {
	1455	+ reg = <0>;
	1456	+ replicator_out0: endpoint {
	1457	+ remote-endpoint =
	1458	+ <&etr_in>;
	1459	+ };
	1460	+ };
	1461	+
	1462	+ port@1 {
	1463	+ reg = <1>;
	1464	+ replicator_out1: endpoint {
	1465	+ remote-endpoint =
	1466	+ <&tpiu_in>;
	1467	+ };
	1468	+ };
	1469	+ };
	1470	+ };
	1471	+
	1472	+ etf@3027000 {
	1473	+ compatible = "arm,coresight-tmc", "arm,primecell";
	1474	+ reg = <0x3027000 0x1000>;
	1475	+
	1476	+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	1477	+ clock-names = "apb_pclk", "atclk";
	1478	+
	1479	+ in-ports {
	1480	+ port {
	1481	+ etf_in: endpoint {
	1482	+ remote-endpoint =
	1483	+ <&merge_funnel_out>;
	1484	+ };
	1485	+ };
	1486	+ };
	1487	+
	1488	+ out-ports {
	1489	+ port {
	1490	+ etf_out: endpoint {
	1491	+ remote-endpoint =
	1492	+ <&replicator_in>;
	1493	+ };
	1494	+ };
	1495	+ };
	1496	+ };
	1497	+
	1498	+ etr@3028000 {
	1499	+ compatible = "arm,coresight-tmc", "arm,primecell";
	1500	+ reg = <0x3028000 0x1000>;
	1501	+
	1502	+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	1503	+ clock-names = "apb_pclk", "atclk";
	1504	+ arm,scatter-gather;
	1505	+
	1506	+ in-ports {
	1507	+ port {
	1508	+ etr_in: endpoint {
	1509	+ remote-endpoint =
	1510	+ <&replicator_out0>;
	1511	+ };
	1512	+ };
	1513	+ };
	1514	+ };
	1515	+
	1516	+ debug@3810000 {
	1517	+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
	1518	+ reg = <0x3810000 0x1000>;
	1519	+
	1520	+ clocks = <&rpmcc RPM_QDSS_CLK>;
	1521	+ clock-names = "apb_pclk";
	1522	+
	1523	+ cpu = <&CPU0>;
	1524	+ };
	1525	+
	1526	+ etm@3840000 {
	1527	+ compatible = "arm,coresight-etm4x", "arm,primecell";
	1528	+ reg = <0x3840000 0x1000>;
	1529	+
	1530	+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	1531	+ clock-names = "apb_pclk", "atclk";
	1532	+
	1533	+ cpu = <&CPU0>;
	1534	+
	1535	+ out-ports {
	1536	+ port {
	1537	+ etm0_out: endpoint {
	1538	+ remote-endpoint =
	1539	+ <&apss_funnel0_in0>;
	1540	+ };
	1541	+ };
	1542	+ };
	1543	+ };
	1544	+
	1545	+ debug@3910000 {
	1546	+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
	1547	+ reg = <0x3910000 0x1000>;
	1548	+
	1549	+ clocks = <&rpmcc RPM_QDSS_CLK>;
	1550	+ clock-names = "apb_pclk";
	1551	+
	1552	+ cpu = <&CPU1>;
	1553	+ };
	1554	+
	1555	+ etm@3940000 {
	1556	+ compatible = "arm,coresight-etm4x", "arm,primecell";
	1557	+ reg = <0x3940000 0x1000>;
	1558	+
	1559	+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	1560	+ clock-names = "apb_pclk", "atclk";
	1561	+
	1562	+ cpu = <&CPU1>;
	1563	+
	1564	+ out-ports {
	1565	+ port {
	1566	+ etm1_out: endpoint {
	1567	+ remote-endpoint =
	1568	+ <&apss_funnel0_in1>;
	1569	+ };
	1570	+ };
	1571	+ };
	1572	+ };
	1573	+
	1574	+ funnel@39b0000 { /* APSS Funnel 0 */
	1575	+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	1576	+ reg = <0x39b0000 0x1000>;
	1577	+
	1578	+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	1579	+ clock-names = "apb_pclk", "atclk";
	1580	+
	1581	+ in-ports {
	1582	+ #address-cells = <1>;
	1583	+ #size-cells = <0>;
	1584	+
	1585	+ port@0 {
	1586	+ reg = <0>;
	1587	+ apss_funnel0_in0: endpoint {
	1588	+ remote-endpoint = <&etm0_out>;
	1589	+ };
	1590	+ };
	1591	+
	1592	+ port@1 {
	1593	+ reg = <1>;
	1594	+ apss_funnel0_in1: endpoint {
	1595	+ remote-endpoint = <&etm1_out>;
	1596	+ };
	1597	+ };
	1598	+ };
	1599	+
	1600	+ out-ports {
	1601	+ port {
	1602	+ apss_funnel0_out: endpoint {
	1603	+ remote-endpoint =
	1604	+ <&apss_merge_funnel_in0>;
	1605	+ };
	1606	+ };
	1607	+ };
	1608	+ };
	1609	+
	1610	+ debug@3a10000 {
	1611	+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
	1612	+ reg = <0x3a10000 0x1000>;
	1613	+
	1614	+ clocks = <&rpmcc RPM_QDSS_CLK>;
	1615	+ clock-names = "apb_pclk";
	1616	+
	1617	+ cpu = <&CPU2>;
	1618	+ };
	1619	+
	1620	+ etm@3a40000 {
	1621	+ compatible = "arm,coresight-etm4x", "arm,primecell";
	1622	+ reg = <0x3a40000 0x1000>;
	1623	+
	1624	+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	1625	+ clock-names = "apb_pclk", "atclk";
	1626	+
	1627	+ cpu = <&CPU2>;
	1628	+
	1629	+ out-ports {
	1630	+ port {
	1631	+ etm2_out: endpoint {
	1632	+ remote-endpoint =
	1633	+ <&apss_funnel1_in0>;
	1634	+ };
	1635	+ };
	1636	+ };
	1637	+ };
	1638	+
	1639	+ debug@3b10000 {
	1640	+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
	1641	+ reg = <0x3b10000 0x1000>;
	1642	+
	1643	+ clocks = <&rpmcc RPM_QDSS_CLK>;
	1644	+ clock-names = "apb_pclk";
	1645	+
	1646	+ cpu = <&CPU3>;
	1647	+ };
	1648	+
	1649	+ etm@3b40000 {
	1650	+ compatible = "arm,coresight-etm4x", "arm,primecell";
	1651	+ reg = <0x3b40000 0x1000>;
	1652	+
	1653	+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	1654	+ clock-names = "apb_pclk", "atclk";
	1655	+
	1656	+ cpu = <&CPU3>;
	1657	+
	1658	+ out-ports {
	1659	+ port {
	1660	+ etm3_out: endpoint {
	1661	+ remote-endpoint =
	1662	+ <&apss_funnel1_in1>;
	1663	+ };
	1664	+ };
	1665	+ };
	1666	+ };
	1667	+
	1668	+ funnel@3bb0000 { /* APSS Funnel 1 */
	1669	+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	1670	+ reg = <0x3bb0000 0x1000>;
	1671	+
	1672	+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	1673	+ clock-names = "apb_pclk", "atclk";
	1674	+
	1675	+ in-ports {
	1676	+ #address-cells = <1>;
	1677	+ #size-cells = <0>;
	1678	+
	1679	+ port@0 {
	1680	+ reg = <0>;
	1681	+ apss_funnel1_in0: endpoint {
	1682	+ remote-endpoint = <&etm2_out>;
	1683	+ };
	1684	+ };
	1685	+
	1686	+ port@1 {
	1687	+ reg = <1>;
	1688	+ apss_funnel1_in1: endpoint {
	1689	+ remote-endpoint = <&etm3_out>;
	1690	+ };
	1691	+ };
	1692	+ };
	1693	+
	1694	+ out-ports {
	1695	+ port {
	1696	+ apss_funnel1_out: endpoint {
	1697	+ remote-endpoint =
	1698	+ <&apss_merge_funnel_in1>;
	1699	+ };
	1700	+ };
	1701	+ };
	1702	+ };
	1703	+
	1704	+ funnel@3bc0000 {
	1705	+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	1706	+ reg = <0x3bc0000 0x1000>;
	1707	+
	1708	+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	1709	+ clock-names = "apb_pclk", "atclk";
	1710	+
	1711	+ in-ports {
	1712	+ #address-cells = <1>;
	1713	+ #size-cells = <0>;
	1714	+
	1715	+ port@0 {
	1716	+ reg = <0>;
	1717	+ apss_merge_funnel_in0: endpoint {
	1718	+ remote-endpoint =
	1719	+ <&apss_funnel0_out>;
	1720	+ };
	1721	+ };
	1722	+
	1723	+ port@1 {
	1724	+ reg = <1>;
	1725	+ apss_merge_funnel_in1: endpoint {
	1726	+ remote-endpoint =
	1727	+ <&apss_funnel1_out>;
	1728	+ };
	1729	+ };
	1730	+ };
	1731	+
	1732	+ out-ports {
	1733	+ port {
	1734	+ apss_merge_funnel_out: endpoint {
	1735	+ remote-endpoint =
	1736	+ <&funnel1_in>;
	1737	+ };
	1738	+ };
	1739	+ };
	1740	+ };
432	1741	kryocc: clock-controller@6400000 {
433	1742	compatible = "qcom,apcc-msm8996";
434		- reg = <0x6400000 0x90000>;
	1743	+ reg = <0x06400000 0x90000>;
435	1744	#clock-cells = <1>;
436	1745	};
	1746	+
	1747	+ usb3: usb@6af8800 {
	1748	+ compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
	1749	+ reg = <0x06af8800 0x400>;
	1750	+ #address-cells = <1>;
	1751	+ #size-cells = <1>;
	1752	+ ranges;
	1753	+
	1754	+ clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
	1755	+ <&gcc GCC_USB30_MASTER_CLK>,
	1756	+ <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
	1757	+ <&gcc GCC_USB30_MOCK_UTMI_CLK>,
	1758	+ <&gcc GCC_USB30_SLEEP_CLK>,
	1759	+ <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
	1760	+
	1761	+ assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
	1762	+ <&gcc GCC_USB30_MASTER_CLK>;
	1763	+ assigned-clock-rates = <19200000>, <120000000>;
	1764	+
	1765	+ power-domains = <&gcc USB30_GDSC>;
	1766	+ status = "disabled";
	1767	+
	1768	+ dwc3@6a00000 {
	1769	+ compatible = "snps,dwc3";
	1770	+ reg = <0x06a00000 0xcc00>;
	1771	+ interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
	1772	+ phys = <&hsusb_phy1>, <&ssusb_phy_0>;
	1773	+ phy-names = "usb2-phy", "usb3-phy";
	1774	+ snps,dis_u2_susphy_quirk;
	1775	+ snps,dis_enblslpm_quirk;
	1776	+ };
	1777	+ };
	1778	+
	1779	+ usb3phy: phy@7410000 {
	1780	+ compatible = "qcom,msm8996-qmp-usb3-phy";
	1781	+ reg = <0x07410000 0x1c4>;
	1782	+ #clock-cells = <1>;
	1783	+ #address-cells = <1>;
	1784	+ #size-cells = <1>;
	1785	+ ranges;
	1786	+
	1787	+ clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
	1788	+ <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
	1789	+ <&gcc GCC_USB3_CLKREF_CLK>;
	1790	+ clock-names = "aux", "cfg_ahb", "ref";
	1791	+
	1792	+ resets = <&gcc GCC_USB3_PHY_BCR>,
	1793	+ <&gcc GCC_USB3PHY_PHY_BCR>;
	1794	+ reset-names = "phy", "common";
	1795	+ status = "disabled";
	1796	+
	1797	+ ssusb_phy_0: lane@7410200 {
	1798	+ reg = <0x07410200 0x200>,
	1799	+ <0x07410400 0x130>,
	1800	+ <0x07410600 0x1a8>;
	1801	+ #phy-cells = <0>;
	1802	+
	1803	+ clock-output-names = "usb3_phy_pipe_clk_src";
	1804	+ clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
	1805	+ clock-names = "pipe0";
	1806	+ };
	1807	+ };
	1808	+
	1809	+ hsusb_phy1: phy@7411000 {
	1810	+ compatible = "qcom,msm8996-qusb2-phy";
	1811	+ reg = <0x07411000 0x180>;
	1812	+ #phy-cells = <0>;
	1813	+
	1814	+ clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
	1815	+ <&gcc GCC_RX1_USB2_CLKREF_CLK>;
	1816	+ clock-names = "cfg_ahb", "ref";
	1817	+
	1818	+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
	1819	+ nvmem-cells = <&qusb2p_hstx_trim>;
	1820	+ status = "disabled";
	1821	+ };
	1822	+
	1823	+ hsusb_phy2: phy@7412000 {
	1824	+ compatible = "qcom,msm8996-qusb2-phy";
	1825	+ reg = <0x07412000 0x180>;
	1826	+ #phy-cells = <0>;
	1827	+
	1828	+ clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
	1829	+ <&gcc GCC_RX2_USB2_CLKREF_CLK>;
	1830	+ clock-names = "cfg_ahb", "ref";
	1831	+
	1832	+ resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
	1833	+ nvmem-cells = <&qusb2s_hstx_trim>;
	1834	+ status = "disabled";
	1835	+ };
	1836	+
	1837	+ sdhc2: sdhci@74a4900 {
	1838	+ status = "disabled";
	1839	+ compatible = "qcom,sdhci-msm-v4";
	1840	+ reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
	1841	+ reg-names = "hc_mem", "core_mem";
	1842	+
	1843	+ interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>,
	1844	+ <0 221 IRQ_TYPE_LEVEL_HIGH>;
	1845	+ interrupt-names = "hc_irq", "pwr_irq";
	1846	+
	1847	+ clock-names = "iface", "core", "xo";
	1848	+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
	1849	+ <&gcc GCC_SDCC2_APPS_CLK>,
	1850	+ <&xo_board>;
	1851	+ bus-width = <4>;
	1852	+ };
437	1853
438	1854	blsp1_uart1: serial@7570000 {
439	1855	compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
..	..	@@ -460,6 +1876,41 @@
460	1876	status = "disabled";
461	1877	};
462	1878
	1879	+ blsp1_i2c2: i2c@7577000 {
	1880	+ compatible = "qcom,i2c-qup-v2.2.1";
	1881	+ reg = <0x07577000 0x1000>;
	1882	+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
	1883	+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
	1884	+ <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
	1885	+ clock-names = "iface", "core";
	1886	+ pinctrl-names = "default", "sleep";
	1887	+ pinctrl-0 = <&blsp1_i2c2_default>;
	1888	+ pinctrl-1 = <&blsp1_i2c2_sleep>;
	1889	+ #address-cells = <1>;
	1890	+ #size-cells = <0>;
	1891	+ status = "disabled";
	1892	+ };
	1893	+
	1894	+ blsp2_uart1: serial@75b0000 {
	1895	+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	1896	+ reg = <0x075b0000 0x1000>;
	1897	+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
	1898	+ clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
	1899	+ <&gcc GCC_BLSP2_AHB_CLK>;
	1900	+ clock-names = "core", "iface";
	1901	+ status = "disabled";
	1902	+ };
	1903	+
	1904	+ blsp2_uart2: serial@75b1000 {
	1905	+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	1906	+ reg = <0x075b1000 0x1000>;
	1907	+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
	1908	+ clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
	1909	+ <&gcc GCC_BLSP2_AHB_CLK>;
	1910	+ clock-names = "core", "iface";
	1911	+ status = "disabled";
	1912	+ };
	1913	+
463	1914	blsp2_i2c0: i2c@75b5000 {
464	1915	compatible = "qcom,i2c-qup-v2.2.1";
465	1916	reg = <0x075b5000 0x1000>;
..	..	@@ -475,16 +1926,6 @@
475	1926	status = "disabled";
476	1927	};
477	1928
478		- blsp2_uart1: serial@75b0000 {
479		- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
480		- reg = <0x75b0000 0x1000>;
481		- interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
482		- clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
483		- <&gcc GCC_BLSP2_AHB_CLK>;
484		- clock-names = "core", "iface";
485		- status = "disabled";
486		- };
487		-
488	1929	blsp2_i2c1: i2c@75b6000 {
489	1930	compatible = "qcom,i2c-qup-v2.2.1";
490	1931	reg = <0x075b6000 0x1000>;
..	..	@@ -495,31 +1936,6 @@
495	1936	pinctrl-names = "default", "sleep";
496	1937	pinctrl-0 = <&blsp2_i2c1_default>;
497	1938	pinctrl-1 = <&blsp2_i2c1_sleep>;
498		- #address-cells = <1>;
499		- #size-cells = <0>;
500		- status = "disabled";
501		- };
502		-
503		- blsp2_uart2: serial@75b1000 {
504		- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
505		- reg = <0x075b1000 0x1000>;
506		- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
507		- clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
508		- <&gcc GCC_BLSP2_AHB_CLK>;
509		- clock-names = "core", "iface";
510		- status = "disabled";
511		- };
512		-
513		- blsp1_i2c2: i2c@7577000 {
514		- compatible = "qcom,i2c-qup-v2.2.1";
515		- reg = <0x07577000 0x1000>;
516		- interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
517		- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
518		- <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
519		- clock-names = "iface", "core";
520		- pinctrl-names = "default", "sleep";
521		- pinctrl-0 = <&blsp1_i2c2_default>;
522		- pinctrl-1 = <&blsp1_i2c2_sleep>;
523	1939	#address-cells = <1>;
524	1940	#size-cells = <0>;
525	1941	status = "disabled";
..	..	@@ -540,31 +1956,176 @@
540	1956	status = "disabled";
541	1957	};
542	1958
543		- sdhc2: sdhci@74a4900 {
544		- status = "disabled";
545		- compatible = "qcom,sdhci-msm-v4";
546		- reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
547		- reg-names = "hc_mem", "core_mem";
	1959	+ usb2: usb@76f8800 {
	1960	+ compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
	1961	+ reg = <0x076f8800 0x400>;
	1962	+ #address-cells = <1>;
	1963	+ #size-cells = <1>;
	1964	+ ranges;
548	1965
549		- interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>,
550		- <0 221 IRQ_TYPE_LEVEL_HIGH>;
551		- interrupt-names = "hc_irq", "pwr_irq";
	1966	+ clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
	1967	+ <&gcc GCC_USB20_MASTER_CLK>,
	1968	+ <&gcc GCC_USB20_MOCK_UTMI_CLK>,
	1969	+ <&gcc GCC_USB20_SLEEP_CLK>,
	1970	+ <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
552	1971
553		- clock-names = "iface", "core", "xo";
554		- clocks = <&gcc GCC_SDCC2_AHB_CLK>,
555		- <&gcc GCC_SDCC2_APPS_CLK>,
556		- <&xo_board>;
557		- bus-width = <4>;
558		- };
	1972	+ assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
	1973	+ <&gcc GCC_USB20_MASTER_CLK>;
	1974	+ assigned-clock-rates = <19200000>, <60000000>;
559	1975
560		- msmgpio: pinctrl@1010000 {
561		- compatible = "qcom,msm8996-pinctrl";
562		- reg = <0x01010000 0x300000>;
563		- interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
564		- gpio-controller;
565		- #gpio-cells = <2>;
566		- interrupt-controller;
567		- #interrupt-cells = <2>;
	1976	+ power-domains = <&gcc USB30_GDSC>;
	1977	+ status = "disabled";
	1978	+
	1979	+ dwc3@7600000 {
	1980	+ compatible = "snps,dwc3";
	1981	+ reg = <0x07600000 0xcc00>;
	1982	+ interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
	1983	+ phys = <&hsusb_phy2>;
	1984	+ phy-names = "usb2-phy";
	1985	+ snps,dis_u2_susphy_quirk;
	1986	+ snps,dis_enblslpm_quirk;
	1987	+ };
	1988	+ };
	1989	+
	1990	+ slimbam: dma@9184000 {
	1991	+ compatible = "qcom,bam-v1.7.0";
	1992	+ qcom,controlled-remotely;
	1993	+ reg = <0x09184000 0x32000>;
	1994	+ num-channels = <31>;
	1995	+ interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
	1996	+ #dma-cells = <1>;
	1997	+ qcom,ee = <1>;
	1998	+ qcom,num-ees = <2>;
	1999	+ };
	2000	+
	2001	+ slim_msm: slim@91c0000 {
	2002	+ compatible = "qcom,slim-ngd-v1.5.0";
	2003	+ reg = <0x091c0000 0x2C000>;
	2004	+ reg-names = "ctrl";
	2005	+ interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
	2006	+ dmas = <&slimbam 3>, <&slimbam 4>,
	2007	+ <&slimbam 5>, <&slimbam 6>;
	2008	+ dma-names = "rx", "tx", "tx2", "rx2";
	2009	+ #address-cells = <1>;
	2010	+ #size-cells = <0>;
	2011	+ ngd@1 {
	2012	+ reg = <1>;
	2013	+ #address-cells = <1>;
	2014	+ #size-cells = <1>;
	2015	+
	2016	+ tasha_ifd: tas-ifd {
	2017	+ compatible = "slim217,1a0";
	2018	+ reg = <0 0>;
	2019	+ };
	2020	+
	2021	+ wcd9335: codec@1{
	2022	+ pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
	2023	+ pinctrl-names = "default";
	2024	+
	2025	+ compatible = "slim217,1a0";
	2026	+ reg = <1 0>;
	2027	+
	2028	+ interrupt-parent = <&msmgpio>;
	2029	+ interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
	2030	+ <53 IRQ_TYPE_LEVEL_HIGH>;
	2031	+ interrupt-names = "intr1", "intr2";
	2032	+ interrupt-controller;
	2033	+ #interrupt-cells = <1>;
	2034	+ reset-gpios = <&msmgpio 64 0>;
	2035	+
	2036	+ slim-ifc-dev = <&tasha_ifd>;
	2037	+
	2038	+ #sound-dai-cells = <1>;
	2039	+ };
	2040	+ };
	2041	+ };
	2042	+
	2043	+ adsp_pil: remoteproc@9300000 {
	2044	+ compatible = "qcom,msm8996-adsp-pil";
	2045	+ reg = <0x09300000 0x80000>;
	2046	+
	2047	+ interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
	2048	+ <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
	2049	+ <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
	2050	+ <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
	2051	+ <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
	2052	+ interrupt-names = "wdog", "fatal", "ready",
	2053	+ "handover", "stop-ack";
	2054	+
	2055	+ clocks = <&xo_board>;
	2056	+ clock-names = "xo";
	2057	+
	2058	+ memory-region = <&adsp_region>;
	2059	+
	2060	+ qcom,smem-states = <&smp2p_adsp_out 0>;
	2061	+ qcom,smem-state-names = "stop";
	2062	+
	2063	+ smd-edge {
	2064	+ interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
	2065	+
	2066	+ label = "lpass";
	2067	+ mboxes = <&apcs_glb 8>;
	2068	+ qcom,smd-edge = <1>;
	2069	+ qcom,remote-pid = <2>;
	2070	+ #address-cells = <1>;
	2071	+ #size-cells = <0>;
	2072	+ apr {
	2073	+ power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
	2074	+ compatible = "qcom,apr-v2";
	2075	+ qcom,smd-channels = "apr_audio_svc";
	2076	+ qcom,apr-domain = <APR_DOMAIN_ADSP>;
	2077	+ #address-cells = <1>;
	2078	+ #size-cells = <0>;
	2079	+
	2080	+ q6core {
	2081	+ reg = <APR_SVC_ADSP_CORE>;
	2082	+ compatible = "qcom,q6core";
	2083	+ };
	2084	+
	2085	+ q6afe: q6afe {
	2086	+ compatible = "qcom,q6afe";
	2087	+ reg = <APR_SVC_AFE>;
	2088	+ q6afedai: dais {
	2089	+ compatible = "qcom,q6afe-dais";
	2090	+ #address-cells = <1>;
	2091	+ #size-cells = <0>;
	2092	+ #sound-dai-cells = <1>;
	2093	+ hdmi@1 {
	2094	+ reg = <1>;
	2095	+ };
	2096	+ };
	2097	+ };
	2098	+
	2099	+ q6asm: q6asm {
	2100	+ compatible = "qcom,q6asm";
	2101	+ reg = <APR_SVC_ASM>;
	2102	+ q6asmdai: dais {
	2103	+ compatible = "qcom,q6asm-dais";
	2104	+ #address-cells = <1>;
	2105	+ #size-cells = <0>;
	2106	+ #sound-dai-cells = <1>;
	2107	+ iommus = <&lpass_q6_smmu 1>;
	2108	+ };
	2109	+ };
	2110	+
	2111	+ q6adm: q6adm {
	2112	+ compatible = "qcom,q6adm";
	2113	+ reg = <APR_SVC_ADM>;
	2114	+ q6routing: routing {
	2115	+ compatible = "qcom,q6adm-routing";
	2116	+ #sound-dai-cells = <0>;
	2117	+ };
	2118	+ };
	2119	+ };
	2120	+
	2121	+ };
	2122	+ };
	2123	+
	2124	+ apcs_glb: mailbox@9820000 {
	2125	+ compatible = "qcom,msm8996-apcs-hmss-global";
	2126	+ reg = <0x09820000 0x1000>;
	2127	+
	2128	+ #mbox-cells = <1>;
568	2129	};
569	2130
570	2131	timer@9840000 {
..	..	@@ -626,600 +2187,268 @@
626	2187	};
627	2188	};
628	2189
629		- spmi_bus: qcom,spmi@400f000 {
630		- compatible = "qcom,spmi-pmic-arb";
631		- reg = <0x400f000 0x1000>,
632		- <0x4400000 0x800000>,
633		- <0x4c00000 0x800000>,
634		- <0x5800000 0x200000>,
635		- <0x400a000 0x002100>;
636		- reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
637		- interrupt-names = "periph_irq";
638		- interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
639		- qcom,ee = <0>;
640		- qcom,channel = <0>;
641		- #address-cells = <2>;
642		- #size-cells = <0>;
	2190	+ saw3: syscon@9a10000 {
	2191	+ compatible = "syscon";
	2192	+ reg = <0x09a10000 0x1000>;
	2193	+ };
	2194	+
	2195	+ intc: interrupt-controller@9bc0000 {
	2196	+ compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
	2197	+ #interrupt-cells = <3>;
643	2198	interrupt-controller;
644		- #interrupt-cells = <4>;
	2199	+ #redistributor-regions = <1>;
	2200	+ redistributor-stride = <0x0 0x40000>;
	2201	+ reg = <0x09bc0000 0x10000>,
	2202	+ <0x09c00000 0x100000>;
	2203	+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
645	2204	};
	2205	+ };
646	2206
647		- ufsphy: phy@627000 {
648		- compatible = "qcom,msm8996-ufs-phy-qmp-14nm";
649		- reg = <0x627000 0xda8>;
650		- reg-names = "phy_mem";
651		- #phy-cells = <0>;
	2207	+ sound: sound {
	2208	+ };
652	2209
653		- vdda-phy-supply = <&pm8994_l28>;
654		- vdda-pll-supply = <&pm8994_l12>;
	2210	+ thermal-zones {
	2211	+ cpu0-thermal {
	2212	+ polling-delay-passive = <250>;
	2213	+ polling-delay = <1000>;
655	2214
656		- vdda-phy-max-microamp = <18380>;
657		- vdda-pll-max-microamp = <9440>;
	2215	+ thermal-sensors = <&tsens0 3>;
658	2216
659		- vddp-ref-clk-supply = <&pm8994_l25>;
660		- vddp-ref-clk-max-microamp = <100>;
661		- vddp-ref-clk-always-on;
	2217	+ trips {
	2218	+ cpu0_alert0: trip-point0 {
	2219	+ temperature = <75000>;
	2220	+ hysteresis = <2000>;
	2221	+ type = "passive";
	2222	+ };
662	2223
663		- clock-names = "ref_clk_src", "ref_clk";
664		- clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
665		- <&gcc GCC_UFS_CLKREF_CLK>;
666		- status = "disabled";
667		- };
668		-
669		- ufshc@624000 {
670		- compatible = "qcom,ufshc";
671		- reg = <0x624000 0x2500>;
672		- interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
673		-
674		- phys = <&ufsphy>;
675		- phy-names = "ufsphy";
676		-
677		- vcc-supply = <&pm8994_l20>;
678		- vccq-supply = <&pm8994_l25>;
679		- vccq2-supply = <&pm8994_s4>;
680		-
681		- vcc-max-microamp = <600000>;
682		- vccq-max-microamp = <450000>;
683		- vccq2-max-microamp = <450000>;
684		-
685		- power-domains = <&gcc UFS_GDSC>;
686		-
687		- clock-names =
688		- "core_clk_src",
689		- "core_clk",
690		- "bus_clk",
691		- "bus_aggr_clk",
692		- "iface_clk",
693		- "core_clk_unipro_src",
694		- "core_clk_unipro",
695		- "core_clk_ice",
696		- "ref_clk",
697		- "tx_lane0_sync_clk",
698		- "rx_lane0_sync_clk";
699		- clocks =
700		- <&gcc UFS_AXI_CLK_SRC>,
701		- <&gcc GCC_UFS_AXI_CLK>,
702		- <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
703		- <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
704		- <&gcc GCC_UFS_AHB_CLK>,
705		- <&gcc UFS_ICE_CORE_CLK_SRC>,
706		- <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
707		- <&gcc GCC_UFS_ICE_CORE_CLK>,
708		- <&rpmcc RPM_SMD_LN_BB_CLK>,
709		- <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
710		- <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
711		- freq-table-hz =
712		- <100000000 200000000>,
713		- <0 0>,
714		- <0 0>,
715		- <0 0>,
716		- <0 0>,
717		- <150000000 300000000>,
718		- <0 0>,
719		- <0 0>,
720		- <0 0>,
721		- <0 0>,
722		- <0 0>;
723		-
724		- lanes-per-direction = <1>;
725		- status = "disabled";
726		-
727		- ufs_variant {
728		- compatible = "qcom,ufs_variant";
	2224	+ cpu0_crit: cpu_crit {
	2225	+ temperature = <110000>;
	2226	+ hysteresis = <2000>;
	2227	+ type = "critical";
	2228	+ };
729	2229	};
730	2230	};
731	2231
732		- mmcc: clock-controller@8c0000 {
733		- compatible = "qcom,mmcc-msm8996";
734		- #clock-cells = <1>;
735		- #reset-cells = <1>;
736		- #power-domain-cells = <1>;
737		- reg = <0x8c0000 0x40000>;
738		- assigned-clocks = <&mmcc MMPLL9_PLL>,
739		- <&mmcc MMPLL1_PLL>,
740		- <&mmcc MMPLL3_PLL>,
741		- <&mmcc MMPLL4_PLL>,
742		- <&mmcc MMPLL5_PLL>;
743		- assigned-clock-rates = <624000000>,
744		- <810000000>,
745		- <980000000>,
746		- <960000000>,
747		- <825000000>;
748		- };
	2232	+ cpu1-thermal {
	2233	+ polling-delay-passive = <250>;
	2234	+ polling-delay = <1000>;
749	2235
750		- qfprom@74000 {
751		- compatible = "qcom,qfprom";
752		- reg = <0x74000 0x8ff>;
753		- #address-cells = <1>;
754		- #size-cells = <1>;
	2236	+ thermal-sensors = <&tsens0 5>;
755	2237
756		- qusb2p_hstx_trim: hstx_trim@24e {
757		- reg = <0x24e 0x2>;
758		- bits = <5 4>;
759		- };
	2238	+ trips {
	2239	+ cpu1_alert0: trip-point0 {
	2240	+ temperature = <75000>;
	2241	+ hysteresis = <2000>;
	2242	+ type = "passive";
	2243	+ };
760	2244
761		- qusb2s_hstx_trim: hstx_trim@24f {
762		- reg = <0x24f 0x1>;
763		- bits = <1 4>;
	2245	+ cpu1_crit: cpu_crit {
	2246	+ temperature = <110000>;
	2247	+ hysteresis = <2000>;
	2248	+ type = "critical";
	2249	+ };
764	2250	};
765	2251	};
766	2252
767		- phy@34000 {
768		- compatible = "qcom,msm8996-qmp-pcie-phy";
769		- reg = <0x34000 0x488>;
770		- #clock-cells = <1>;
771		- #address-cells = <1>;
772		- #size-cells = <1>;
773		- ranges;
	2253	+ cpu2-thermal {
	2254	+ polling-delay-passive = <250>;
	2255	+ polling-delay = <1000>;
774	2256
775		- clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
776		- <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
777		- <&gcc GCC_PCIE_CLKREF_CLK>;
778		- clock-names = "aux", "cfg_ahb", "ref";
	2257	+ thermal-sensors = <&tsens0 8>;
779	2258
780		- vdda-phy-supply = <&pm8994_l28>;
781		- vdda-pll-supply = <&pm8994_l12>;
	2259	+ trips {
	2260	+ cpu2_alert0: trip-point0 {
	2261	+ temperature = <75000>;
	2262	+ hysteresis = <2000>;
	2263	+ type = "passive";
	2264	+ };
782	2265
783		- resets = <&gcc GCC_PCIE_PHY_BCR>,
784		- <&gcc GCC_PCIE_PHY_COM_BCR>,
785		- <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
786		- reset-names = "phy", "common", "cfg";
787		- status = "disabled";
788		-
789		- pciephy_0: lane@35000 {
790		- reg = <0x035000 0x130>,
791		- <0x035200 0x200>,
792		- <0x035400 0x1dc>;
793		- #phy-cells = <0>;
794		-
795		- clock-output-names = "pcie_0_pipe_clk_src";
796		- clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
797		- clock-names = "pipe0";
798		- resets = <&gcc GCC_PCIE_0_PHY_BCR>;
799		- reset-names = "lane0";
800		- };
801		-
802		- pciephy_1: lane@36000 {
803		- reg = <0x036000 0x130>,
804		- <0x036200 0x200>,
805		- <0x036400 0x1dc>;
806		- #phy-cells = <0>;
807		-
808		- clock-output-names = "pcie_1_pipe_clk_src";
809		- clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
810		- clock-names = "pipe1";
811		- resets = <&gcc GCC_PCIE_1_PHY_BCR>;
812		- reset-names = "lane1";
813		- };
814		-
815		- pciephy_2: lane@37000 {
816		- reg = <0x037000 0x130>,
817		- <0x037200 0x200>,
818		- <0x037400 0x1dc>;
819		- #phy-cells = <0>;
820		-
821		- clock-output-names = "pcie_2_pipe_clk_src";
822		- clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
823		- clock-names = "pipe2";
824		- resets = <&gcc GCC_PCIE_2_PHY_BCR>;
825		- reset-names = "lane2";
	2266	+ cpu2_crit: cpu_crit {
	2267	+ temperature = <110000>;
	2268	+ hysteresis = <2000>;
	2269	+ type = "critical";
	2270	+ };
826	2271	};
827	2272	};
828	2273
829		- phy@7410000 {
830		- compatible = "qcom,msm8996-qmp-usb3-phy";
831		- reg = <0x7410000 0x1c4>;
832		- #clock-cells = <1>;
833		- #address-cells = <1>;
834		- #size-cells = <1>;
835		- ranges;
	2274	+ cpu3-thermal {
	2275	+ polling-delay-passive = <250>;
	2276	+ polling-delay = <1000>;
836	2277
837		- clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
838		- <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
839		- <&gcc GCC_USB3_CLKREF_CLK>;
840		- clock-names = "aux", "cfg_ahb", "ref";
	2278	+ thermal-sensors = <&tsens0 10>;
841	2279
842		- vdda-phy-supply = <&pm8994_l28>;
843		- vdda-pll-supply = <&pm8994_l12>;
	2280	+ trips {
	2281	+ cpu3_alert0: trip-point0 {
	2282	+ temperature = <75000>;
	2283	+ hysteresis = <2000>;
	2284	+ type = "passive";
	2285	+ };
844	2286
845		- resets = <&gcc GCC_USB3_PHY_BCR>,
846		- <&gcc GCC_USB3PHY_PHY_BCR>;
847		- reset-names = "phy", "common";
848		- status = "disabled";
849		-
850		- ssusb_phy_0: lane@7410200 {
851		- reg = <0x7410200 0x200>,
852		- <0x7410400 0x130>,
853		- <0x7410600 0x1a8>;
854		- #phy-cells = <0>;
855		-
856		- clock-output-names = "usb3_phy_pipe_clk_src";
857		- clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
858		- clock-names = "pipe0";
	2287	+ cpu3_crit: cpu_crit {
	2288	+ temperature = <110000>;
	2289	+ hysteresis = <2000>;
	2290	+ type = "critical";
	2291	+ };
859	2292	};
860	2293	};
861	2294
862		- hsusb_phy1: phy@7411000 {
863		- compatible = "qcom,msm8996-qusb2-phy";
864		- reg = <0x7411000 0x180>;
865		- #phy-cells = <0>;
	2295	+ gpu-thermal-top {
	2296	+ polling-delay-passive = <250>;
	2297	+ polling-delay = <1000>;
866	2298
867		- clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
868		- <&gcc GCC_RX1_USB2_CLKREF_CLK>;
869		- clock-names = "cfg_ahb", "ref";
	2299	+ thermal-sensors = <&tsens1 6>;
870	2300
871		- vdda-pll-supply = <&pm8994_l12>;
872		- vdda-phy-dpdm-supply = <&pm8994_l24>;
873		-
874		- resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
875		- nvmem-cells = <&qusb2p_hstx_trim>;
876		- status = "disabled";
877		- };
878		-
879		- hsusb_phy2: phy@7412000 {
880		- compatible = "qcom,msm8996-qusb2-phy";
881		- reg = <0x7412000 0x180>;
882		- #phy-cells = <0>;
883		-
884		- clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
885		- <&gcc GCC_RX2_USB2_CLKREF_CLK>;
886		- clock-names = "cfg_ahb", "ref";
887		-
888		- vdda-pll-supply = <&pm8994_l12>;
889		- vdda-phy-dpdm-supply = <&pm8994_l24>;
890		-
891		- resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
892		- nvmem-cells = <&qusb2s_hstx_trim>;
893		- status = "disabled";
894		- };
895		-
896		- usb2: usb@7600000 {
897		- compatible = "qcom,dwc3";
898		- #address-cells = <1>;
899		- #size-cells = <1>;
900		- ranges;
901		-
902		- clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
903		- <&gcc GCC_USB20_MASTER_CLK>,
904		- <&gcc GCC_USB20_MOCK_UTMI_CLK>,
905		- <&gcc GCC_USB20_SLEEP_CLK>,
906		- <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
907		-
908		- assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
909		- <&gcc GCC_USB20_MASTER_CLK>;
910		- assigned-clock-rates = <19200000>, <60000000>;
911		-
912		- power-domains = <&gcc USB30_GDSC>;
913		- status = "disabled";
914		-
915		- dwc3@7600000 {
916		- compatible = "snps,dwc3";
917		- reg = <0x7600000 0xcc00>;
918		- interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
919		- phys = <&hsusb_phy2>;
920		- phy-names = "usb2-phy";
921		- snps,dis_u2_susphy_quirk;
922		- snps,dis_enblslpm_quirk;
	2301	+ trips {
	2302	+ gpu1_alert0: trip-point0 {
	2303	+ temperature = <90000>;
	2304	+ hysteresis = <2000>;
	2305	+ type = "hot";
	2306	+ };
923	2307	};
924	2308	};
925	2309
926		- usb3: usb@6a00000 {
927		- compatible = "qcom,dwc3";
928		- #address-cells = <1>;
929		- #size-cells = <1>;
930		- ranges;
	2310	+ gpu-thermal-bottom {
	2311	+ polling-delay-passive = <250>;
	2312	+ polling-delay = <1000>;
931	2313
932		- clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
933		- <&gcc GCC_USB30_MASTER_CLK>,
934		- <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
935		- <&gcc GCC_USB30_MOCK_UTMI_CLK>,
936		- <&gcc GCC_USB30_SLEEP_CLK>,
937		- <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
	2314	+ thermal-sensors = <&tsens1 7>;
938	2315
939		- assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
940		- <&gcc GCC_USB30_MASTER_CLK>;
941		- assigned-clock-rates = <19200000>, <120000000>;
942		-
943		- power-domains = <&gcc USB30_GDSC>;
944		- status = "disabled";
945		-
946		- dwc3@6a00000 {
947		- compatible = "snps,dwc3";
948		- reg = <0x6a00000 0xcc00>;
949		- interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
950		- phys = <&hsusb_phy1>, <&ssusb_phy_0>;
951		- phy-names = "usb2-phy", "usb3-phy";
952		- snps,dis_u2_susphy_quirk;
953		- snps,dis_enblslpm_quirk;
	2316	+ trips {
	2317	+ gpu2_alert0: trip-point0 {
	2318	+ temperature = <90000>;
	2319	+ hysteresis = <2000>;
	2320	+ type = "hot";
	2321	+ };
954	2322	};
955	2323	};
956	2324
957		- agnoc@0 {
958		- power-domains = <&gcc AGGRE0_NOC_GDSC>;
959		- compatible = "simple-pm-bus";
960		- #address-cells = <1>;
961		- #size-cells = <1>;
962		- ranges;
	2325	+ m4m-thermal {
	2326	+ polling-delay-passive = <250>;
	2327	+ polling-delay = <1000>;
963	2328
964		- pcie0: pcie@600000 {
965		- compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
966		- status = "disabled";
967		- power-domains = <&gcc PCIE0_GDSC>;
968		- bus-range = <0x00 0xff>;
969		- num-lanes = <1>;
	2329	+ thermal-sensors = <&tsens0 1>;
970	2330
971		- reg = <0x00600000 0x2000>,
972		- <0x0c000000 0xf1d>,
973		- <0x0c000f20 0xa8>,
974		- <0x0c100000 0x100000>;
975		- reg-names = "parf", "dbi", "elbi","config";
976		-
977		- phys = <&pciephy_0>;
978		- phy-names = "pciephy";
979		-
980		- #address-cells = <3>;
981		- #size-cells = <2>;
982		- ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
983		- <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
984		-
985		- interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
986		- interrupt-names = "msi";
987		- #interrupt-cells = <1>;
988		- interrupt-map-mask = <0 0 0 0x7>;
989		- interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
990		- <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
991		- <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
992		- <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
993		-
994		- pinctrl-names = "default", "sleep";
995		- pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>;
996		- pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>;
997		-
998		-
999		- vdda-supply = <&pm8994_l28>;
1000		-
1001		- linux,pci-domain = <0>;
1002		-
1003		- clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1004		- <&gcc GCC_PCIE_0_AUX_CLK>,
1005		- <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1006		- <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1007		- <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1008		-
1009		- clock-names = "pipe",
1010		- "aux",
1011		- "cfg",
1012		- "bus_master",
1013		- "bus_slave";
1014		-
	2331	+ trips {
	2332	+ m4m_alert0: trip-point0 {
	2333	+ temperature = <90000>;
	2334	+ hysteresis = <2000>;
	2335	+ type = "hot";
	2336	+ };
1015	2337	};
	2338	+ };
1016	2339
1017		- pcie1: pcie@608000 {
1018		- compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1019		- power-domains = <&gcc PCIE1_GDSC>;
1020		- bus-range = <0x00 0xff>;
1021		- num-lanes = <1>;
	2340	+ l3-or-venus-thermal {
	2341	+ polling-delay-passive = <250>;
	2342	+ polling-delay = <1000>;
1022	2343
1023		- status = "disabled";
	2344	+ thermal-sensors = <&tsens0 2>;
1024	2345
1025		- reg = <0x00608000 0x2000>,
1026		- <0x0d000000 0xf1d>,
1027		- <0x0d000f20 0xa8>,
1028		- <0x0d100000 0x100000>;
1029		-
1030		- reg-names = "parf", "dbi", "elbi","config";
1031		-
1032		- phys = <&pciephy_1>;
1033		- phy-names = "pciephy";
1034		-
1035		- #address-cells = <3>;
1036		- #size-cells = <2>;
1037		- ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
1038		- <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
1039		-
1040		- interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
1041		- interrupt-names = "msi";
1042		- #interrupt-cells = <1>;
1043		- interrupt-map-mask = <0 0 0 0x7>;
1044		- interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1045		- <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1046		- <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1047		- <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1048		-
1049		- pinctrl-names = "default", "sleep";
1050		- pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>;
1051		- pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>;
1052		-
1053		-
1054		- vdda-supply = <&pm8994_l28>;
1055		- linux,pci-domain = <1>;
1056		-
1057		- clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1058		- <&gcc GCC_PCIE_1_AUX_CLK>,
1059		- <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1060		- <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1061		- <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
1062		-
1063		- clock-names = "pipe",
1064		- "aux",
1065		- "cfg",
1066		- "bus_master",
1067		- "bus_slave";
	2346	+ trips {
	2347	+ l3_or_venus_alert0: trip-point0 {
	2348	+ temperature = <90000>;
	2349	+ hysteresis = <2000>;
	2350	+ type = "hot";
	2351	+ };
1068	2352	};
	2353	+ };
1069	2354
1070		- pcie2: pcie@610000 {
1071		- compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1072		- power-domains = <&gcc PCIE2_GDSC>;
1073		- bus-range = <0x00 0xff>;
1074		- num-lanes = <1>;
1075		- status = "disabled";
1076		- reg = <0x00610000 0x2000>,
1077		- <0x0e000000 0xf1d>,
1078		- <0x0e000f20 0xa8>,
1079		- <0x0e100000 0x100000>;
	2355	+ cluster0-l2-thermal {
	2356	+ polling-delay-passive = <250>;
	2357	+ polling-delay = <1000>;
1080	2358
1081		- reg-names = "parf", "dbi", "elbi","config";
	2359	+ thermal-sensors = <&tsens0 7>;
1082	2360
1083		- phys = <&pciephy_2>;
1084		- phy-names = "pciephy";
	2361	+ trips {
	2362	+ cluster0_l2_alert0: trip-point0 {
	2363	+ temperature = <90000>;
	2364	+ hysteresis = <2000>;
	2365	+ type = "hot";
	2366	+ };
	2367	+ };
	2368	+ };
1085	2369
1086		- #address-cells = <3>;
1087		- #size-cells = <2>;
1088		- ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
1089		- <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
	2370	+ cluster1-l2-thermal {
	2371	+ polling-delay-passive = <250>;
	2372	+ polling-delay = <1000>;
1090	2373
1091		- device_type = "pci";
	2374	+ thermal-sensors = <&tsens0 12>;
1092	2375
1093		- interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
1094		- interrupt-names = "msi";
1095		- #interrupt-cells = <1>;
1096		- interrupt-map-mask = <0 0 0 0x7>;
1097		- interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1098		- <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1099		- <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1100		- <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
	2376	+ trips {
	2377	+ cluster1_l2_alert0: trip-point0 {
	2378	+ temperature = <90000>;
	2379	+ hysteresis = <2000>;
	2380	+ type = "hot";
	2381	+ };
	2382	+ };
	2383	+ };
1101	2384
1102		- pinctrl-names = "default", "sleep";
1103		- pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>;
1104		- pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >;
	2385	+ camera-thermal {
	2386	+ polling-delay-passive = <250>;
	2387	+ polling-delay = <1000>;
1105	2388
1106		- vdda-supply = <&pm8994_l28>;
	2389	+ thermal-sensors = <&tsens1 1>;
1107	2390
1108		- linux,pci-domain = <2>;
1109		- clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
1110		- <&gcc GCC_PCIE_2_AUX_CLK>,
1111		- <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
1112		- <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
1113		- <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
	2391	+ trips {
	2392	+ camera_alert0: trip-point0 {
	2393	+ temperature = <90000>;
	2394	+ hysteresis = <2000>;
	2395	+ type = "hot";
	2396	+ };
	2397	+ };
	2398	+ };
1114	2399
1115		- clock-names = "pipe",
1116		- "aux",
1117		- "cfg",
1118		- "bus_master",
1119		- "bus_slave";
	2400	+ q6-dsp-thermal {
	2401	+ polling-delay-passive = <250>;
	2402	+ polling-delay = <1000>;
	2403	+
	2404	+ thermal-sensors = <&tsens1 2>;
	2405	+
	2406	+ trips {
	2407	+ q6_dsp_alert0: trip-point0 {
	2408	+ temperature = <90000>;
	2409	+ hysteresis = <2000>;
	2410	+ type = "hot";
	2411	+ };
	2412	+ };
	2413	+ };
	2414	+
	2415	+ mem-thermal {
	2416	+ polling-delay-passive = <250>;
	2417	+ polling-delay = <1000>;
	2418	+
	2419	+ thermal-sensors = <&tsens1 3>;
	2420	+
	2421	+ trips {
	2422	+ mem_alert0: trip-point0 {
	2423	+ temperature = <90000>;
	2424	+ hysteresis = <2000>;
	2425	+ type = "hot";
	2426	+ };
	2427	+ };
	2428	+ };
	2429	+
	2430	+ modemtx-thermal {
	2431	+ polling-delay-passive = <250>;
	2432	+ polling-delay = <1000>;
	2433	+
	2434	+ thermal-sensors = <&tsens1 4>;
	2435	+
	2436	+ trips {
	2437	+ modemtx_alert0: trip-point0 {
	2438	+ temperature = <90000>;
	2439	+ hysteresis = <2000>;
	2440	+ type = "hot";
	2441	+ };
1120	2442	};
1121	2443	};
1122	2444	};
1123	2445
1124		- adsp-pil {
1125		- compatible = "qcom,msm8996-adsp-pil";
1126		-
1127		- interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
1128		- <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1129		- <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1130		- <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1131		- <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1132		- interrupt-names = "wdog", "fatal", "ready",
1133		- "handover", "stop-ack";
1134		-
1135		- clocks = <&xo_board>;
1136		- clock-names = "xo";
1137		-
1138		- memory-region = <&adsp_region>;
1139		-
1140		- qcom,smem-states = <&adsp_smp2p_out 0>;
1141		- qcom,smem-state-names = "stop";
1142		-
1143		- smd-edge {
1144		- interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
1145		-
1146		- label = "lpass";
1147		- qcom,ipc = <&apcs 16 8>;
1148		- qcom,smd-edge = <1>;
1149		- qcom,remote-pid = <2>;
1150		- };
	2446	+ timer {
	2447	+ compatible = "arm,armv8-timer";
	2448	+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
	2449	+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
	2450	+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
	2451	+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
1151	2452	};
1152		-
1153		- adsp-smp2p {
1154		- compatible = "qcom,smp2p";
1155		- qcom,smem = <443>, <429>;
1156		-
1157		- interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
1158		-
1159		- qcom,ipc = <&apcs 16 10>;
1160		-
1161		- qcom,local-pid = <0>;
1162		- qcom,remote-pid = <2>;
1163		-
1164		- adsp_smp2p_out: master-kernel {
1165		- qcom,entry-name = "master-kernel";
1166		- #qcom,smem-state-cells = <1>;
1167		- };
1168		-
1169		- adsp_smp2p_in: slave-kernel {
1170		- qcom,entry-name = "slave-kernel";
1171		-
1172		- interrupt-controller;
1173		- #interrupt-cells = <2>;
1174		- };
1175		- };
1176		-
1177		- modem-smp2p {
1178		- compatible = "qcom,smp2p";
1179		- qcom,smem = <435>, <428>;
1180		-
1181		- interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
1182		-
1183		- qcom,ipc = <&apcs 16 14>;
1184		-
1185		- qcom,local-pid = <0>;
1186		- qcom,remote-pid = <1>;
1187		-
1188		- modem_smp2p_out: master-kernel {
1189		- qcom,entry-name = "master-kernel";
1190		- #qcom,smem-state-cells = <1>;
1191		- };
1192		-
1193		- modem_smp2p_in: slave-kernel {
1194		- qcom,entry-name = "slave-kernel";
1195		-
1196		- interrupt-controller;
1197		- #interrupt-cells = <2>;
1198		- };
1199		- };
1200		-
1201		- smp2p-slpi {
1202		- compatible = "qcom,smp2p";
1203		- qcom,smem = <481>, <430>;
1204		-
1205		- interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
1206		-
1207		- qcom,ipc = <&apcs 16 26>;
1208		-
1209		- qcom,local-pid = <0>;
1210		- qcom,remote-pid = <3>;
1211		-
1212		- slpi_smp2p_in: slave-kernel {
1213		- qcom,entry-name = "slave-kernel";
1214		- interrupt-controller;
1215		- #interrupt-cells = <2>;
1216		- };
1217		-
1218		- slpi_smp2p_out: master-kernel {
1219		- qcom,entry-name = "master-kernel";
1220		- #qcom,smem-state-cells = <1>;
1221		- };
1222		- };
1223		-
1224	2453	};
1225	2454	#include "msm8996-pins.dtsi"