add dts config

hc

2023-12-06 08f87f769b595151be1afeff53e144f543faa614

 kernel/arch/arm64/boot/dts/qcom/ipq8074.dtsi
..
..
@@ -1,14 +1,6 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 and
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- * only version 2 as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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4
  */
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5
 
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 #include <dt-bindings/interrupt-controller/arm-gic.h>
..
..
@@ -18,17 +10,199 @@
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 	model = "Qualcomm Technologies, Inc. IPQ8074";
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 	compatible = "qcom,ipq8074";
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12
 
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+	clocks {
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+		sleep_clk: sleep_clk {
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+			compatible = "fixed-clock";
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+			clock-frequency = <32768>;
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+			#clock-cells = <0>;
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+		};
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+
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+		xo: xo {
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+			compatible = "fixed-clock";
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+			clock-frequency = <19200000>;
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+			#clock-cells = <0>;
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+		};
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+	};
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+
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+	cpus {
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+		#address-cells = <0x1>;
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+		#size-cells = <0x0>;
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+
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+		CPU0: cpu@0 {
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+			device_type = "cpu";
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+			compatible = "arm,cortex-a53";
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+			reg = <0x0>;
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+			next-level-cache = <&L2_0>;
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+			enable-method = "psci";
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+		};
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+
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+		CPU1: cpu@1 {
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+			device_type = "cpu";
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+			compatible = "arm,cortex-a53";
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+			enable-method = "psci";
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+			reg = <0x1>;
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+			next-level-cache = <&L2_0>;
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+		};
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+
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+		CPU2: cpu@2 {
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+			device_type = "cpu";
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+			compatible = "arm,cortex-a53";
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+			enable-method = "psci";
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+			reg = <0x2>;
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+			next-level-cache = <&L2_0>;
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+		};
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+
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+		CPU3: cpu@3 {
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+			device_type = "cpu";
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+			compatible = "arm,cortex-a53";
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+			enable-method = "psci";
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+			reg = <0x3>;
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+			next-level-cache = <&L2_0>;
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+		};
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+
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+		L2_0: l2-cache {
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+			compatible = "cache";
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+			cache-level = <0x2>;
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+		};
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+	};
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+
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+	pmu {
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+		compatible = "arm,cortex-a53-pmu";
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+		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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+	};
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+
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+	psci {
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+		compatible = "arm,psci-1.0";
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+		method = "smc";
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+	};
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+
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 	soc: soc {
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 		#address-cells = <0x1>;
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 		#size-cells = <0x1>;
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 		ranges = <0 0 0 0xffffffff>;
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 		compatible = "simple-bus";
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84
 
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+		ssphy_1: phy@58000 {
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+			compatible = "qcom,ipq8074-qmp-usb3-phy";
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+			reg = <0x00058000 0x1c4>;
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+			#clock-cells = <1>;
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+			#address-cells = <1>;
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+			#size-cells = <1>;
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+			ranges;
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+
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+			clocks = <&gcc GCC_USB1_AUX_CLK>,
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+				<&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
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+				<&xo>;
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+			clock-names = "aux", "cfg_ahb", "ref";
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+
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+			resets =  <&gcc GCC_USB1_PHY_BCR>,
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+				<&gcc GCC_USB3PHY_1_PHY_BCR>;
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+			reset-names = "phy","common";
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+			status = "disabled";
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+
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+			usb1_ssphy: lane@58200 {
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+				reg = <0x00058200 0x130>,       /* Tx */
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+				      <0x00058400 0x200>,     /* Rx */
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+				      <0x00058800 0x1f8>,     /* PCS  */
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+				      <0x00058600 0x044>;     /* PCS misc*/
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+				#phy-cells = <0>;
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+				clocks = <&gcc GCC_USB1_PIPE_CLK>;
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+				clock-names = "pipe0";
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+				clock-output-names = "gcc_usb1_pipe_clk_src";
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+			};
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+		};
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+
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+		qusb_phy_1: phy@59000 {
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+			compatible = "qcom,ipq8074-qusb2-phy";
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+			reg = <0x00059000 0x180>;
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+			#phy-cells = <0>;
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+
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+			clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
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+				 <&xo>;
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+			clock-names = "cfg_ahb", "ref";
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+
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+			resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
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+			status = "disabled";
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+		};
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+
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+		ssphy_0: phy@78000 {
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+			compatible = "qcom,ipq8074-qmp-usb3-phy";
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+			reg = <0x00078000 0x1c4>;
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+			#clock-cells = <1>;
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+			#address-cells = <1>;
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+			#size-cells = <1>;
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+			ranges;
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+
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+			clocks = <&gcc GCC_USB0_AUX_CLK>,
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+				<&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
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+				<&xo>;
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+			clock-names = "aux", "cfg_ahb", "ref";
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+
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+			resets =  <&gcc GCC_USB0_PHY_BCR>,
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+				<&gcc GCC_USB3PHY_0_PHY_BCR>;
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+			reset-names = "phy","common";
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+			status = "disabled";
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+
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+			usb0_ssphy: lane@78200 {
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+				reg = <0x00078200 0x130>,       /* Tx */
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+				      <0x00078400 0x200>,     /* Rx */
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+				      <0x00078800 0x1f8>,     /* PCS  */
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+				      <0x00078600 0x044>;     /* PCS misc*/
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+				#phy-cells = <0>;
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+				clocks = <&gcc GCC_USB0_PIPE_CLK>;
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+				clock-names = "pipe0";
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+				clock-output-names = "gcc_usb0_pipe_clk_src";
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+			};
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+		};
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+
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+		qusb_phy_0: phy@79000 {
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+			compatible = "qcom,ipq8074-qusb2-phy";
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+			reg = <0x00079000 0x180>;
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+			#phy-cells = <0>;
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+
163
+			clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
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+				 <&xo>;
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+			clock-names = "cfg_ahb", "ref";
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+
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+			resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
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+		};
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+
170
+		pcie_phy0: phy@86000 {
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+			compatible = "qcom,ipq8074-qmp-pcie-phy";
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+			reg = <0x00086000 0x1000>;
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+			#phy-cells = <0>;
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+			clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
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+			clock-names = "pipe_clk";
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+			clock-output-names = "pcie20_phy0_pipe_clk";
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+
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+			resets = <&gcc GCC_PCIE0_PHY_BCR>,
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+				<&gcc GCC_PCIE0PHY_PHY_BCR>;
180
+			reset-names = "phy",
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+				      "common";
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+			status = "disabled";
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+		};
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+
185
+		pcie_phy1: phy@8e000 {
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+			compatible = "qcom,ipq8074-qmp-pcie-phy";
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+			reg = <0x0008e000 0x1000>;
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+			#phy-cells = <0>;
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+			clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
190
+			clock-names = "pipe_clk";
191
+			clock-output-names = "pcie20_phy1_pipe_clk";
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+
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+			resets = <&gcc GCC_PCIE1_PHY_BCR>,
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+				<&gcc GCC_PCIE1PHY_PHY_BCR>;
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+			reset-names = "phy",
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+				      "common";
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+			status = "disabled";
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+		};
199
+
27
200
 		tlmm: pinctrl@1000000 {
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201
 			compatible = "qcom,ipq8074-pinctrl";
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-			reg = <0x1000000 0x300000>;
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+			reg = <0x01000000 0x300000>;
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203
 			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
31
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 			gpio-controller;
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+			gpio-ranges = <&tlmm 0 0 70>;
32
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 			#gpio-cells = <0x2>;
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 			interrupt-controller;
34
208
 			#interrupt-cells = <0x2>;
..
..
@@ -73,102 +247,38 @@
73
247
 			};
74
248
 		};
75
249
 
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-		intc: interrupt-controller@b000000 {
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-			compatible = "qcom,msm-qgic2";
78
-			interrupt-controller;
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-			#interrupt-cells = <0x3>;
80
-			reg = <0xb000000 0x1000>, <0xb002000 0x1000>;
81
-		};
82
-
83
-		timer {
84
-			compatible = "arm,armv8-timer";
85
-			interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
86
-				     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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-				     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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-				     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
89
-		};
90
-
91
-		timer@b120000 {
92
-			#address-cells = <1>;
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-			#size-cells = <1>;
94
-			ranges;
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-			compatible = "arm,armv7-timer-mem";
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-			reg = <0xb120000 0x1000>;
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-			clock-frequency = <19200000>;
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-
99
-			frame@b120000 {
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-				frame-number = <0>;
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-				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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-					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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-				reg = <0xb121000 0x1000>,
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-				      <0xb122000 0x1000>;
105
-			};
106
-
107
-			frame@b123000 {
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-				frame-number = <1>;
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-				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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-				reg = <0xb123000 0x1000>;
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-				status = "disabled";
112
-			};
113
-
114
-			frame@b124000 {
115
-				frame-number = <2>;
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-				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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-				reg = <0xb124000 0x1000>;
118
-				status = "disabled";
119
-			};
120
-
121
-			frame@b125000 {
122
-				frame-number = <3>;
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-				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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-				reg = <0xb125000 0x1000>;
125
-				status = "disabled";
126
-			};
127
-
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-			frame@b126000 {
129
-				frame-number = <4>;
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-				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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-				reg = <0xb126000 0x1000>;
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-				status = "disabled";
133
-			};
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-
135
-			frame@b127000 {
136
-				frame-number = <5>;
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-				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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-				reg = <0xb127000 0x1000>;
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-				status = "disabled";
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-			};
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-
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-			frame@b128000 {
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-				frame-number = <6>;
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-				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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-				reg = <0xb128000 0x1000>;
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-				status = "disabled";
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-			};
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-		};
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-
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 		gcc: gcc@1800000 {
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 			compatible = "qcom,gcc-ipq8074";
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-			reg = <0x1800000 0x80000>;
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+			reg = <0x01800000 0x80000>;
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 			#clock-cells = <0x1>;
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 			#reset-cells = <0x1>;
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 		};
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256
 
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-		blsp1_uart5: serial@78b3000 {
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-			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
159
-			reg = <0x78b3000 0x200>;
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-			interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
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-			clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
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-				 <&gcc GCC_BLSP1_AHB_CLK>;
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-			clock-names = "core", "iface";
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-			pinctrl-0 = <&serial_4_pins>;
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-			pinctrl-names = "default";
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+		sdhc_1: sdhci@7824900 {
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+			compatible = "qcom,sdhci-msm-v4";
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+			reg = <0x7824900 0x500>, <0x7824000 0x800>;
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+			reg-names = "hc_mem", "core_mem";
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+
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+			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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+				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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+			interrupt-names = "hc_irq", "pwr_irq";
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+
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+			clocks = <&xo>,
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+				 <&gcc GCC_SDCC1_AHB_CLK>,
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+				 <&gcc GCC_SDCC1_APPS_CLK>;
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+			clock-names = "xo", "iface", "core";
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+			max-frequency = <384000000>;
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+			mmc-ddr-1_8v;
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+			mmc-hs200-1_8v;
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+			mmc-hs400-1_8v;
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+			bus-width = <8>;
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+
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 			status = "disabled";
167
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 		};
168
278
 
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 		blsp_dma: dma@7884000 {
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 			compatible = "qcom,bam-v1.7.0";
171
-			reg = <0x7884000 0x2b000>;
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+			reg = <0x07884000 0x2b000>;
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 			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
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 			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
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 			clock-names = "bam_clk";
..
..
@@ -178,7 +288,7 @@
178
288
 
179
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 		blsp1_uart1: serial@78af000 {
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 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
181
-			reg = <0x78af000 0x200>;
291
+			reg = <0x078af000 0x200>;
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292
 			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
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 			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
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294
 				 <&gcc GCC_BLSP1_AHB_CLK>;
..
..
@@ -188,7 +298,7 @@
188
298
 
189
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 		blsp1_uart3: serial@78b1000 {
190
300
 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
191
-			reg = <0x78b1000 0x200>;
301
+			reg = <0x078b1000 0x200>;
192
302
 			interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
193
303
 			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
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304
 				<&gcc GCC_BLSP1_AHB_CLK>;
..
..
@@ -201,11 +311,23 @@
201
311
 			status = "disabled";
202
312
 		};
203
313
 
314
+		blsp1_uart5: serial@78b3000 {
315
+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
316
+			reg = <0x078b3000 0x200>;
317
+			interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
318
+			clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
319
+				 <&gcc GCC_BLSP1_AHB_CLK>;
320
+			clock-names = "core", "iface";
321
+			pinctrl-0 = <&serial_4_pins>;
322
+			pinctrl-names = "default";
323
+			status = "disabled";
324
+		};
325
+
204
326
 		blsp1_spi1: spi@78b5000 {
205
327
 			compatible = "qcom,spi-qup-v2.2.1";
206
328
 			#address-cells = <1>;
207
329
 			#size-cells = <0>;
208
-			reg = <0x78b5000 0x600>;
330
+			reg = <0x078b5000 0x600>;
209
331
 			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
210
332
 			spi-max-frequency = <50000000>;
211
333
 			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
..
..
@@ -222,7 +344,7 @@
222
344
 			compatible = "qcom,i2c-qup-v2.2.1";
223
345
 			#address-cells = <1>;
224
346
 			#size-cells = <0>;
225
-			reg = <0x78b6000 0x600>;
347
+			reg = <0x078b6000 0x600>;
226
348
 			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
227
349
 			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
228
350
 				<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
..
..
@@ -239,7 +361,7 @@
239
361
 			compatible = "qcom,i2c-qup-v2.2.1";
240
362
 			#address-cells = <1>;
241
363
 			#size-cells = <0>;
242
-			reg = <0x78b7000 0x600>;
364
+			reg = <0x078b7000 0x600>;
243
365
 			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
244
366
 			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
245
367
 				<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
..
..
@@ -252,7 +374,7 @@
252
374
 
253
375
 		qpic_bam: dma@7984000 {
254
376
 			compatible = "qcom,bam-v1.7.0";
255
-			reg = <0x7984000 0x1a000>;
377
+			reg = <0x07984000 0x1a000>;
256
378
 			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
257
379
 			clocks = <&gcc GCC_QPIC_AHB_CLK>;
258
380
 			clock-names = "bam_clk";
..
..
@@ -261,9 +383,9 @@
261
383
 			status = "disabled";
262
384
 		};
263
385
 
264
-		qpic_nand: nand@79b0000 {
386
+		qpic_nand: nand-controller@79b0000 {
265
387
 			compatible = "qcom,ipq8074-nand";
266
-			reg = <0x79b0000 0x10000>;
388
+			reg = <0x079b0000 0x10000>;
267
389
 			#address-cells = <1>;
268
390
 			#size-cells = <0>;
269
391
 			clocks = <&gcc GCC_QPIC_CLK>,
..
..
@@ -279,105 +401,174 @@
279
401
 			status = "disabled";
280
402
 		};
281
403
 
282
-		pcie_phy0: phy@86000 {
283
-			compatible = "qcom,ipq8074-qmp-pcie-phy";
284
-			reg = <0x86000 0x1000>;
285
-			#phy-cells = <0>;
286
-			clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
287
-			clock-names = "pipe_clk";
288
-			clock-output-names = "pcie20_phy0_pipe_clk";
404
+		usb_0: usb@8af8800 {
405
+			compatible = "qcom,dwc3";
406
+			reg = <0x08af8800 0x400>;
407
+			#address-cells = <1>;
408
+			#size-cells = <1>;
409
+			ranges;
289
410
 
290
-			resets = <&gcc GCC_PCIE0_PHY_BCR>,
291
-				<&gcc GCC_PCIE0PHY_PHY_BCR>;
292
-			reset-names = "phy",
293
-				      "common";
411
+			clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
412
+				<&gcc GCC_USB0_MASTER_CLK>,
413
+				<&gcc GCC_USB0_SLEEP_CLK>,
414
+				<&gcc GCC_USB0_MOCK_UTMI_CLK>;
415
+			clock-names = "sys_noc_axi",
416
+				"master",
417
+				"sleep",
418
+				"mock_utmi";
419
+
420
+			assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
421
+					  <&gcc GCC_USB0_MASTER_CLK>,
422
+					  <&gcc GCC_USB0_MOCK_UTMI_CLK>;
423
+			assigned-clock-rates = <133330000>,
424
+						<133330000>,
425
+						<19200000>;
426
+
427
+			resets = <&gcc GCC_USB0_BCR>;
294
428
 			status = "disabled";
429
+
430
+			dwc_0: dwc3@8a00000 {
431
+				compatible = "snps,dwc3";
432
+				reg = <0x8a00000 0xcd00>;
433
+				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
434
+				phys = <&qusb_phy_0>, <&usb0_ssphy>;
435
+				phy-names = "usb2-phy", "usb3-phy";
436
+				snps,is-utmi-l1-suspend;
437
+				snps,hird-threshold = /bits/ 8 <0x0>;
438
+				snps,dis_u2_susphy_quirk;
439
+				snps,dis_u3_susphy_quirk;
440
+				dr_mode = "host";
441
+			};
295
442
 		};
296
443
 
297
-		pcie0: pci@20000000 {
298
-			compatible = "qcom,pcie-ipq8074";
299
-			reg =  <0x20000000 0xf1d
300
-				0x20000f20 0xa8
301
-				0x80000 0x2000
302
-				0x20100000 0x1000>;
303
-			reg-names = "dbi", "elbi", "parf", "config";
304
-			device_type = "pci";
305
-			linux,pci-domain = <0>;
306
-			bus-range = <0x00 0xff>;
307
-			num-lanes = <1>;
308
-			#address-cells = <3>;
309
-			#size-cells = <2>;
444
+		usb_1: usb@8cf8800 {
445
+			compatible = "qcom,dwc3";
446
+			reg = <0x08cf8800 0x400>;
447
+			#address-cells = <1>;
448
+			#size-cells = <1>;
449
+			ranges;
310
450
 
311
-			phys = <&pcie_phy0>;
312
-			phy-names = "pciephy";
451
+			clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
452
+				<&gcc GCC_USB1_MASTER_CLK>,
453
+				<&gcc GCC_USB1_SLEEP_CLK>,
454
+				<&gcc GCC_USB1_MOCK_UTMI_CLK>;
455
+			clock-names = "sys_noc_axi",
456
+				"master",
457
+				"sleep",
458
+				"mock_utmi";
313
459
 
314
-			ranges = <0x81000000 0 0x20200000 0x20200000
315
-				  0 0x100000   /* downstream I/O */
316
-				  0x82000000 0 0x20300000 0x20300000
317
-				  0 0xd00000>; /* non-prefetchable memory */
460
+			assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
461
+					  <&gcc GCC_USB1_MASTER_CLK>,
462
+					  <&gcc GCC_USB1_MOCK_UTMI_CLK>;
463
+			assigned-clock-rates = <133330000>,
464
+						<133330000>,
465
+						<19200000>;
318
466
 
319
-			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
320
-			interrupt-names = "msi";
321
-			#interrupt-cells = <1>;
322
-			interrupt-map-mask = <0 0 0 0x7>;
323
-			interrupt-map = <0 0 0 1 &intc 0 75
324
-					 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
325
-					<0 0 0 2 &intc 0 78
326
-					 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
327
-					<0 0 0 3 &intc 0 79
328
-					 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
329
-					<0 0 0 4 &intc 0 83
330
-					 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
331
-
332
-			clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
333
-				 <&gcc GCC_PCIE0_AXI_M_CLK>,
334
-				 <&gcc GCC_PCIE0_AXI_S_CLK>,
335
-				 <&gcc GCC_PCIE0_AHB_CLK>,
336
-				 <&gcc GCC_PCIE0_AUX_CLK>;
337
-
338
-			clock-names = "iface",
339
-				      "axi_m",
340
-				      "axi_s",
341
-				      "ahb",
342
-				      "aux";
343
-			resets = <&gcc GCC_PCIE0_PIPE_ARES>,
344
-				 <&gcc GCC_PCIE0_SLEEP_ARES>,
345
-				 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
346
-				 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
347
-				 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
348
-				 <&gcc GCC_PCIE0_AHB_ARES>,
349
-				 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
350
-			reset-names = "pipe",
351
-				      "sleep",
352
-				      "sticky",
353
-				      "axi_m",
354
-				      "axi_s",
355
-				      "ahb",
356
-				      "axi_m_sticky";
467
+			resets = <&gcc GCC_USB1_BCR>;
357
468
 			status = "disabled";
469
+
470
+			dwc_1: dwc3@8c00000 {
471
+				compatible = "snps,dwc3";
472
+				reg = <0x8c00000 0xcd00>;
473
+				interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
474
+				phys = <&qusb_phy_1>, <&usb1_ssphy>;
475
+				phy-names = "usb2-phy", "usb3-phy";
476
+				snps,is-utmi-l1-suspend;
477
+				snps,hird-threshold = /bits/ 8 <0x0>;
478
+				snps,dis_u2_susphy_quirk;
479
+				snps,dis_u3_susphy_quirk;
480
+				dr_mode = "host";
481
+			};
358
482
 		};
359
483
 
360
-		pcie_phy1: phy@8e000 {
361
-			compatible = "qcom,ipq8074-qmp-pcie-phy";
362
-			reg = <0x8e000 0x1000>;
363
-			#phy-cells = <0>;
364
-			clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
365
-			clock-names = "pipe_clk";
366
-			clock-output-names = "pcie20_phy1_pipe_clk";
484
+		intc: interrupt-controller@b000000 {
485
+			compatible = "qcom,msm-qgic2";
486
+			interrupt-controller;
487
+			#interrupt-cells = <0x3>;
488
+			reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
489
+		};
367
490
 
368
-			resets = <&gcc GCC_PCIE1_PHY_BCR>,
369
-				<&gcc GCC_PCIE1PHY_PHY_BCR>;
370
-			reset-names = "phy",
371
-				      "common";
372
-			status = "disabled";
491
+		timer {
492
+			compatible = "arm,armv8-timer";
493
+			interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
494
+				     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
495
+				     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
496
+				     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
497
+		};
498
+
499
+		watchdog: watchdog@b017000 {
500
+			compatible = "qcom,kpss-wdt";
501
+			reg = <0xb017000 0x1000>;
502
+			interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
503
+			clocks = <&sleep_clk>;
504
+			timeout-sec = <30>;
505
+		};
506
+
507
+		timer@b120000 {
508
+			#address-cells = <1>;
509
+			#size-cells = <1>;
510
+			ranges;
511
+			compatible = "arm,armv7-timer-mem";
512
+			reg = <0x0b120000 0x1000>;
513
+			clock-frequency = <19200000>;
514
+
515
+			frame@b120000 {
516
+				frame-number = <0>;
517
+				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
518
+					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
519
+				reg = <0x0b121000 0x1000>,
520
+				      <0x0b122000 0x1000>;
521
+			};
522
+
523
+			frame@b123000 {
524
+				frame-number = <1>;
525
+				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
526
+				reg = <0x0b123000 0x1000>;
527
+				status = "disabled";
528
+			};
529
+
530
+			frame@b124000 {
531
+				frame-number = <2>;
532
+				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
533
+				reg = <0x0b124000 0x1000>;
534
+				status = "disabled";
535
+			};
536
+
537
+			frame@b125000 {
538
+				frame-number = <3>;
539
+				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
540
+				reg = <0x0b125000 0x1000>;
541
+				status = "disabled";
542
+			};
543
+
544
+			frame@b126000 {
545
+				frame-number = <4>;
546
+				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
547
+				reg = <0x0b126000 0x1000>;
548
+				status = "disabled";
549
+			};
550
+
551
+			frame@b127000 {
552
+				frame-number = <5>;
553
+				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
554
+				reg = <0x0b127000 0x1000>;
555
+				status = "disabled";
556
+			};
557
+
558
+			frame@b128000 {
559
+				frame-number = <6>;
560
+				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
561
+				reg = <0x0b128000 0x1000>;
562
+				status = "disabled";
563
+			};
373
564
 		};
374
565
 
375
566
 		pcie1: pci@10000000 {
376
567
 			compatible = "qcom,pcie-ipq8074";
377
-			reg =  <0x10000000 0xf1d
378
-				0x10000f20 0xa8
379
-				0x88000 0x2000
380
-				0x10100000 0x1000>;
568
+			reg =  <0x10000000 0xf1d>,
569
+			       <0x10000f20 0xa8>,
570
+			       <0x00088000 0x2000>,
571
+			       <0x10100000 0x1000>;
381
572
 			reg-names = "dbi", "elbi", "parf", "config";
382
573
 			device_type = "pci";
383
574
 			linux,pci-domain = <1>;
..
..
@@ -433,71 +624,68 @@
433
624
 				      "axi_m_sticky";
434
625
 			status = "disabled";
435
626
 		};
436
-	};
437
627
 
438
-	cpus {
439
-		#address-cells = <0x1>;
440
-		#size-cells = <0x0>;
628
+		pcie0: pci@20000000 {
629
+			compatible = "qcom,pcie-ipq8074";
630
+			reg = <0x20000000 0xf1d>,
631
+			      <0x20000f20 0xa8>,
632
+			      <0x00080000 0x2000>,
633
+			      <0x20100000 0x1000>;
634
+			reg-names = "dbi", "elbi", "parf", "config";
635
+			device_type = "pci";
636
+			linux,pci-domain = <0>;
637
+			bus-range = <0x00 0xff>;
638
+			num-lanes = <1>;
639
+			#address-cells = <3>;
640
+			#size-cells = <2>;
441
641
 
442
-		CPU0: cpu@0 {
443
-			device_type = "cpu";
444
-			compatible = "arm,cortex-a53", "arm,armv8";
445
-			reg = <0x0>;
446
-			next-level-cache = <&L2_0>;
447
-			enable-method = "psci";
448
-		};
642
+			phys = <&pcie_phy0>;
643
+			phy-names = "pciephy";
449
644
 
450
-		CPU1: cpu@1 {
451
-			device_type = "cpu";
452
-			compatible = "arm,cortex-a53", "arm,armv8";
453
-			enable-method = "psci";
454
-			reg = <0x1>;
455
-			next-level-cache = <&L2_0>;
456
-		};
645
+			ranges = <0x81000000 0 0x20200000 0x20200000
646
+				  0 0x100000   /* downstream I/O */
647
+				  0x82000000 0 0x20300000 0x20300000
648
+				  0 0xd00000>; /* non-prefetchable memory */
457
649
 
458
-		CPU2: cpu@2 {
459
-			device_type = "cpu";
460
-			compatible = "arm,cortex-a53", "arm,armv8";
461
-			enable-method = "psci";
462
-			reg = <0x2>;
463
-			next-level-cache = <&L2_0>;
464
-		};
650
+			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
651
+			interrupt-names = "msi";
652
+			#interrupt-cells = <1>;
653
+			interrupt-map-mask = <0 0 0 0x7>;
654
+			interrupt-map = <0 0 0 1 &intc 0 75
655
+					 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
656
+					<0 0 0 2 &intc 0 78
657
+					 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
658
+					<0 0 0 3 &intc 0 79
659
+					 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
660
+					<0 0 0 4 &intc 0 83
661
+					 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
465
662
 
466
-		CPU3: cpu@3 {
467
-			device_type = "cpu";
468
-			compatible = "arm,cortex-a53", "arm,armv8";
469
-			enable-method = "psci";
470
-			reg = <0x3>;
471
-			next-level-cache = <&L2_0>;
472
-		};
663
+			clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
664
+				 <&gcc GCC_PCIE0_AXI_M_CLK>,
665
+				 <&gcc GCC_PCIE0_AXI_S_CLK>,
666
+				 <&gcc GCC_PCIE0_AHB_CLK>,
667
+				 <&gcc GCC_PCIE0_AUX_CLK>;
473
668
 
474
-		L2_0: l2-cache {
475
-			compatible = "cache";
476
-			cache-level = <0x2>;
477
-		};
478
-	};
479
-
480
-	psci {
481
-		compatible = "arm,psci-1.0";
482
-		method = "smc";
483
-	};
484
-
485
-	pmu {
486
-		compatible = "arm,armv8-pmuv3";
487
-		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
488
-	};
489
-
490
-	clocks {
491
-		sleep_clk: sleep_clk {
492
-			compatible = "fixed-clock";
493
-			clock-frequency = <32000>;
494
-			#clock-cells = <0>;
495
-		};
496
-
497
-		xo: xo {
498
-			compatible = "fixed-clock";
499
-			clock-frequency = <19200000>;
500
-			#clock-cells = <0>;
669
+			clock-names = "iface",
670
+				      "axi_m",
671
+				      "axi_s",
672
+				      "ahb",
673
+				      "aux";
674
+			resets = <&gcc GCC_PCIE0_PIPE_ARES>,
675
+				 <&gcc GCC_PCIE0_SLEEP_ARES>,
676
+				 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
677
+				 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
678
+				 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
679
+				 <&gcc GCC_PCIE0_AHB_ARES>,
680
+				 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
681
+			reset-names = "pipe",
682
+				      "sleep",
683
+				      "sticky",
684
+				      "axi_m",
685
+				      "axi_s",
686
+				      "ahb",
687
+				      "axi_m_sticky";
688
+			status = "disabled";
501
689
 		};
502
690
 	};
503
691
 };