add dts config

hc

2023-12-06 08f87f769b595151be1afeff53e144f543faa614

 kernel/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
..
..
@@ -81,7 +81,7 @@
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 		};
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 		cpu0: cpu@0 {
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-			compatible = "arm,cortex-a53", "arm,armv8";
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+			compatible = "arm,cortex-a53";
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 			device_type = "cpu";
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 			reg = <0x0 0x0>;
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 			enable-method = "psci";
..
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@@ -94,11 +94,12 @@
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 		};
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 		cpu1: cpu@1 {
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-			compatible = "arm,cortex-a53", "arm,armv8";
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+			compatible = "arm,cortex-a53";
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 			device_type = "cpu";
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 			reg = <0x0 0x1>;
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 			enable-method = "psci";
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 			next-level-cache = <&CLUSTER0_L2>;
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+			clocks = <&stub_clock 0>;
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 			operating-points-v2 = <&cpu_opp_table>;
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 			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
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 			#cooling-cells = <2>; /* min followed by max */
..
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@@ -106,11 +107,12 @@
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 		};
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 		cpu2: cpu@2 {
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-			compatible = "arm,cortex-a53", "arm,armv8";
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+			compatible = "arm,cortex-a53";
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 			device_type = "cpu";
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 			reg = <0x0 0x2>;
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 			enable-method = "psci";
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 			next-level-cache = <&CLUSTER0_L2>;
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+			clocks = <&stub_clock 0>;
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 			operating-points-v2 = <&cpu_opp_table>;
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 			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
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 			#cooling-cells = <2>; /* min followed by max */
..
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@@ -118,11 +120,12 @@
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 		};
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 		cpu3: cpu@3 {
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-			compatible = "arm,cortex-a53", "arm,armv8";
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+			compatible = "arm,cortex-a53";
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 			device_type = "cpu";
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 			reg = <0x0 0x3>;
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 			enable-method = "psci";
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 			next-level-cache = <&CLUSTER0_L2>;
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+			clocks = <&stub_clock 0>;
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 			operating-points-v2 = <&cpu_opp_table>;
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 			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
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 			#cooling-cells = <2>; /* min followed by max */
..
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@@ -130,11 +133,12 @@
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 		};
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 		cpu4: cpu@100 {
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-			compatible = "arm,cortex-a53", "arm,armv8";
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+			compatible = "arm,cortex-a53";
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 			device_type = "cpu";
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 			reg = <0x0 0x100>;
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 			enable-method = "psci";
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 			next-level-cache = <&CLUSTER1_L2>;
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+			clocks = <&stub_clock 0>;
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 			operating-points-v2 = <&cpu_opp_table>;
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 			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
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 			#cooling-cells = <2>; /* min followed by max */
..
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@@ -142,11 +146,12 @@
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 		};
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 		cpu5: cpu@101 {
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-			compatible = "arm,cortex-a53", "arm,armv8";
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+			compatible = "arm,cortex-a53";
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 			device_type = "cpu";
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 			reg = <0x0 0x101>;
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 			enable-method = "psci";
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 			next-level-cache = <&CLUSTER1_L2>;
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+			clocks = <&stub_clock 0>;
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 			operating-points-v2 = <&cpu_opp_table>;
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 			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
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 			#cooling-cells = <2>; /* min followed by max */
..
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@@ -154,11 +159,12 @@
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 		};
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 		cpu6: cpu@102 {
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-			compatible = "arm,cortex-a53", "arm,armv8";
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+			compatible = "arm,cortex-a53";
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 			device_type = "cpu";
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 			reg = <0x0 0x102>;
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 			enable-method = "psci";
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 			next-level-cache = <&CLUSTER1_L2>;
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+			clocks = <&stub_clock 0>;
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 			operating-points-v2 = <&cpu_opp_table>;
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 			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
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 			#cooling-cells = <2>; /* min followed by max */
..
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@@ -166,11 +172,12 @@
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 		};
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 		cpu7: cpu@103 {
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-			compatible = "arm,cortex-a53", "arm,armv8";
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+			compatible = "arm,cortex-a53";
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 			device_type = "cpu";
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 			reg = <0x0 0x103>;
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 			enable-method = "psci";
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 			next-level-cache = <&CLUSTER1_L2>;
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+			clocks = <&stub_clock 0>;
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 			operating-points-v2 = <&cpu_opp_table>;
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 			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
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 			#cooling-cells = <2>; /* min followed by max */
..
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@@ -253,6 +260,7 @@
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 			compatible = "hisilicon,hi6220-aoctrl", "syscon";
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 			reg = <0x0 0xf7800000 0x0 0x2000>;
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 			#clock-cells = <1>;
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+			#reset-cells = <1>;
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 		};
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 		sys_ctrl: sys_ctrl@f7030000 {
..
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@@ -294,7 +302,7 @@
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 			mboxes = <&mailbox 1 0 11>;
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 		};
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-		uart0: uart@f8015000 {	/* console */
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+		uart0: serial@f8015000 {	/* console */
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 			compatible = "arm,pl011", "arm,primecell";
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 			reg = <0x0 0xf8015000 0x0 0x1000>;
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 			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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@@ -303,7 +311,7 @@
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 			clock-names = "uartclk", "apb_pclk";
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 		};
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-		uart1: uart@f7111000 {
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+		uart1: serial@f7111000 {
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 			compatible = "arm,pl011", "arm,primecell";
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 			reg = <0x0 0xf7111000 0x0 0x1000>;
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 			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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@@ -312,10 +320,12 @@
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 			clock-names = "uartclk", "apb_pclk";
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 			pinctrl-names = "default";
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 			pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>;
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+			dmas = <&dma0 8 &dma0 9>;
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+			dma-names = "rx", "tx";
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 			status = "disabled";
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 		};
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-		uart2: uart@f7112000 {
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+		uart2: serial@f7112000 {
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 			compatible = "arm,pl011", "arm,primecell";
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 			reg = <0x0 0xf7112000 0x0 0x1000>;
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 			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
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@@ -327,7 +337,7 @@
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 			status = "disabled";
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 		};
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-		uart3: uart@f7113000 {
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+		uart3: serial@f7113000 {
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 			compatible = "arm,pl011", "arm,primecell";
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 			reg = <0x0 0xf7113000 0x0 0x1000>;
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 			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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@@ -339,7 +349,7 @@
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 			status = "disabled";
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 		};
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-		uart4: uart@f7114000 {
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+		uart4: serial@f7114000 {
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 			compatible = "arm,pl011", "arm,primecell";
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 			reg = <0x0 0xf7114000 0x0 0x1000>;
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 			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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@@ -361,7 +371,7 @@
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 			clocks = <&sys_ctrl HI6220_EDMAC_ACLK>;
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 			dma-no-cci;
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 			dma-type = "hi6220_dma";
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-			status = "ok";
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+			status = "okay";
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 		};
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 		dual_timer0: timer@f8008000 {
..
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@@ -833,8 +843,9 @@
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 			compatible = "arm,sp805", "arm,primecell";
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 			reg = <0x0 0xf8005000 0x0 0x1000>;
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 			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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-			clocks = <&ao_ctrl HI6220_WDT0_PCLK>;
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-			clock-names = "apb_pclk";
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+			clocks = <&ao_ctrl HI6220_WDT0_PCLK>,
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+				 <&ao_ctrl HI6220_WDT0_PCLK>;
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+			clock-names = "wdog_clk", "apb_pclk";
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 		};
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 		tsensor: tsensor@0,f7030700 {
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@@ -886,7 +897,14 @@
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 				cooling-maps {
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 					map0 {
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 						trip = <&target>;
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-						cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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+						cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+								 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+								 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+								 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+								 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+								 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+								 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+								 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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 					};
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 				};
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 			};
..
..
@@ -1005,6 +1023,43 @@
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 			clock-names = "apb_pclk";
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 			cpu = <&cpu7>;
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 		};
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+
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+		mali: gpu@f4080000 {
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+			compatible = "hisilicon,hi6220-mali", "arm,mali-450";
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+			reg = <0x0 0xf4080000 0x0 0x00040000>;
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+			interrupt-parent = <&gic>;
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+			interrupts =	<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
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+					<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
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+					<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
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+					<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
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+					<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
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+					<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
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+					<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
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+					<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
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+					<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
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+					<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
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+					<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>;
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+
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+			interrupt-names = "gp",
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+					  "gpmmu",
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+					  "pp",
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+					  "pp0",
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+					  "ppmmu0",
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+					  "pp1",
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+					  "ppmmu1",
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+					  "pp2",
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+					  "ppmmu2",
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+					  "pp3",
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+					  "ppmmu3";
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+			clocks = <&media_ctrl HI6220_G3D_CLK>,
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+				 <&media_ctrl HI6220_G3D_PCLK>;
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+			clock-names = "core", "bus";
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+			assigned-clocks = <&media_ctrl HI6220_G3D_CLK>,
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+					  <&media_ctrl HI6220_G3D_PCLK>;
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+			assigned-clock-rates = <500000000>, <144000000>;
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+			reset-names = "ao_g3d", "media_g3d";
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+			resets = <&ao_ctrl AO_G3D>, <&media_ctrl MEDIA_G3D>;
1062
+		};
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 	};
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 };
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