forked from ~ljy/RK356X_SDK_RELEASE
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hc
2023-12-06 08f87f769b595151be1afeff53e144f543faa614 
 kernel/arch/arm/boot/dts/tegra30-apalis.dtsi
....@@ -3,48 +3,53 @@
33 
44 /*
55  * Toradex Apalis T30 Module Device Tree
6
- * Compatible for Revisions 1GB: V1.0A, V1.1A; 1GB IT: V1.1A;
7
- * 2GB: V1.0B, V1.0C, V1.0E, V1.1A
6
+ * Compatible for Revisions 1GB: V1.0A; 2GB: V1.0B, V1.0C, V1.0E
87  */
98 / {
10
-	model = "Toradex Apalis T30";
11
-	compatible = "toradex,apalis_t30", "nvidia,tegra30";
12
-
139 	memory@80000000 {
1410 		reg = <0x80000000 0x40000000>;
1511 	};
1612 
1713 	pcie@3000 {
14
+		status = "okay";
1815 		avdd-pexa-supply = <&vdd2_reg>;
19
-		vdd-pexa-supply = <&vdd2_reg>;
2016 		avdd-pexb-supply = <&vdd2_reg>;
21
-		vdd-pexb-supply = <&vdd2_reg>;
2217 		avdd-pex-pll-supply = <&vdd2_reg>;
2318 		avdd-plle-supply = <&ldo6_reg>;
24
-		vddio-pex-ctl-supply = <&sys_3v3_reg>;
25
-		hvdd-pex-supply = <&sys_3v3_reg>;
19
+		hvdd-pex-supply = <&reg_module_3v3>;
20
+		vddio-pex-ctl-supply = <&reg_module_3v3>;
21
+		vdd-pexa-supply = <&vdd2_reg>;
22
+		vdd-pexb-supply = <&vdd2_reg>;
2623 
24
+		/* Apalis type specific */
2725 		pci@1,0 {
2826 			nvidia,num-lanes = <4>;
2927 		};
3028 
29
+		/* Apalis PCIe */
3130 		pci@2,0 {
3231 			nvidia,num-lanes = <1>;
3332 		};
3433 
34
+		/* I210/I211 Gigabit Ethernet Controller (on-module) */
3535 		pci@3,0 {
36
+			status = "okay";
3637 			nvidia,num-lanes = <1>;
38
+
39
+			ethernet@0,0 {
40
+				reg = <0 0 0 0 0>;
41
+				local-mac-address = [00 00 00 00 00 00];
42
+			};
3743 		};
3844 	};
3945 
4046 	host1x@50000000 {
4147 		hdmi@54280000 {
42
-			vdd-supply = <&avdd_hdmi_3v3_reg>;
43
-			pll-supply = <&avdd_hdmi_pll_1v8_reg>;
44
-
48
+			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
4549 			nvidia,hpd-gpio =
4650 				<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
47
-			nvidia,ddc-i2c-bus = <&hdmiddc>;
51
+			pll-supply = <&reg_1v8_avdd_hdmi_pll>;
52
+			vdd-supply = <&reg_3v3_avdd_hdmi>;
4853 		};
4954 	};
5055 
....@@ -54,18 +59,18 @@
5459 
5560 		state_default: pinmux {
5661 			/* Analogue Audio (On-module) */
57
-			clk1_out_pw4 {
62
+			clk1-out-pw4 {
5863 				nvidia,pins = "clk1_out_pw4";
5964 				nvidia,function = "extperiph1";
6065 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
6166 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
6267 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
6368 			};
64
-			dap3_fs_pp0 {
65
-				nvidia,pins =	"dap3_fs_pp0",
66
-						"dap3_sclk_pp3",
67
-						"dap3_din_pp1",
68
-						"dap3_dout_pp2";
69
+			dap3-fs-pp0 {
70
+				nvidia,pins = "dap3_fs_pp0",
71
+					      "dap3_sclk_pp3",
72
+					      "dap3_din_pp1",
73
+					      "dap3_dout_pp2";
6974 				nvidia,function = "i2s2";
7075 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
7176 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
....@@ -77,25 +82,28 @@
7782 				nvidia,function = "rsvd4";
7883 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
7984 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
85
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
8086 			};
8187 
8288 			/* Apalis BKL1_PWM */
83
-			uart3_rts_n_pc0 {
89
+			uart3-rts-n-pc0 {
8490 				nvidia,pins = "uart3_rts_n_pc0";
8591 				nvidia,function = "pwm0";
8692 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
8793 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
94
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
8895 			};
8996 			/* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */
90
-			uart3_cts_n_pa1 {
97
+			uart3-cts-n-pa1 {
9198 				nvidia,pins = "uart3_cts_n_pa1";
9299 				nvidia,function = "rsvd2";
93100 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
94101 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
102
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
95103 			};
96104 
97105 			/* Apalis CAN1 on SPI6 */
98
-			spi2_cs0_n_px3 {
106
+			spi2-cs0-n-px3 {
99107 				nvidia,pins = "spi2_cs0_n_px3",
100108 					      "spi2_miso_px1",
101109 					      "spi2_mosi_px0",
....@@ -105,7 +113,7 @@
105113 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
106114 			};
107115 			/* CAN_INT1 */
108
-			spi2_cs1_n_pw2 {
116
+			spi2-cs1-n-pw2 {
109117 				nvidia,pins = "spi2_cs1_n_pw2";
110118 				nvidia,function = "spi3";
111119 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
....@@ -114,7 +122,7 @@
114122 			};
115123 
116124 			/* Apalis CAN2 on SPI4 */
117
-			gmi_a16_pj7 {
125
+			gmi-a16-pj7 {
118126 				nvidia,pins = "gmi_a16_pj7",
119127 					      "gmi_a17_pb0",
120128 					      "gmi_a18_pb1",
....@@ -125,7 +133,7 @@
125133 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
126134 			};
127135 			/* CAN_INT2 */
128
-			spi2_cs2_n_pw3 {
136
+			spi2-cs2-n-pw3 {
129137 				nvidia,pins = "spi2_cs2_n_pw3";
130138 				nvidia,function = "spi3";
131139 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
....@@ -134,20 +142,20 @@
134142 			};
135143 
136144 			/* Apalis Digital Audio */
137
-			clk1_req_pee2 {
145
+			clk1-req-pee2 {
138146 				nvidia,pins = "clk1_req_pee2";
139147 				nvidia,function = "hda";
140148 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
141149 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
142150 			};
143
-			clk2_out_pw5 {
151
+			clk2-out-pw5 {
144152 				nvidia,pins = "clk2_out_pw5";
145153 				nvidia,function = "extperiph2";
146154 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
147155 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
148156 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
149157 			};
150
-			dap1_fs_pn0 {
158
+			dap1-fs-pn0 {
151159 				nvidia,pins = "dap1_fs_pn0",
152160 					      "dap1_din_pn1",
153161 					      "dap1_dout_pn2",
....@@ -157,26 +165,123 @@
157165 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
158166 			};
159167 
160
-			/* Apalis I2C3 */
161
-			cam_i2c_scl_pbb1 {
168
+			/* Apalis GPIO */
169
+			kb-col0-pq0 {
170
+				nvidia,pins = "kb_col0_pq0",
171
+					      "kb_col1_pq1",
172
+					      "kb_row10_ps2",
173
+					      "kb_row11_ps3",
174
+					      "kb_row12_ps4",
175
+					      "kb_row13_ps5",
176
+					      "kb_row14_ps6",
177
+					      "kb_row15_ps7";
178
+				nvidia,function = "kbc";
179
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
180
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
181
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
182
+			};
183
+			/* Multiplexed and therefore disabled */
184
+			owr {
185
+				nvidia,pins = "owr";
186
+				nvidia,function = "rsvd3";
187
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
188
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
189
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
190
+			};
191
+
192
+			/* Apalis HDMI1 */
193
+			hdmi-cec-pee3 {
194
+				nvidia,pins = "hdmi_cec_pee3";
195
+				nvidia,function = "cec";
196
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
197
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
198
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
199
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
200
+			};
201
+			hdmi-int-pn7 {
202
+				nvidia,pins = "hdmi_int_pn7";
203
+				nvidia,function = "hdmi";
204
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
205
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
206
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
207
+			};
208
+
209
+			/* Apalis I2C1 */
210
+			gen1-i2c-scl-pc4 {
211
+				nvidia,pins = "gen1_i2c_scl_pc4",
212
+					      "gen1_i2c_sda_pc5";
213
+				nvidia,function = "i2c1";
214
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
215
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
216
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
217
+				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
218
+			};
219
+
220
+			/* Apalis I2C2 (DDC) */
221
+			ddc-scl-pv4 {
222
+				nvidia,pins = "ddc_scl_pv4",
223
+					      "ddc_sda_pv5";
224
+				nvidia,function = "i2c4";
225
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
226
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
227
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
228
+			};
229
+
230
+			/* Apalis I2C3 (CAM) */
231
+			cam-i2c-scl-pbb1 {
162232 				nvidia,pins = "cam_i2c_scl_pbb1",
163233 					      "cam_i2c_sda_pbb2";
164234 				nvidia,function = "i2c3";
165235 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
166236 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
167237 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
168
-				nvidia,lock = <TEGRA_PIN_DISABLE>;
169238 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
170239 			};
171240 
241
+			/* Apalis LCD1 */
242
+			lcd-d0-pe0 {
243
+				nvidia,pins = "lcd_d0_pe0",
244
+					      "lcd_d1_pe1",
245
+					      "lcd_d2_pe2",
246
+					      "lcd_d3_pe3",
247
+					      "lcd_d4_pe4",
248
+					      "lcd_d5_pe5",
249
+					      "lcd_d6_pe6",
250
+					      "lcd_d7_pe7",
251
+					      "lcd_d8_pf0",
252
+					      "lcd_d9_pf1",
253
+					      "lcd_d10_pf2",
254
+					      "lcd_d11_pf3",
255
+					      "lcd_d12_pf4",
256
+					      "lcd_d13_pf5",
257
+					      "lcd_d14_pf6",
258
+					      "lcd_d15_pf7",
259
+					      "lcd_d16_pm0",
260
+					      "lcd_d17_pm1",
261
+					      "lcd_d18_pm2",
262
+					      "lcd_d19_pm3",
263
+					      "lcd_d20_pm4",
264
+					      "lcd_d21_pm5",
265
+					      "lcd_d22_pm6",
266
+					      "lcd_d23_pm7",
267
+					      "lcd_de_pj1",
268
+					      "lcd_hsync_pj3",
269
+					      "lcd_pclk_pb3",
270
+					      "lcd_vsync_pj4";
271
+				nvidia,function = "displaya";
272
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
273
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
274
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
275
+			};
276
+
172277 			/* Apalis MMC1 */
173
-			sdmmc3_clk_pa6 {
278
+			sdmmc3-clk-pa6 {
174279 				nvidia,pins = "sdmmc3_clk_pa6";
175280 				nvidia,function = "sdmmc3";
176281 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
177282 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
178283 			};
179
-			sdmmc3_dat0_pb7 {
284
+			sdmmc3-dat0-pb7 {
180285 				nvidia,pins = "sdmmc3_cmd_pa7",
181286 					      "sdmmc3_dat0_pb7",
182287 					      "sdmmc3_dat1_pb6",
....@@ -194,9 +299,80 @@
194299 			pv3 {
195300 				nvidia,pins = "pv3";
196301 				nvidia,function = "rsvd2";
302
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
303
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
304
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
305
+			};
306
+
307
+			/* Apalis Parallel Camera */
308
+			cam-mclk-pcc0 {
309
+				nvidia,pins = "cam_mclk_pcc0";
310
+				nvidia,function = "vi_alt3";
311
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
312
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
313
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
314
+			};
315
+			vi-vsync-pd6 {
316
+				nvidia,pins = "vi_d0_pt4",
317
+					      "vi_d1_pd5",
318
+					      "vi_d2_pl0",
319
+					      "vi_d3_pl1",
320
+					      "vi_d4_pl2",
321
+					      "vi_d5_pl3",
322
+					      "vi_d6_pl4",
323
+					      "vi_d7_pl5",
324
+					      "vi_d8_pl6",
325
+					      "vi_d9_pl7",
326
+					      "vi_d10_pt2",
327
+					      "vi_d11_pt3",
328
+					      "vi_hsync_pd7",
329
+					      "vi_pclk_pt0",
330
+					      "vi_vsync_pd6";
331
+				nvidia,function = "vi";
197332 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
198333 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
199334 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
335
+			};
336
+			/* Multiplexed and therefore disabled */
337
+			kb-col2-pq2 {
338
+				nvidia,pins = "kb_col2_pq2",
339
+					      "kb_col3_pq3",
340
+					      "kb_col4_pq4",
341
+					      "kb_row4_pr4";
342
+				nvidia,function = "rsvd4";
343
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
344
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
345
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
346
+			};
347
+			kb-row0-pr0 {
348
+				nvidia,pins = "kb_row0_pr0",
349
+					      "kb_row1_pr1",
350
+					      "kb_row2_pr2",
351
+					      "kb_row3_pr3";
352
+				nvidia,function = "rsvd3";
353
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
354
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
355
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
356
+			};
357
+			kb-row5-pr5 {
358
+				nvidia,pins = "kb_row5_pr5",
359
+					      "kb_row6_pr6",
360
+					      "kb_row7_pr7";
361
+				nvidia,function = "kbc";
362
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
363
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
364
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
365
+			};
366
+			/*
367
+			 * VI level-shifter direction
368
+			 * (pull-down => default direction input)
369
+			 */
370
+			vi-mclk-pt1 {
371
+				nvidia,pins = "vi_mclk_pt1";
372
+				nvidia,function = "vi_alt3";
373
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
374
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
375
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
200376 			};
201377 
202378 			/* Apalis PWM1 */
....@@ -232,21 +408,30 @@
232408 			};
233409 
234410 			/* Apalis RESET_MOCI# */
235
-			gmi_rst_n_pi4 {
411
+			gmi-rst-n-pi4 {
236412 				nvidia,pins = "gmi_rst_n_pi4";
237413 				nvidia,function = "gmi";
238414 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
239415 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
240416 			};
241417 
418
+			/* Apalis SATA1_ACT# */
419
+			pex-l0-prsnt-n-pdd0 {
420
+				nvidia,pins = "pex_l0_prsnt_n_pdd0";
421
+				nvidia,function = "rsvd3";
422
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
423
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
424
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
425
+			};
426
+
242427 			/* Apalis SD1 */
243
-			sdmmc1_clk_pz0 {
428
+			sdmmc1-clk-pz0 {
244429 				nvidia,pins = "sdmmc1_clk_pz0";
245430 				nvidia,function = "sdmmc1";
246431 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
247432 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
248433 			};
249
-			sdmmc1_cmd_pz1 {
434
+			sdmmc1-cmd-pz1 {
250435 				nvidia,pins = "sdmmc1_cmd_pz1",
251436 					      "sdmmc1_dat0_py7",
252437 					      "sdmmc1_dat1_py6",
....@@ -257,16 +442,26 @@
257442 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
258443 			};
259444 			/* Apalis SD1_CD# */
260
-			clk2_req_pcc5 {
445
+			clk2-req-pcc5 {
261446 				nvidia,pins = "clk2_req_pcc5";
262447 				nvidia,function = "rsvd2";
448
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
449
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
450
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
451
+			};
452
+
453
+			/* Apalis SPDIF1 */
454
+			spdif-out-pk5 {
455
+				nvidia,pins = "spdif_out_pk5",
456
+					      "spdif_in_pk6";
457
+				nvidia,function = "spdif";
263458 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
264459 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
265460 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
266461 			};
267462 
268463 			/* Apalis SPI1 */
269
-			spi1_sck_px5 {
464
+			spi1-sck-px5 {
270465 				nvidia,pins = "spi1_sck_px5",
271466 					      "spi1_mosi_px4",
272467 					      "spi1_miso_px7",
....@@ -277,7 +472,7 @@
277472 			};
278473 
279474 			/* Apalis SPI2 */
280
-			lcd_sck_pz4 {
475
+			lcd-sck-pz4 {
281476 				nvidia,pins = "lcd_sck_pz4",
282477 					      "lcd_sdout_pn5",
283478 					      "lcd_sdin_pz2",
....@@ -287,8 +482,30 @@
287482 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
288483 			};
289484 
485
+			/*
486
+			 * Apalis TS (Low-speed type specific)
487
+			 * pins may be used as GPIOs
488
+			 */
489
+			kb-col5-pq5 {
490
+				nvidia,pins = "kb_col5_pq5";
491
+				nvidia,function = "rsvd4";
492
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
493
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
494
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
495
+			};
496
+			kb-col6-pq6 {
497
+				nvidia,pins = "kb_col6_pq6",
498
+					      "kb_col7_pq7",
499
+					      "kb_row8_ps0",
500
+					      "kb_row9_ps1";
501
+				nvidia,function = "kbc";
502
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
503
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
504
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
505
+			};
506
+
290507 			/* Apalis UART1 */
291
-			ulpi_data0 {
508
+			ulpi-data0 {
292509 				nvidia,pins = "ulpi_data0_po1",
293510 					      "ulpi_data1_po2",
294511 					      "ulpi_data2_po3",
....@@ -303,7 +520,7 @@
303520 			};
304521 
305522 			/* Apalis UART2 */
306
-			ulpi_clk_py0 {
523
+			ulpi-clk-py0 {
307524 				nvidia,pins = "ulpi_clk_py0",
308525 					      "ulpi_dir_py1",
309526 					      "ulpi_nxt_py2",
....@@ -314,7 +531,7 @@
314531 			};
315532 
316533 			/* Apalis UART3 */
317
-			uart2_rxd_pc3 {
534
+			uart2-rxd-pc3 {
318535 				nvidia,pins = "uart2_rxd_pc3",
319536 					      "uart2_txd_pc2";
320537 				nvidia,function = "uartb";
....@@ -323,7 +540,7 @@
323540 			};
324541 
325542 			/* Apalis UART4 */
326
-			uart3_rxd_pw7 {
543
+			uart3-rxd-pw7 {
327544 				nvidia,pins = "uart3_rxd_pw7",
328545 					      "uart3_txd_pw6";
329546 				nvidia,function = "uartc";
....@@ -331,8 +548,26 @@
331548 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
332549 			};
333550 
551
+			/* Apalis USBH_EN */
552
+			pex-l0-rst-n-pdd1 {
553
+				nvidia,pins = "pex_l0_rst_n_pdd1";
554
+				nvidia,function = "rsvd3";
555
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
556
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
557
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
558
+			};
559
+
560
+			/* Apalis USBH_OC# */
561
+			pex-l0-clkreq-n-pdd2 {
562
+				nvidia,pins = "pex_l0_clkreq_n_pdd2";
563
+				nvidia,function = "rsvd3";
564
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
565
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
566
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
567
+			};
568
+
334569 			/* Apalis USBO1_EN */
335
-			gen2_i2c_scl_pt5 {
570
+			gen2-i2c-scl-pt5 {
336571 				nvidia,pins = "gen2_i2c_scl_pt5";
337572 				nvidia,function = "rsvd4";
338573 				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
....@@ -341,13 +576,23 @@
341576 			};
342577 
343578 			/* Apalis USBO1_OC# */
344
-			gen2_i2c_sda_pt6 {
579
+			gen2-i2c-sda-pt6 {
345580 				nvidia,pins = "gen2_i2c_sda_pt6";
346581 				nvidia,function = "rsvd4";
347582 				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
348583 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
349584 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
350585 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
586
+			};
587
+
588
+			/* Apalis VGA1 not supported and therefore disabled */
589
+			crt-hsync-pv6 {
590
+				nvidia,pins = "crt_hsync_pv6",
591
+					      "crt_vsync_pv7";
592
+				nvidia,function = "rsvd2";
593
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
594
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
595
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
351596 			};
352597 
353598 			/* Apalis WAKE1_MICO */
....@@ -360,14 +605,16 @@
360605 			};
361606 
362607 			/* eMMC (On-module) */
363
-			sdmmc4_clk_pcc4 {
608
+			sdmmc4-clk-pcc4 {
364609 				nvidia,pins = "sdmmc4_clk_pcc4",
610
+					      "sdmmc4_cmd_pt7",
365611 					      "sdmmc4_rst_n_pcc3";
366612 				nvidia,function = "sdmmc4";
367613 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
368614 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
615
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
369616 			};
370
-			sdmmc4_dat0_paa0 {
617
+			sdmmc4-dat0-paa0 {
371618 				nvidia,pins = "sdmmc4_dat0_paa0",
372619 					      "sdmmc4_dat1_paa1",
373620 					      "sdmmc4_dat2_paa2",
....@@ -379,6 +626,34 @@
379626 				nvidia,function = "sdmmc4";
380627 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
381628 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
629
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
630
+			};
631
+
632
+			/* LAN i210/i211 DEV_OFF_N, PE_RST_N (On-module) */
633
+			pex-l2-prsnt-n-pdd7 {
634
+				nvidia,pins = "pex_l2_prsnt_n_pdd7",
635
+					      "pex_l2_rst_n_pcc6";
636
+				nvidia,function = "pcie";
637
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
638
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
639
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
640
+			};
641
+			/* LAN i210/i211 PE_WAKE_N, SDP3 (On-module) */
642
+			pex-wake-n-pdd3 {
643
+				nvidia,pins = "pex_wake_n_pdd3",
644
+					      "pex_l2_clkreq_n_pcc7";
645
+				nvidia,function = "pcie";
646
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
647
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
648
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
649
+			};
650
+			/* LAN i210/i211 SMB_ALERT_N (On-module) */
651
+			sys-clk-req-pz5 {
652
+				nvidia,pins = "sys_clk_req_pz5";
653
+				nvidia,function = "rsvd2";
654
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
655
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
656
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
382657 			};
383658 
384659 			/* LVDS Transceiver Configuration */
....@@ -391,7 +666,6 @@
391666 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
392667 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
393668 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
394
-				nvidia,lock = <TEGRA_PIN_DISABLE>;
395669 			};
396670 			pbb3 {
397671 				nvidia,pins = "pbb3",
....@@ -402,18 +676,121 @@
402676 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
403677 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
404678 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
405
-				nvidia,lock = <TEGRA_PIN_DISABLE>;
679
+			};
680
+
681
+			/* Not connected and therefore disabled */
682
+			clk-32k-out-pa0 {
683
+				nvidia,pins = "clk3_out_pee0",
684
+					      "clk3_req_pee1",
685
+					      "clk_32k_out_pa0",
686
+					      "dap4_din_pp5",
687
+					      "dap4_dout_pp6",
688
+					      "dap4_fs_pp4",
689
+					      "dap4_sclk_pp7";
690
+				nvidia,function = "rsvd2";
691
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
692
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
693
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
694
+			};
695
+			dap2-fs-pa2 {
696
+				nvidia,pins = "dap2_fs_pa2",
697
+					      "dap2_sclk_pa3",
698
+					      "dap2_din_pa4",
699
+					      "dap2_dout_pa5",
700
+					      "lcd_dc0_pn6",
701
+					      "lcd_m1_pw1",
702
+					      "lcd_pwr1_pc1",
703
+					      "pex_l1_clkreq_n_pdd6",
704
+					      "pex_l1_prsnt_n_pdd4",
705
+					      "pex_l1_rst_n_pdd5";
706
+				nvidia,function = "rsvd3";
707
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
708
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
709
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
710
+			};
711
+			gmi-ad0-pg0 {
712
+				nvidia,pins = "gmi_ad0_pg0",
713
+					      "gmi_ad2_pg2",
714
+					      "gmi_ad3_pg3",
715
+					      "gmi_ad4_pg4",
716
+					      "gmi_ad5_pg5",
717
+					      "gmi_ad6_pg6",
718
+					      "gmi_ad7_pg7",
719
+					      "gmi_ad8_ph0",
720
+					      "gmi_ad9_ph1",
721
+					      "gmi_ad10_ph2",
722
+					      "gmi_ad11_ph3",
723
+					      "gmi_ad12_ph4",
724
+					      "gmi_ad13_ph5",
725
+					      "gmi_ad14_ph6",
726
+					      "gmi_ad15_ph7",
727
+					      "gmi_adv_n_pk0",
728
+					      "gmi_clk_pk1",
729
+					      "gmi_cs4_n_pk2",
730
+					      "gmi_cs2_n_pk3",
731
+					      "gmi_dqs_pi2",
732
+					      "gmi_iordy_pi5",
733
+					      "gmi_oe_n_pi1",
734
+					      "gmi_wait_pi7",
735
+					      "gmi_wr_n_pi0",
736
+					      "lcd_cs1_n_pw0",
737
+					      "pu0",
738
+					      "pu1",
739
+					      "pu2";
740
+				nvidia,function = "rsvd4";
741
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
742
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
743
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
744
+			};
745
+			gmi-cs0-n-pj0 {
746
+				nvidia,pins = "gmi_cs0_n_pj0",
747
+					      "gmi_cs1_n_pj2",
748
+					      "gmi_cs3_n_pk4";
749
+				nvidia,function = "rsvd1";
750
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
751
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
752
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
753
+			};
754
+			gmi-cs6-n-pi3 {
755
+				nvidia,pins = "gmi_cs6_n_pi3";
756
+				nvidia,function = "sata";
757
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
758
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
759
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
760
+			};
761
+			gmi-cs7-n-pi6 {
762
+				nvidia,pins = "gmi_cs7_n_pi6";
763
+				nvidia,function = "gmi_alt";
764
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
765
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
766
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
767
+			};
768
+			lcd-pwr0-pb2 {
769
+				nvidia,pins = "lcd_pwr0_pb2",
770
+					      "lcd_pwr2_pc6",
771
+					      "lcd_wr_n_pz3";
772
+				nvidia,function = "hdcp";
773
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
774
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
775
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
776
+			};
777
+			uart2-cts-n-pj5 {
778
+				nvidia,pins = "uart2_cts_n_pj5",
779
+					      "uart2_rts_n_pj6";
780
+				nvidia,function = "gmi";
781
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
782
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
783
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
406784 			};
407785 
408786 			/* Power I2C (On-module) */
409
-			pwr_i2c_scl_pz6 {
787
+			pwr-i2c-scl-pz6 {
410788 				nvidia,pins = "pwr_i2c_scl_pz6",
411789 					      "pwr_i2c_sda_pz7";
412790 				nvidia,function = "i2cpwr";
413791 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
414792 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
415793 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
416
-				nvidia,lock = <TEGRA_PIN_DISABLE>;
417794 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
418795 			};
419796 
....@@ -422,15 +799,15 @@
422799 			 * temperature sensor therefore requires disabling for
423800 			 * now
424801 			 */
425
-			lcd_dc1_pd2 {
802
+			lcd-dc1-pd2 {
426803 				nvidia,pins = "lcd_dc1_pd2";
427804 				nvidia,function = "rsvd3";
428
-				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
429
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
430
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
805
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
806
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
807
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
431808 			};
432809 
433
-			/* TOUCH_PEN_INT# */
810
+			/* TOUCH_PEN_INT# (On-module) */
434811 			pv0 {
435812 				nvidia,pins = "pv0";
436813 				nvidia,function = "rsvd1";
....@@ -441,7 +818,19 @@
441818 		};
442819 	};
443820 
444
-	hdmiddc: i2c@7000c700 {
821
+	serial@70006040 {
822
+		compatible = "nvidia,tegra30-hsuart";
823
+	};
824
+
825
+	serial@70006200 {
826
+		compatible = "nvidia,tegra30-hsuart";
827
+	};
828
+
829
+	serial@70006300 {
830
+		compatible = "nvidia,tegra30-hsuart";
831
+	};
832
+
833
+	hdmi_ddc: i2c@7000c700 {
445834 		clock-frequency = <10000>;
446835 	};
447836 
....@@ -457,12 +846,14 @@
457846 		sgtl5000: codec@a {
458847 			compatible = "fsl,sgtl5000";
459848 			reg = <0x0a>;
460
-			VDDA-supply = <&sys_3v3_reg>;
461
-			VDDIO-supply = <&sys_3v3_reg>;
849
+			#sound-dai-cells = <0>;
850
+			VDDA-supply = <&reg_module_3v3_audio>;
851
+			VDDD-supply = <&reg_1v8_vio>;
852
+			VDDIO-supply = <&reg_module_3v3>;
462853 			clocks = <&tegra_car TEGRA30_CLK_EXTERN1>;
463854 		};
464855 
465
-		pmic: tps65911@2d {
856
+		pmic: pmic@2d {
466857 			compatible = "ti,tps65911";
467858 			reg = <0x2d>;
468859 
....@@ -475,43 +866,38 @@
475866 			#gpio-cells = <2>;
476867 			gpio-controller;
477868 
478
-			vcc1-supply = <&sys_3v3_reg>;
479
-			vcc2-supply = <&sys_3v3_reg>;
480
-			vcc3-supply = <&vio_reg>;
481
-			vcc4-supply = <&sys_3v3_reg>;
482
-			vcc5-supply = <&sys_3v3_reg>;
483
-			vcc6-supply = <&vio_reg>;
484
-			vcc7-supply = <&charge_pump_5v0_reg>;
485
-			vccio-supply = <&sys_3v3_reg>;
869
+			vcc1-supply = <&reg_module_3v3>;
870
+			vcc2-supply = <&reg_module_3v3>;
871
+			vcc3-supply = <&reg_1v8_vio>;
872
+			vcc4-supply = <&reg_module_3v3>;
873
+			vcc5-supply = <&reg_module_3v3>;
874
+			vcc6-supply = <&reg_1v8_vio>;
875
+			vcc7-supply = <&reg_5v0_charge_pump>;
876
+			vccio-supply = <&reg_module_3v3>;
486877 
487878 			regulators {
488
-				/* SW1: +V1.35_VDDIO_DDR */
489879 				vdd1_reg: vdd1 {
490
-					regulator-name = "vddio_ddr_1v35";
880
+					regulator-name = "+V1.35_VDDIO_DDR";
491881 					regulator-min-microvolt = <1350000>;
492882 					regulator-max-microvolt = <1350000>;
493883 					regulator-always-on;
494884 				};
495885 
496
-				/* SW2: +V1.05 */
497886 				vdd2_reg: vdd2 {
498
-					regulator-name =
499
-						"vdd_pexa,vdd_pexb,vdd_sata";
887
+					regulator-name = "+V1.05";
500888 					regulator-min-microvolt = <1050000>;
501889 					regulator-max-microvolt = <1050000>;
502890 				};
503891 
504
-				/* SW CTRL: +V1.0_VDD_CPU */
505892 				vddctrl_reg: vddctrl {
506
-					regulator-name = "vdd_cpu,vdd_sys";
893
+					regulator-name = "+V1.0_VDD_CPU";
507894 					regulator-min-microvolt = <1150000>;
508895 					regulator-max-microvolt = <1150000>;
509896 					regulator-always-on;
510897 				};
511898 
512
-				/* SWIO: +V1.8 */
513
-				vio_reg: vio {
514
-					regulator-name = "vdd_1v8_gen";
899
+				reg_1v8_vio: vio {
900
+					regulator-name = "+V1.8";
515901 					regulator-min-microvolt = <1800000>;
516902 					regulator-max-microvolt = <1800000>;
517903 					regulator-always-on;
....@@ -521,27 +907,24 @@
521907 
522908 				/*
523909 				 * EN_+V3.3 switching via FET:
524
-				 * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN
525
-				 * see also v3_3 fixed supply
910
+				 * +V3.3_AUDIO_AVDD_S, +V3.3
911
+				 * see also +V3.3 fixed supply
526912 				 */
527913 				ldo2_reg: ldo2 {
528
-					regulator-name = "en_3v3";
914
+					regulator-name = "EN_+V3.3";
529915 					regulator-min-microvolt = <3300000>;
530916 					regulator-max-microvolt = <3300000>;
531917 					regulator-always-on;
532918 				};
533919 
534
-				/* +V1.2_CSI */
535920 				ldo3_reg: ldo3 {
536
-					regulator-name =
537
-						"avdd_dsi_csi,pwrdet_mipi";
921
+					regulator-name = "+V1.2_CSI";
538922 					regulator-min-microvolt = <1200000>;
539923 					regulator-max-microvolt = <1200000>;
540924 				};
541925 
542
-				/* +V1.2_VDD_RTC */
543926 				ldo4_reg: ldo4 {
544
-					regulator-name = "vdd_rtc";
927
+					regulator-name = "+V1.2_VDD_RTC";
545928 					regulator-min-microvolt = <1200000>;
546929 					regulator-max-microvolt = <1200000>;
547930 					regulator-always-on;
....@@ -549,10 +932,10 @@
549932 
550933 				/*
551934 				 * +V2.8_AVDD_VDAC:
552
-				 * only required for analog RGB
935
+				 * only required for (unsupported) analog RGB
553936 				 */
554937 				ldo5_reg: ldo5 {
555
-					regulator-name = "avdd_vdac";
938
+					regulator-name = "+V2.8_AVDD_VDAC";
556939 					regulator-min-microvolt = <2800000>;
557940 					regulator-max-microvolt = <2800000>;
558941 					regulator-always-on;
....@@ -564,22 +947,20 @@
564947 				 * granularity
565948 				 */
566949 				ldo6_reg: ldo6 {
567
-					regulator-name = "avdd_plle";
950
+					regulator-name = "+V1.05_AVDD_PLLE";
568951 					regulator-min-microvolt = <1100000>;
569952 					regulator-max-microvolt = <1100000>;
570953 				};
571954 
572
-				/* +V1.2_AVDD_PLL */
573955 				ldo7_reg: ldo7 {
574
-					regulator-name = "avdd_pll";
956
+					regulator-name = "+V1.2_AVDD_PLL";
575957 					regulator-min-microvolt = <1200000>;
576958 					regulator-max-microvolt = <1200000>;
577959 					regulator-always-on;
578960 				};
579961 
580
-				/* +V1.0_VDD_DDR_HS */
581962 				ldo8_reg: ldo8 {
582
-					regulator-name = "vdd_ddr_hs";
963
+					regulator-name = "+V1.0_VDD_DDR_HS";
583964 					regulator-min-microvolt = <1000000>;
584965 					regulator-max-microvolt = <1000000>;
585966 					regulator-always-on;
....@@ -588,20 +969,25 @@
588969 		};
589970 
590971 		/* STMPE811 touch screen controller */
591
-		stmpe811@41 {
972
+		touchscreen@41 {
592973 			compatible = "st,stmpe811";
593974 			reg = <0x41>;
594
-			interrupts = <TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
595
-			interrupt-parent = <&gpio>;
975
+			irq-gpio = <&gpio TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
596976 			interrupt-controller;
597977 			id = <0>;
598978 			blocks = <0x5>;
599979 			irq-trigger = <0x1>;
980
+			/* 3.25 MHz ADC clock speed */
981
+			st,adc-freq = <1>;
982
+			/* 12-bit ADC */
983
+			st,mod-12b = <1>;
984
+			/* internal ADC reference */
985
+			st,ref-sel = <0>;
986
+			/* ADC converstion time: 80 clocks */
987
+			st,sample-time = <4>;
600988 
601989 			stmpe_touchscreen {
602990 				compatible = "st,stmpe-ts";
603
-				/* 3.25 MHz ADC clock speed */
604
-				st,adc-freq = <1>;
605991 				/* 8 sample average control */
606992 				st,ave-ctrl = <3>;
607993 				/* 7 length fractional part in z */
....@@ -611,22 +997,22 @@
611997 				 * current limit value
612998 				 */
613999 				st,i-drive = <1>;
614
-				/* 12-bit ADC */
615
-				st,mod-12b = <1>;
616
-				/* internal ADC reference */
617
-				st,ref-sel = <0>;
618
-				/* ADC converstion time: 80 clocks */
619
-				st,sample-time = <4>;
6201000 				/* 1 ms panel driver settling time */
6211001 				st,settling = <3>;
6221002 				/* 5 ms touch detect interrupt delay */
6231003 				st,touch-det-delay = <5>;
6241004 			};
1005
+
1006
+			stmpe_adc {
1007
+				compatible = "st,stmpe-adc";
1008
+				/* forbid to use ADC channels 3-0 (touch) */
1009
+				st,norequest-mask = <0x0F>;
1010
+			};
6251011 		};
6261012 
6271013 		/*
6281014 		 * LM95245 temperature sensor
629
-		 * Note: OVERT_N directly connected to PMIC PWRDN
1015
+		 * Note: OVERT1# directly connected to TPS65911 PMIC PWRDN
6301016 		 */
6311017 		temp-sensor@4c {
6321018 			compatible = "national,lm95245";
....@@ -634,7 +1020,7 @@
6341020 		};
6351021 
6361022 		/* SW: +V1.2_VDD_CORE */
637
-		tps62362@60 {
1023
+		regulator@60 {
6381024 			compatible = "ti,tps62362";
6391025 			reg = <0x60>;
6401026 
....@@ -688,6 +1074,18 @@
6881074 		nvidia,core-pwr-off-time = <0>;
6891075 		nvidia,core-power-req-active-high;
6901076 		nvidia,sys-clock-req-active-high;
1077
+
1078
+		/* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */
1079
+		i2c-thermtrip {
1080
+			nvidia,i2c-controller-id = <4>;
1081
+			nvidia,bus-addr = <0x2d>;
1082
+			nvidia,reg-addr = <0x3f>;
1083
+			nvidia,reg-data = <0x1>;
1084
+		};
1085
+	};
1086
+
1087
+	hda@70030000 {
1088
+		status = "okay";
6911089 	};
6921090 
6931091 	ahub@70080000 {
....@@ -697,77 +1095,69 @@
6971095 	};
6981096 
6991097 	/* eMMC */
700
-	sdhci@78000600 {
1098
+	mmc@78000600 {
7011099 		status = "okay";
7021100 		bus-width = <8>;
7031101 		non-removable;
1102
+		vmmc-supply = <&reg_module_3v3>; /* VCC */
1103
+		vqmmc-supply = <&reg_1v8_vio>; /* VCCQ */
1104
+		mmc-ddr-1_8v;
7041105 	};
7051106 
706
-	clocks {
707
-		compatible = "simple-bus";
708
-		#address-cells = <1>;
709
-		#size-cells = <0>;
710
-
711
-		clk32k_in: clk@0 {
712
-			compatible = "fixed-clock";
713
-			reg = <0>;
714
-			#clock-cells = <0>;
715
-			clock-frequency = <32768>;
716
-		};
717
-
718
-		clk16m: clk@1 {
719
-			compatible = "fixed-clock";
720
-			reg = <1>;
721
-			#clock-cells = <0>;
722
-			clock-frequency = <16000000>;
723
-			clock-output-names = "clk16m";
724
-		};
1107
+	clk32k_in: xtal1 {
1108
+		compatible = "fixed-clock";
1109
+		#clock-cells = <0>;
1110
+		clock-frequency = <32768>;
7251111 	};
7261112 
727
-	regulators {
728
-		compatible = "simple-bus";
729
-		#address-cells = <1>;
730
-		#size-cells = <0>;
1113
+	clk16m: osc4 {
1114
+		compatible = "fixed-clock";
1115
+		#clock-cells = <0>;
1116
+		clock-frequency = <16000000>;
1117
+	};
7311118 
732
-		avdd_hdmi_pll_1v8_reg: regulator@100 {
733
-			compatible = "regulator-fixed";
734
-			reg = <100>;
735
-			regulator-name = "+V1.8_AVDD_HDMI_PLL";
736
-			regulator-min-microvolt = <1800000>;
737
-			regulator-max-microvolt = <1800000>;
738
-			enable-active-high;
739
-			gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
740
-			vin-supply = <&vio_reg>;
741
-		};
1119
+	reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll {
1120
+		compatible = "regulator-fixed";
1121
+		regulator-name = "+V1.8_AVDD_HDMI_PLL";
1122
+		regulator-min-microvolt = <1800000>;
1123
+		regulator-max-microvolt = <1800000>;
1124
+		enable-active-high;
1125
+		gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
1126
+		vin-supply = <&reg_1v8_vio>;
1127
+	};
7421128 
743
-		sys_3v3_reg: regulator@101 {
744
-			compatible = "regulator-fixed";
745
-			reg = <101>;
746
-			regulator-name = "3v3";
747
-			regulator-min-microvolt = <3300000>;
748
-			regulator-max-microvolt = <3300000>;
749
-			regulator-always-on;
750
-		};
1129
+	reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
1130
+		compatible = "regulator-fixed";
1131
+		regulator-name = "+V3.3_AVDD_HDMI";
1132
+		regulator-min-microvolt = <3300000>;
1133
+		regulator-max-microvolt = <3300000>;
1134
+		enable-active-high;
1135
+		gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
1136
+		vin-supply = <&reg_module_3v3>;
1137
+	};
7511138 
752
-		avdd_hdmi_3v3_reg: regulator@102 {
753
-			compatible = "regulator-fixed";
754
-			reg = <102>;
755
-			regulator-name = "+V3.3_AVDD_HDMI";
756
-			regulator-min-microvolt = <3300000>;
757
-			regulator-max-microvolt = <3300000>;
758
-			enable-active-high;
759
-			gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
760
-			vin-supply = <&sys_3v3_reg>;
761
-		};
1139
+	reg_5v0_charge_pump: regulator-5v0-charge-pump {
1140
+		compatible = "regulator-fixed";
1141
+		regulator-name = "+V5.0";
1142
+		regulator-min-microvolt = <5000000>;
1143
+		regulator-max-microvolt = <5000000>;
1144
+		regulator-always-on;
1145
+	};
7621146 
763
-		charge_pump_5v0_reg: regulator@103 {
764
-			compatible = "regulator-fixed";
765
-			reg = <103>;
766
-			regulator-name = "5v0";
767
-			regulator-min-microvolt = <5000000>;
768
-			regulator-max-microvolt = <5000000>;
769
-			regulator-always-on;
770
-		};
1147
+	reg_module_3v3: regulator-module-3v3 {
1148
+		compatible = "regulator-fixed";
1149
+		regulator-name = "+V3.3";
1150
+		regulator-min-microvolt = <3300000>;
1151
+		regulator-max-microvolt = <3300000>;
1152
+		regulator-always-on;
1153
+	};
1154
+
1155
+	reg_module_3v3_audio: regulator-module-3v3-audio {
1156
+		compatible = "regulator-fixed";
1157
+		regulator-name = "+V3.3_AUDIO_AVDD_S";
1158
+		regulator-min-microvolt = <3300000>;
1159
+		regulator-max-microvolt = <3300000>;
1160
+		regulator-always-on;
7711161 	};
7721162 
7731163 	sound {
....@@ -782,7 +1172,13 @@
7821172 		nvidia,audio-codec = <&sgtl5000>;
7831173 		clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
7841174 			 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
785
-			 <&tegra_car TEGRA30_CLK_EXTERN1>;
1175
+			 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
7861176 		clock-names = "pll_a", "pll_a_out0", "mclk";
1177
+
1178
+		assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
1179
+				  <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
1180
+
1181
+		assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1182
+					 <&tegra_car TEGRA30_CLK_EXTERN1>;
7871183 	};
7881184 };