| .. | .. |
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| 66 | 66 | |
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| 67 | 67 | &gmac { |
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| 68 | 68 | pinctrl-names = "default"; |
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| 69 | | - pinctrl-0 = <&gmac_pins_mii_a>; |
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| 70 | | - phy = <&phy1>; |
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| 69 | + pinctrl-0 = <&gmac_mii_pins>; |
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| 70 | + phy-handle = <&phy1>; |
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| 71 | 71 | phy-mode = "mii"; |
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| 72 | 72 | status = "okay"; |
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| 73 | | - phy1: ethernet-phy@1 { |
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| 74 | | - reg = <1>; |
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| 75 | | - }; |
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| 76 | 73 | }; |
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| 77 | 74 | |
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| 78 | 75 | &ir { |
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| 79 | 76 | pinctrl-names = "default"; |
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| 80 | | - pinctrl-0 = <&ir_pins_a>; |
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| 77 | + pinctrl-0 = <&s_ir_rx_pin>; |
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| 81 | 78 | status = "okay"; |
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| 79 | +}; |
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| 80 | + |
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| 81 | +&mdio { |
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| 82 | + phy1: ethernet-phy@1 { |
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| 83 | + reg = <1>; |
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| 84 | + }; |
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| 82 | 85 | }; |
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| 83 | 86 | |
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| 84 | 87 | &ohci1 { |
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| .. | .. |
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| 87 | 90 | |
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| 88 | 91 | &uart0 { |
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| 89 | 92 | pinctrl-names = "default"; |
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| 90 | | - pinctrl-0 = <&uart0_pins_a>; |
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| 93 | + pinctrl-0 = <&uart0_ph_pins>; |
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| 91 | 94 | status = "okay"; |
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| 92 | 95 | }; |
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| 93 | 96 | |
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