forked from ~ljy/RK356X_SDK_RELEASE
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hc
2023-12-06 08f87f769b595151be1afeff53e144f543faa614 
 kernel/arch/arm/boot/dts/stm32h743.dtsi
....@@ -40,13 +40,15 @@
4040  *     OTHER DEALINGS IN THE SOFTWARE.
4141  */
4242 
43
-#include "skeleton.dtsi"
4443 #include "armv7-m.dtsi"
4544 #include <dt-bindings/clock/stm32h7-clks.h>
4645 #include <dt-bindings/mfd/stm32h7-rcc.h>
4746 #include <dt-bindings/interrupt-controller/irq.h>
4847 
4948 / {
49
+	#address-cells = <1>;
50
+	#size-cells = <1>;
51
+
5052 	clocks {
5153 		clk_hse: clk-hse {
5254 			#clock-cells = <0>;
....@@ -108,6 +110,7 @@
108110 			compatible = "st,stm32h7-spi";
109111 			reg = <0x40003800 0x400>;
110112 			interrupts = <36>;
113
+			resets = <&rcc STM32H7_APB1L_RESET(SPI2)>;
111114 			clocks = <&rcc SPI2_CK>;
112115 			status = "disabled";
113116 
....@@ -119,12 +122,13 @@
119122 			compatible = "st,stm32h7-spi";
120123 			reg = <0x40003c00 0x400>;
121124 			interrupts = <51>;
125
+			resets = <&rcc STM32H7_APB1L_RESET(SPI3)>;
122126 			clocks = <&rcc SPI3_CK>;
123127 			status = "disabled";
124128 		};
125129 
126130 		usart2: serial@40004400 {
127
-			compatible = "st,stm32f7-uart";
131
+			compatible = "st,stm32h7-uart";
128132 			reg = <0x40004400 0x400>;
129133 			interrupts = <38>;
130134 			status = "disabled";
....@@ -178,21 +182,21 @@
178182 
179183 			dac1: dac@1 {
180184 				compatible = "st,stm32-dac";
181
-				#io-channels-cells = <1>;
185
+				#io-channel-cells = <1>;
182186 				reg = <1>;
183187 				status = "disabled";
184188 			};
185189 
186190 			dac2: dac@2 {
187191 				compatible = "st,stm32-dac";
188
-				#io-channels-cells = <1>;
192
+				#io-channel-cells = <1>;
189193 				reg = <2>;
190194 				status = "disabled";
191195 			};
192196 		};
193197 
194198 		usart1: serial@40011000 {
195
-			compatible = "st,stm32f7-uart";
199
+			compatible = "st,stm32h7-uart";
196200 			reg = <0x40011000 0x400>;
197201 			interrupts = <37>;
198202 			status = "disabled";
....@@ -205,6 +209,7 @@
205209 			compatible = "st,stm32h7-spi";
206210 			reg = <0x40013000 0x400>;
207211 			interrupts = <35>;
212
+			resets = <&rcc STM32H7_APB2_RESET(SPI1)>;
208213 			clocks = <&rcc SPI1_CK>;
209214 			status = "disabled";
210215 		};
....@@ -215,6 +220,7 @@
215220 			compatible = "st,stm32h7-spi";
216221 			reg = <0x40013400 0x400>;
217222 			interrupts = <84>;
223
+			resets = <&rcc STM32H7_APB2_RESET(SPI4)>;
218224 			clocks = <&rcc SPI4_CK>;
219225 			status = "disabled";
220226 		};
....@@ -225,11 +231,12 @@
225231 			compatible = "st,stm32h7-spi";
226232 			reg = <0x40015000 0x400>;
227233 			interrupts = <85>;
234
+			resets = <&rcc STM32H7_APB2_RESET(SPI5)>;
228235 			clocks = <&rcc SPI5_CK>;
229236 			status = "disabled";
230237 		};
231238 
232
-		dma1: dma@40020000 {
239
+		dma1: dma-controller@40020000 {
233240 			compatible = "st,stm32-dma";
234241 			reg = <0x40020000 0x400>;
235242 			interrupts = <11>,
....@@ -247,7 +254,7 @@
247254 			status = "disabled";
248255 		};
249256 
250
-		dma2: dma@40020400 {
257
+		dma2: dma-controller@40020400 {
251258 			compatible = "st,stm32-dma";
252259 			reg = <0x40020400 0x400>;
253260 			interrupts = <56>,
....@@ -327,7 +334,17 @@
327334 			status = "disabled";
328335 		};
329336 
330
-		mdma1: dma@52000000 {
337
+		ltdc: display-controller@50001000 {
338
+			compatible = "st,stm32-ltdc";
339
+			reg = <0x50001000 0x200>;
340
+			interrupts = <88>, <89>;
341
+			resets = <&rcc STM32H7_APB3_RESET(LTDC)>;
342
+			clocks = <&rcc LTDC_CK>;
343
+			clock-names = "lcd";
344
+			status = "disabled";
345
+		};
346
+
347
+		mdma1: dma-controller@52000000 {
331348 			compatible = "st,stm32h7-mdma";
332349 			reg = <0x52000000 0x1000>;
333350 			interrupts = <122>;
....@@ -335,6 +352,20 @@
335352 			#dma-cells = <5>;
336353 			dma-channels = <16>;
337354 			dma-requests = <32>;
355
+		};
356
+
357
+		sdmmc1: sdmmc@52007000 {
358
+			compatible = "arm,pl18x", "arm,primecell";
359
+			arm,primecell-periphid = <0x10153180>;
360
+			reg = <0x52007000 0x1000>;
361
+			interrupts = <49>;
362
+			interrupt-names	= "cmd_irq";
363
+			clocks = <&rcc SDMMC1_CK>;
364
+			clock-names = "apb_pclk";
365
+			resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
366
+			cap-sd-highspeed;
367
+			cap-mmc-highspeed;
368
+			max-frequency = <120000000>;
338369 		};
339370 
340371 		exti: interrupt-controller@58000000 {
....@@ -345,8 +376,8 @@
345376 			interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <62>, <76>;
346377 		};
347378 
348
-		syscfg: system-config@58000400 {
349
-			compatible = "syscon";
379
+		syscfg: syscon@58000400 {
380
+			compatible = "st,stm32-syscfg", "syscon";
350381 			reg = <0x58000400 0x400>;
351382 		};
352383 
....@@ -356,6 +387,7 @@
356387 			compatible = "st,stm32h7-spi";
357388 			reg = <0x58001400 0x400>;
358389 			interrupts = <86>;
390
+			resets = <&rcc STM32H7_APB4_RESET(SPI6)>;
359391 			clocks = <&rcc SPI6_CK>;
360392 			status = "disabled";
361393 		};
....@@ -467,8 +499,7 @@
467499 			assigned-clock-parents = <&rcc LSE_CK>;
468500 			interrupt-parent = <&exti>;
469501 			interrupts = <17 IRQ_TYPE_EDGE_RISING>;
470
-			interrupt-names = "alarm";
471
-			st,syscfg = <&pwrcfg>;
502
+			st,syscfg = <&pwrcfg 0x00 0x100>;
472503 			status = "disabled";
473504 		};
474505 
....@@ -482,7 +513,7 @@
482513 		};
483514 
484515 		pwrcfg: power-config@58024800 {
485
-			compatible = "syscon";
516
+			compatible = "st,stm32-power-config", "syscon";
486517 			reg = <0x58024800 0x400>;
487518 		};
488519 
....@@ -507,6 +538,19 @@
507538 				status = "disabled";
508539 			};
509540 		};
541
+
542
+		mac: ethernet@40028000 {
543
+			compatible = "st,stm32-dwmac", "snps,dwmac-4.10a";
544
+			reg = <0x40028000 0x8000>;
545
+			reg-names = "stmmaceth";
546
+			interrupts = <61>;
547
+			interrupt-names = "macirq";
548
+			clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
549
+			clocks = <&rcc ETH1MAC_CK>, <&rcc ETH1TX_CK>, <&rcc ETH1RX_CK>;
550
+			st,syscon = <&syscfg 0x4>;
551
+			snps,pbl = <8>;
552
+			status = "disabled";
553
+		};
510554 	};
511555 };
512556