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2023-12-06 08f87f769b595151be1afeff53e144f543faa614 
 kernel/arch/arm/boot/dts/socfpga.dtsi
....@@ -1,18 +1,6 @@
1
+// SPDX-License-Identifier: GPL-2.0+
12 /*
2
- *  Copyright (C) 2012 Altera <www.altera.com>
3
- *
4
- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License as published by
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- * the Free Software Foundation; either version 2 of the License, or
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- * (at your option) any later version.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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+ * Copyright (C) 2012 Altera <www.altera.com>
164  */
175 
186 #include <dt-bindings/reset/altr,rst-mgr.h>
....@@ -22,8 +10,6 @@
2210 	#size-cells = <1>;
2311 
2412 	aliases {
25
-		ethernet0 = &gmac0;
26
-		ethernet1 = &gmac1;
2713 		serial0 = &uart0;
2814 		serial1 = &uart1;
2915 		timer0 = &timer0;
....@@ -98,6 +84,8 @@
9884 				#dma-requests = <32>;
9985 				clocks = <&l4_main_clk>;
10086 				clock-names = "apb_pclk";
87
+				resets = <&rst DMA_RESET>;
88
+				reset-names = "dma";
10189 			};
10290 		};
10391 
....@@ -114,6 +102,7 @@
114102 			reg = <0xffc00000 0x1000>;
115103 			interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
116104 			clocks = <&can0_clk>;
105
+			resets = <&rst CAN0_RESET>;
117106 			status = "disabled";
118107 		};
119108 
....@@ -122,6 +111,7 @@
122111 			reg = <0xffc01000 0x1000>;
123112 			interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
124113 			clocks = <&can1_clk>;
114
+			resets = <&rst CAN1_RESET>;
125115 			status = "disabled";
126116 		};
127117 
....@@ -483,10 +473,17 @@
483473 						clk-gate = <0xa0 9>;
484474 					};
485475 
476
+					nand_ecc_clk: nand_ecc_clk {
477
+						#clock-cells = <0>;
478
+						compatible = "altr,socfpga-gate-clk";
479
+						clocks = <&nand_x_clk>;
480
+						clk-gate = <0xa0 9>;
481
+					};
482
+
486483 					nand_clk: nand_clk {
487484 						#clock-cells = <0>;
488485 						compatible = "altr,socfpga-gate-clk";
489
-						clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
486
+						clocks = <&nand_x_clk>;
490487 						clk-gate = <0xa0 10>;
491488 						fixed-divider = <4>;
492489 					};
....@@ -534,6 +531,7 @@
534531 			reg = <0xff400000 0x100000>;
535532 			resets = <&rst LWHPS2FPGA_RESET>;
536533 			clocks = <&l4_main_clk>;
534
+			status = "disabled";
537535 		};
538536 
539537 		fpga_bridge1: fpga_bridge@ff500000 {
....@@ -541,6 +539,21 @@
541539 			reg = <0xff500000 0x10000>;
542540 			resets = <&rst HPS2FPGA_RESET>;
543541 			clocks = <&l4_main_clk>;
542
+			status = "disabled";
543
+		};
544
+
545
+		fpga_bridge2: fpga-bridge@ff600000 {
546
+			compatible = "altr,socfpga-fpga2hps-bridge";
547
+			reg = <0xff600000 0x100000>;
548
+			resets = <&rst FPGA2HPS_RESET>;
549
+			clocks = <&l4_main_clk>;
550
+			status = "disabled";
551
+		};
552
+
553
+		fpga_bridge3: fpga-bridge@ffc25080 {
554
+			compatible = "altr,socfpga-fpga2sdram-bridge";
555
+			reg = <0xffc25080 0x4>;
556
+			status = "disabled";
544557 		};
545558 
546559 		fpgamgr0: fpgamgr@ff706000 {
....@@ -592,6 +605,7 @@
592605 			compatible = "snps,dw-apb-gpio";
593606 			reg = <0xff708000 0x1000>;
594607 			clocks = <&l4_mp_clk>;
608
+			resets = <&rst GPIO0_RESET>;
595609 			status = "disabled";
596610 
597611 			porta: gpio-controller@0 {
....@@ -612,6 +626,7 @@
612626 			compatible = "snps,dw-apb-gpio";
613627 			reg = <0xff709000 0x1000>;
614628 			clocks = <&l4_mp_clk>;
629
+			resets = <&rst GPIO1_RESET>;
615630 			status = "disabled";
616631 
617632 			portb: gpio-controller@0 {
....@@ -632,6 +647,7 @@
632647 			compatible = "snps,dw-apb-gpio";
633648 			reg = <0xff70a000 0x1000>;
634649 			clocks = <&l4_mp_clk>;
650
+			resets = <&rst GPIO2_RESET>;
635651 			status = "disabled";
636652 
637653 			portc: gpio-controller@0 {
....@@ -742,19 +758,21 @@
742758 			#size-cells = <0>;
743759 			clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>;
744760 			clock-names = "biu", "ciu";
761
+			resets = <&rst SDMMC_RESET>;
745762 			status = "disabled";
746763 		};
747764 
748765 		nand0: nand@ff900000 {
749766 			#address-cells = <0x1>;
750
-			#size-cells = <0x1>;
767
+			#size-cells = <0x0>;
751768 			compatible = "altr,socfpga-denali-nand";
752769 			reg = <0xff900000 0x100000>,
753770 			      <0xffb80000 0x10000>;
754771 			reg-names = "nand_data", "denali_reg";
755772 			interrupts = <0x0 0x90 0x4>;
756
-			dma-mask = <0xffffffff>;
757
-			clocks = <&nand_x_clk>;
773
+			clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
774
+			clock-names = "nand", "nand_x", "ecc";
775
+			resets = <&rst NAND_RESET>;
758776 			status = "disabled";
759777 		};
760778 
....@@ -765,7 +783,7 @@
765783 
766784 		qspi: spi@ff705000 {
767785 			compatible = "cdns,qspi-nor";
768
-                        #address-cells = <1>;
786
+			#address-cells = <1>;
769787 			#size-cells = <0>;
770788 			reg = <0xff705000 0x1000>,
771789 			      <0xffa00000 0x1000>;
....@@ -774,6 +792,7 @@
774792 			cdns,fifo-width = <4>;
775793 			cdns,trigger-address = <0x00000000>;
776794 			clocks = <&qspi_clk>;
795
+			resets = <&rst QSPI_RESET>;
777796 			status = "disabled";
778797 		};
779798 
....@@ -792,6 +811,7 @@
792811 		sdr: sdr@ffc25000 {
793812 			compatible = "altr,sdr-ctl", "syscon";
794813 			reg = <0xffc25000 0x1000>;
814
+			resets = <&rst SDR_RESET>;
795815 		};
796816 
797817 		sdramedac {
....@@ -808,6 +828,8 @@
808828 			interrupts = <0 154 4>;
809829 			num-cs = <4>;
810830 			clocks = <&spi_m_clk>;
831
+			resets = <&rst SPIM0_RESET>;
832
+			reset-names = "spi";
811833 			status = "disabled";
812834 		};
813835 
....@@ -819,6 +841,8 @@
819841 			interrupts = <0 155 4>;
820842 			num-cs = <4>;
821843 			clocks = <&spi_m_clk>;
844
+			resets = <&rst SPIM1_RESET>;
845
+			reset-names = "spi";
822846 			status = "disabled";
823847 		};
824848 
....@@ -841,6 +865,8 @@
841865 			reg = <0xffc08000 0x1000>;
842866 			clocks = <&l4_sp_clk>;
843867 			clock-names = "timer";
868
+			resets = <&rst SPTIMER0_RESET>;
869
+			reset-names = "timer";
844870 		};
845871 
846872 		timer1: timer1@ffc09000 {
....@@ -849,6 +875,8 @@
849875 			reg = <0xffc09000 0x1000>;
850876 			clocks = <&l4_sp_clk>;
851877 			clock-names = "timer";
878
+			resets = <&rst SPTIMER1_RESET>;
879
+			reset-names = "timer";
852880 		};
853881 
854882 		timer2: timer2@ffd00000 {
....@@ -857,6 +885,8 @@
857885 			reg = <0xffd00000 0x1000>;
858886 			clocks = <&osc1>;
859887 			clock-names = "timer";
888
+			resets = <&rst OSC1TIMER0_RESET>;
889
+			reset-names = "timer";
860890 		};
861891 
862892 		timer3: timer3@ffd01000 {
....@@ -865,6 +895,8 @@
865895 			reg = <0xffd01000 0x1000>;
866896 			clocks = <&osc1>;
867897 			clock-names = "timer";
898
+			resets = <&rst OSC1TIMER1_RESET>;
899
+			reset-names = "timer";
868900 		};
869901 
870902 		uart0: serial0@ffc02000 {
....@@ -877,6 +909,7 @@
877909 			dmas = <&pdma 28>,
878910 			       <&pdma 29>;
879911 			dma-names = "tx", "rx";
912
+			resets = <&rst UART0_RESET>;
880913 		};
881914 
882915 		uart1: serial1@ffc03000 {
....@@ -889,6 +922,7 @@
889922 			dmas = <&pdma 30>,
890923 			       <&pdma 31>;
891924 			dma-names = "tx", "rx";
925
+			resets = <&rst UART1_RESET>;
892926 		};
893927 
894928 		usbphy0: usbphy {
....@@ -928,6 +962,7 @@
928962 			reg = <0xffd02000 0x1000>;
929963 			interrupts = <0 171 4>;
930964 			clocks = <&osc1>;
965
+			resets = <&rst L4WD0_RESET>;
931966 			status = "disabled";
932967 		};
933968 
....@@ -936,6 +971,7 @@
936971 			reg = <0xffd03000 0x1000>;
937972 			interrupts = <0 172 4>;
938973 			clocks = <&osc1>;
974
+			resets = <&rst L4WD1_RESET>;
939975 			status = "disabled";
940976 		};
941977 	};