forked from ~ljy/RK356X_SDK_RELEASE
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hc
2023-12-06 08f87f769b595151be1afeff53e144f543faa614 
 kernel/arch/arm/boot/dts/qcom-apq8084.dtsi
....@@ -1,12 +1,13 @@
11 // SPDX-License-Identifier: GPL-2.0
22 /dts-v1/;
33 
4
-#include "skeleton.dtsi"
5
-
4
+#include <dt-bindings/interrupt-controller/arm-gic.h>
65 #include <dt-bindings/clock/qcom,gcc-apq8084.h>
76 #include <dt-bindings/gpio/gpio.h>
87 
98 / {
9
+	#address-cells = <1>;
10
+	#size-cells = <1>;
1011 	model = "Qualcomm APQ 8084";
1112 	compatible = "qcom,apq8084";
1213 	interrupt-parent = <&intc>;
....@@ -85,6 +86,11 @@
8586 				min-residency-us = <2000>;
8687 			};
8788 		};
89
+	};
90
+
91
+	memory {
92
+		device_type = "memory";
93
+		reg = <0x0 0x0>;
8894 	};
8995 
9096 	firmware {
....@@ -179,7 +185,7 @@
179185 
180186 	cpu-pmu {
181187 		compatible = "qcom,krait-pmu";
182
-		interrupts = <1 7 0xf04>;
188
+		interrupts = <GIC_PPI 7 0xf04>;
183189 	};
184190 
185191 	clocks {
....@@ -198,10 +204,10 @@
198204 
199205 	timer {
200206 		compatible = "arm,armv7-timer";
201
-		interrupts = <1 2 0xf08>,
202
-			     <1 3 0xf08>,
203
-			     <1 4 0xf08>,
204
-			     <1 1 0xf08>;
207
+		interrupts = <GIC_PPI 2 0xf08>,
208
+			     <GIC_PPI 3 0xf08>,
209
+			     <GIC_PPI 4 0xf08>,
210
+			     <GIC_PPI 1 0xf08>;
205211 		clock-frequency = <19200000>;
206212 	};
207213 
....@@ -248,12 +254,13 @@
248254 
249255 		tsens: thermal-sensor@fc4a8000 {
250256 			compatible = "qcom,msm8974-tsens";
251
-			reg = <0xfc4a8000 0x2000>;
257
+			reg = <0xfc4a9000 0x1000>, /* TM */
258
+			      <0xfc4a8000 0x1000>; /* SROT */
252259 			nvmem-cells = <&tsens_calib>, <&tsens_backup>;
253260 			nvmem-cell-names = "calib", "calib_backup";
261
+			#qcom,sensors = <11>;
254262 			#thermal-sensor-cells = <1>;
255263 		};
256
-
257264 		timer@f9020000 {
258265 			#address-cells = <1>;
259266 			#size-cells = <1>;
....@@ -264,50 +271,50 @@
264271 
265272 			frame@f9021000 {
266273 				frame-number = <0>;
267
-				interrupts = <0 8 0x4>,
268
-					     <0 7 0x4>;
274
+				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
275
+					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
269276 				reg = <0xf9021000 0x1000>,
270277 				      <0xf9022000 0x1000>;
271278 			};
272279 
273280 			frame@f9023000 {
274281 				frame-number = <1>;
275
-				interrupts = <0 9 0x4>;
282
+				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
276283 				reg = <0xf9023000 0x1000>;
277284 				status = "disabled";
278285 			};
279286 
280287 			frame@f9024000 {
281288 				frame-number = <2>;
282
-				interrupts = <0 10 0x4>;
289
+				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
283290 				reg = <0xf9024000 0x1000>;
284291 				status = "disabled";
285292 			};
286293 
287294 			frame@f9025000 {
288295 				frame-number = <3>;
289
-				interrupts = <0 11 0x4>;
296
+				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
290297 				reg = <0xf9025000 0x1000>;
291298 				status = "disabled";
292299 			};
293300 
294301 			frame@f9026000 {
295302 				frame-number = <4>;
296
-				interrupts = <0 12 0x4>;
303
+				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
297304 				reg = <0xf9026000 0x1000>;
298305 				status = "disabled";
299306 			};
300307 
301308 			frame@f9027000 {
302309 				frame-number = <5>;
303
-				interrupts = <0 13 0x4>;
310
+				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
304311 				reg = <0xf9027000 0x1000>;
305312 				status = "disabled";
306313 			};
307314 
308315 			frame@f9028000 {
309316 				frame-number = <6>;
310
-				interrupts = <0 14 0x4>;
317
+				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
311318 				reg = <0xf9028000 0x1000>;
312319 				status = "disabled";
313320 			};
....@@ -396,26 +403,27 @@
396403 			compatible = "qcom,apq8084-pinctrl";
397404 			reg = <0xfd510000 0x4000>;
398405 			gpio-controller;
406
+			gpio-ranges = <&tlmm 0 0 147>;
399407 			#gpio-cells = <2>;
400408 			interrupt-controller;
401409 			#interrupt-cells = <2>;
402
-			interrupts = <0 208 0>;
410
+			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
403411 		};
404412 
405413 		blsp2_uart2: serial@f995e000 {
406414 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
407415 			reg = <0xf995e000 0x1000>;
408
-			interrupts = <0 114 0x0>;
416
+			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
409417 			clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
410418 			clock-names = "core", "iface";
411419 			status = "disabled";
412420 		};
413421 
414422 		sdhci@f9824900 {
415
-			compatible = "qcom,sdhci-msm-v4";
423
+			compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
416424 			reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
417425 			reg-names = "hc_mem", "core_mem";
418
-			interrupts = <0 123 0>, <0 138 0>;
426
+			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
419427 			interrupt-names = "hc_irq", "pwr_irq";
420428 			clocks = <&gcc GCC_SDCC1_APPS_CLK>,
421429 				 <&gcc GCC_SDCC1_AHB_CLK>,
....@@ -425,10 +433,10 @@
425433 		};
426434 
427435 		sdhci@f98a4900 {
428
-			compatible = "qcom,sdhci-msm-v4";
436
+			compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
429437 			reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
430438 			reg-names = "hc_mem", "core_mem";
431
-			interrupts = <0 125 0>, <0 221 0>;
439
+			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
432440 			interrupt-names = "hc_irq", "pwr_irq";
433441 			clocks = <&gcc GCC_SDCC2_APPS_CLK>,
434442 				 <&gcc GCC_SDCC2_AHB_CLK>,
....@@ -444,7 +452,7 @@
444452 			      <0xfc4cb000 0x1000>,
445453 			      <0xfc4ca000 0x1000>;
446454 			interrupt-names = "periph_irq";
447
-			interrupts = <0 190 0>;
455
+			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
448456 			qcom,ee = <0>;
449457 			qcom,channel = <0>;
450458 			#address-cells = <2>;
....@@ -458,7 +466,7 @@
458466 		compatible = "qcom,smd";
459467 
460468 		rpm {
461
-			interrupts = <0 168 1>;
469
+			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
462470 			qcom,ipc = <&apcs 8 0>;
463471 			qcom,smd-edge = <15>;
464472