add dts config

hc

2023-12-06 08f87f769b595151be1afeff53e144f543faa614

 kernel/arch/arm/boot/dts/integratorcp.dts
..
..
@@ -192,6 +192,43 @@
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 		interrupts = <27>;
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 	};
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+	bridge {
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+		compatible = "ti,ths8134a", "ti,ths8134";
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+		#address-cells = <1>;
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+		#size-cells = <0>;
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+
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+		ports {
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+			#address-cells = <1>;
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+			#size-cells = <0>;
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+
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+			port@0 {
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+				reg = <0>;
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+
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+				vga_bridge_in: endpoint {
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+					remote-endpoint = <&clcd_pads_vga_dac>;
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+				};
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+			};
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+
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+			port@1 {
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+				reg = <1>;
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+
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+				vga_bridge_out: endpoint {
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+					remote-endpoint = <&vga_con_in>;
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+				};
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+			};
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+		};
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+	};
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+
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+	vga {
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+		compatible = "vga-connector";
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+
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+		port {
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+			vga_con_in: endpoint {
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+				remote-endpoint = <&vga_bridge_out>;
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+			};
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+		};
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+	};
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+
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 	fpga {
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 		/*
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 		 * These PrimeCells are at the same location and using
..
..
@@ -254,39 +291,27 @@
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 			interrupts = <22>;
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 			clocks = <&auxosc>, <&pclk>;
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 			clock-names = "clcdclk", "apb_pclk";
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+			/* 640x480 16bpp @ 25.175MHz is 36827428 bytes/s */
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+			max-memory-bandwidth = <40000000>;
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-			port {
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-				/*
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-				 * The VGA connected is implemented with a
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-				 * THS8134A triple DAC that can be run in 24bit
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-				 * or 16bit RGB mode.
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-				 */
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-				clcd_pads: endpoint {
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-					remote-endpoint = <&clcd_panel>;
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-					arm,pl11x,tft-r0g0b0-pads = <1 7 13>;
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-				};
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-			};
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-
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-			panel {
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-				compatible = "panel-dpi";
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-
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-				port {
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-					clcd_panel: endpoint {
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-						remote-endpoint = <&clcd_pads>;
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-					};
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-				};
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-
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-				/* Standard 640x480 VGA timings */
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-				panel-timing {
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-					clock-frequency = <25175000>;
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-					hactive = <640>;
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-					hback-porch = <48>;
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-					hfront-porch = <16>;
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-					hsync-len = <96>;
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-					vactive = <480>;
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-					vback-porch = <33>;
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-					vfront-porch = <10>;
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-					vsync-len = <2>;
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+			/*
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+			 * This port is routed through a PLD (Programmable
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+			 * Logic Device) that routes the output from the CLCD
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+			 * (after transformations) to the VGA DAC and also an
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+			 * external panel connector. The PLD is essential for
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+			 * supporting RGB565/BGR565.
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+			 *
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+			 * The signals from the port thus reaches two endpoints.
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+			 * The PLD is managed through a few special bits in the
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+			 * FPGA "sysreg".
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+			 *
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+			 * This arrangement can be clearly seen in
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+			 * ARM DUI 0225D, page 3-41, figure 3-19.
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+			 */
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+			port@0 {
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+				clcd_pads_vga_dac: endpoint {
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+					remote-endpoint = <&vga_bridge_in>;
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+					arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
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 				};
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 			};
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 		};