add dts config

hc

2023-12-06 08f87f769b595151be1afeff53e144f543faa614

 kernel/arch/arm/boot/dts/imx7d.dtsi
..
..
@@ -12,6 +12,8 @@
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 			clock-frequency = <996000000>;
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 			operating-points-v2 = <&cpu0_opp_table>;
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 			#cooling-cells = <2>;
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+			nvmem-cells = <&fuse_grade>;
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+			nvmem-cell-names = "speed_grade";
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 		};
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18
 
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 		cpu1: cpu@1 {
..
..
@@ -20,7 +22,18 @@
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 			reg = <1>;
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 			clock-frequency = <996000000>;
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 			operating-points-v2 = <&cpu0_opp_table>;
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+			#cooling-cells = <2>;
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+			cpu-idle-states = <&cpu_sleep_wait>;
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 		};
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+	};
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+
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+	timer {
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+		compatible = "arm,armv7-timer";
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+		interrupt-parent = <&intc>;
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+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
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 	};
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 	cpu0_opp_table: opp-table {
..
..
@@ -29,14 +42,25 @@
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 		opp-792000000 {
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 			opp-hz = /bits/ 64 <792000000>;
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-			opp-microvolt = <975000>;
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+			opp-microvolt = <1000000>;
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 			clock-latency-ns = <150000>;
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+			opp-supported-hw = <0xd>, <0x7>;
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+			opp-suspend;
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 		};
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 		opp-996000000 {
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 			opp-hz = /bits/ 64 <996000000>;
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-			opp-microvolt = <1075000>;
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+			opp-microvolt = <1100000>;
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 			clock-latency-ns = <150000>;
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+			opp-supported-hw = <0xc>, <0x7>;
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+			opp-suspend;
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+		};
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+
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+		opp-1200000000 {
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+			opp-hz = /bits/ 64 <1200000000>;
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+			opp-microvolt = <1225000>;
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+			clock-latency-ns = <150000>;
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+			opp-supported-hw = <0x8>, <0x3>;
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 			opp-suspend;
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 		};
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 	};
..
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@@ -63,12 +87,34 @@
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 			clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
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 			clock-names = "apb_pclk";
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-			port {
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-				etm1_out_port: endpoint {
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-					remote-endpoint = <&ca_funnel_in_port1>;
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+			out-ports {
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+				port {
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+					etm1_out_port: endpoint {
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+						remote-endpoint = <&ca_funnel_in_port1>;
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+					};
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 				};
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 			};
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 		};
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+
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+		intc: interrupt-controller@31001000 {
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+			compatible = "arm,cortex-a7-gic";
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+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
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+			#interrupt-cells = <3>;
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+			interrupt-controller;
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+			interrupt-parent = <&intc>;
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+			reg = <0x31001000 0x1000>,
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+			      <0x31002000 0x2000>,
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+			      <0x31004000 0x2000>,
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+			      <0x31006000 0x2000>;
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+		};
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+	};
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+};
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+
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+&aips2 {
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+	pcie_phy: pcie-phy@306d0000 {
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+		  compatible = "fsl,imx7d-pcie-phy";
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+		  reg = <0x306d0000 0x10000>;
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+		  status = "disabled";
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 	};
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 };
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..
..
@@ -105,8 +151,9 @@
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 			<&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
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 		clock-names = "ipg", "ahb", "ptp",
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 			"enet_clk_ref", "enet_out";
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-		fsl,num-tx-queues=<3>;
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-		fsl,num-rx-queues=<3>;
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+		fsl,num-tx-queues = <3>;
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+		fsl,num-rx-queues = <3>;
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+		fsl,stop-mode = <&gpr 0x10 4>;
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 		status = "disabled";
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 	};
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..
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@@ -122,6 +169,7 @@
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 		ranges = <0x81000000 0 0          0x4ff80000 0 0x00010000   /* downstream I/O */
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 			  0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */
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 		num-lanes = <1>;
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+		num-viewport = <4>;
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 		interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
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 		interrupt-names = "msi";
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 		#interrupt-cells = <1>;
..
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@@ -146,17 +194,21 @@
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 		fsl,max-link-speed = <2>;
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 		power-domains = <&pgc_pcie_phy>;
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 		resets = <&src IMX7_RESET_PCIEPHY>,
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-			 <&src IMX7_RESET_PCIE_CTRL_APPS_EN>;
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-		reset-names = "pciephy", "apps";
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+			 <&src IMX7_RESET_PCIE_CTRL_APPS_EN>,
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+			 <&src IMX7_RESET_PCIE_CTRL_APPS_TURNOFF>;
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+		reset-names = "pciephy", "apps", "turnoff";
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+		fsl,imx7d-pcie-phy = <&pcie_phy>;
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 		status = "disabled";
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 	};
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 };
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-&ca_funnel_ports {
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+&ca_funnel_in_ports {
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+	#address-cells = <1>;
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+	#size-cells = <0>;
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+
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 	port@1 {
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 		reg = <1>;
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 		ca_funnel_in_port1: endpoint {
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-			slave-mode;
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 			remote-endpoint = <&etm1_out_port>;
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 		};
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 	};