add dts config

hc

2023-12-06 08f87f769b595151be1afeff53e144f543faa614

 kernel/arch/arm/boot/dts/bcm63138.dtsi
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@@ -6,9 +6,9 @@
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 #include <dt-bindings/interrupt-controller/arm-gic.h>
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 #include <dt-bindings/interrupt-controller/irq.h>
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-#include "skeleton.dtsi"
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-
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 / {
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+	#address-cells = <1>;
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+	#size-cells = <1>;
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 	compatible = "brcm,bcm63138";
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 	model = "Broadcom BCM63138 DSL SoC";
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 	interrupt-parent = <&gic>;
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@@ -41,9 +41,6 @@
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 	};
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 	clocks {
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-		#address-cells = <1>;
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-		#size-cells = <0>;
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-
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 		/* UBUS peripheral clock */
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 		periph_clk: periph_clk {
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 			#clock-cells = <0>;
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@@ -94,7 +91,7 @@
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 			reg = <0x1e000 0x100>;
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 		};
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-		gic: interrupt-controller@1e100 {
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+		gic: interrupt-controller@1f000 {
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 			compatible = "arm,cortex-a9-gic";
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 			reg = <0x1f000 0x1000
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 				0x1e100 0x100>;
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@@ -125,7 +122,7 @@
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 						  IRQ_TYPE_LEVEL_HIGH)>;
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 		};
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-		armpll: armpll {
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+		armpll: armpll@20000 {
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 			#clock-cells = <0>;
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 			compatible = "brcm,bcm63138-armpll";
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 			clocks = <&periph_clk>;
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@@ -143,6 +140,37 @@
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 			reg = <0x4800e0 0x10>;
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 			#reset-cells = <2>;
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 		};
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+
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+		ahci: sata@a000 {
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+			compatible = "brcm,bcm63138-ahci", "brcm,sata3-ahci";
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+			reg-names = "ahci", "top-ctrl";
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+			reg = <0xa000 0x9ac>, <0x8040 0x24>;
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+			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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+			#address-cells = <1>;
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+			#size-cells = <0>;
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+			resets = <&pmb0 3 1>;
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+			reset-names = "ahci";
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+			status = "disabled";
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+
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+			sata0: sata-port@0 {
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+				reg = <0>;
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+				phys = <&sata_phy0>;
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+			};
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+		};
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+
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+		sata_phy: sata-phy@8100 {
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+			compatible = "brcm,bcm63138-sata-phy", "brcm,phy-sata3";
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+			reg = <0x8100 0x1e00>;
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+			reg-names = "phy";
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+			#address-cells = <1>;
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+			#size-cells = <0>;
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+			status = "disabled";
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+
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+			sata_phy0: sata-phy@0 {
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+				reg = <0>;
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+				#phy-cells = <0>;
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+			};
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+		};
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 	};
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 	/* Legacy UBUS base */