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2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376 
 kernel/include/linux/pxa2xx_ssp.h
....@@ -1,11 +1,6 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
2
- *  pxa2xx_ssp.h
3
- *
43  *  Copyright (C) 2003 Russell King, All Rights Reserved.
5
- *
6
- * This program is free software; you can redistribute it and/or modify
7
- * it under the terms of the GNU General Public License version 2 as
8
- * published by the Free Software Foundation.
94  *
105  * This driver supports the following PXA CPU/SSP ports:-
116  *
....@@ -19,10 +14,16 @@
1914 #ifndef __LINUX_SSP_H
2015 #define __LINUX_SSP_H
2116 
22
-#include <linux/list.h>
17
+#include <linux/bits.h>
18
+#include <linux/compiler_types.h>
2319 #include <linux/io.h>
24
-#include <linux/of.h>
20
+#include <linux/kconfig.h>
21
+#include <linux/list.h>
22
+#include <linux/types.h>
2523 
24
+struct clk;
25
+struct device;
26
+struct device_node;
2627 
2728 /*
2829  * SSP Serial Port Registers
....@@ -46,130 +47,127 @@
4647 #define SSACDD		(0x40)	/* SSP Audio Clock Dither Divider */
4748 
4849 /* Common PXA2xx bits first */
49
-#define SSCR0_DSS	(0x0000000f)	/* Data Size Select (mask) */
50
+#define SSCR0_DSS	GENMASK(3, 0)	/* Data Size Select (mask) */
5051 #define SSCR0_DataSize(x)  ((x) - 1)	/* Data Size Select [4..16] */
51
-#define SSCR0_FRF	(0x00000030)	/* FRame Format (mask) */
52
+#define SSCR0_FRF	GENMASK(5, 4)	/* FRame Format (mask) */
5253 #define SSCR0_Motorola	(0x0 << 4)	/* Motorola's Serial Peripheral Interface (SPI) */
5354 #define SSCR0_TI	(0x1 << 4)	/* Texas Instruments' Synchronous Serial Protocol (SSP) */
5455 #define SSCR0_National	(0x2 << 4)	/* National Microwire */
55
-#define SSCR0_ECS	(1 << 6)	/* External clock select */
56
-#define SSCR0_SSE	(1 << 7)	/* Synchronous Serial Port Enable */
56
+#define SSCR0_ECS	BIT(6)		/* External clock select */
57
+#define SSCR0_SSE	BIT(7)		/* Synchronous Serial Port Enable */
5758 #define SSCR0_SCR(x)	((x) << 8)	/* Serial Clock Rate (mask) */
5859 
5960 /* PXA27x, PXA3xx */
60
-#define SSCR0_EDSS	(1 << 20)	/* Extended data size select */
61
-#define SSCR0_NCS	(1 << 21)	/* Network clock select */
62
-#define SSCR0_RIM	(1 << 22)	/* Receive FIFO overrrun interrupt mask */
63
-#define SSCR0_TUM	(1 << 23)	/* Transmit FIFO underrun interrupt mask */
64
-#define SSCR0_FRDC	(0x07000000)	/* Frame rate divider control (mask) */
61
+#define SSCR0_EDSS	BIT(20)		/* Extended data size select */
62
+#define SSCR0_NCS	BIT(21)		/* Network clock select */
63
+#define SSCR0_RIM	BIT(22)		/* Receive FIFO overrrun interrupt mask */
64
+#define SSCR0_TUM	BIT(23)		/* Transmit FIFO underrun interrupt mask */
65
+#define SSCR0_FRDC	GENMASK(26, 24)	/* Frame rate divider control (mask) */
6566 #define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24)	/* Time slots per frame [1..8] */
66
-#define SSCR0_FPCKE	(1 << 29)	/* FIFO packing enable */
67
-#define SSCR0_ACS	(1 << 30)	/* Audio clock select */
68
-#define SSCR0_MOD	(1 << 31)	/* Mode (normal or network) */
67
+#define SSCR0_FPCKE	BIT(29)		/* FIFO packing enable */
68
+#define SSCR0_ACS	BIT(30)		/* Audio clock select */
69
+#define SSCR0_MOD	BIT(31)		/* Mode (normal or network) */
6970 
71
+#define SSCR1_RIE	BIT(0)		/* Receive FIFO Interrupt Enable */
72
+#define SSCR1_TIE	BIT(1)		/* Transmit FIFO Interrupt Enable */
73
+#define SSCR1_LBM	BIT(2)		/* Loop-Back Mode */
74
+#define SSCR1_SPO	BIT(3)		/* Motorola SPI SSPSCLK polarity setting */
75
+#define SSCR1_SPH	BIT(4)		/* Motorola SPI SSPSCLK phase setting */
76
+#define SSCR1_MWDS	BIT(5)		/* Microwire Transmit Data Size */
7077 
71
-#define SSCR1_RIE	(1 << 0)	/* Receive FIFO Interrupt Enable */
72
-#define SSCR1_TIE	(1 << 1)	/* Transmit FIFO Interrupt Enable */
73
-#define SSCR1_LBM	(1 << 2)	/* Loop-Back Mode */
74
-#define SSCR1_SPO	(1 << 3)	/* Motorola SPI SSPSCLK polarity setting */
75
-#define SSCR1_SPH	(1 << 4)	/* Motorola SPI SSPSCLK phase setting */
76
-#define SSCR1_MWDS	(1 << 5)	/* Microwire Transmit Data Size */
77
-
78
-#define SSSR_ALT_FRM_MASK	3	/* Masks the SFRM signal number */
79
-#define SSSR_TNF	(1 << 2)	/* Transmit FIFO Not Full */
80
-#define SSSR_RNE	(1 << 3)	/* Receive FIFO Not Empty */
81
-#define SSSR_BSY	(1 << 4)	/* SSP Busy */
82
-#define SSSR_TFS	(1 << 5)	/* Transmit FIFO Service Request */
83
-#define SSSR_RFS	(1 << 6)	/* Receive FIFO Service Request */
84
-#define SSSR_ROR	(1 << 7)	/* Receive FIFO Overrun */
78
+#define SSSR_ALT_FRM_MASK	GENMASK(1, 0)	/* Masks the SFRM signal number */
79
+#define SSSR_TNF		BIT(2)		/* Transmit FIFO Not Full */
80
+#define SSSR_RNE		BIT(3)		/* Receive FIFO Not Empty */
81
+#define SSSR_BSY		BIT(4)		/* SSP Busy */
82
+#define SSSR_TFS		BIT(5)		/* Transmit FIFO Service Request */
83
+#define SSSR_RFS		BIT(6)		/* Receive FIFO Service Request */
84
+#define SSSR_ROR		BIT(7)		/* Receive FIFO Overrun */
8585 
8686 #define RX_THRESH_DFLT	8
8787 #define TX_THRESH_DFLT	8
8888 
89
-#define SSSR_TFL_MASK	(0xf << 8)	/* Transmit FIFO Level mask */
90
-#define SSSR_RFL_MASK	(0xf << 12)	/* Receive FIFO Level mask */
89
+#define SSSR_TFL_MASK	GENMASK(11, 8)	/* Transmit FIFO Level mask */
90
+#define SSSR_RFL_MASK	GENMASK(15, 12)	/* Receive FIFO Level mask */
9191 
92
-#define SSCR1_TFT	(0x000003c0)	/* Transmit FIFO Threshold (mask) */
92
+#define SSCR1_TFT	GENMASK(9, 6)	/* Transmit FIFO Threshold (mask) */
9393 #define SSCR1_TxTresh(x) (((x) - 1) << 6)	/* level [1..16] */
94
-#define SSCR1_RFT	(0x00003c00)	/* Receive FIFO Threshold (mask) */
94
+#define SSCR1_RFT	GENMASK(13, 10)	/* Receive FIFO Threshold (mask) */
9595 #define SSCR1_RxTresh(x) (((x) - 1) << 10)	/* level [1..16] */
9696 
9797 #define RX_THRESH_CE4100_DFLT	2
9898 #define TX_THRESH_CE4100_DFLT	2
9999 
100
-#define CE4100_SSSR_TFL_MASK	(0x3 << 8)	/* Transmit FIFO Level mask */
101
-#define CE4100_SSSR_RFL_MASK	(0x3 << 12)	/* Receive FIFO Level mask */
100
+#define CE4100_SSSR_TFL_MASK	GENMASK(9, 8)	/* Transmit FIFO Level mask */
101
+#define CE4100_SSSR_RFL_MASK	GENMASK(13, 12)	/* Receive FIFO Level mask */
102102 
103
-#define CE4100_SSCR1_TFT	(0x000000c0)	/* Transmit FIFO Threshold (mask) */
103
+#define CE4100_SSCR1_TFT	GENMASK(7, 6)	/* Transmit FIFO Threshold (mask) */
104104 #define CE4100_SSCR1_TxTresh(x) (((x) - 1) << 6)	/* level [1..4] */
105
-#define CE4100_SSCR1_RFT	(0x00000c00)	/* Receive FIFO Threshold (mask) */
105
+#define CE4100_SSCR1_RFT	GENMASK(11, 10)	/* Receive FIFO Threshold (mask) */
106106 #define CE4100_SSCR1_RxTresh(x) (((x) - 1) << 10)	/* level [1..4] */
107107 
108108 /* QUARK_X1000 SSCR0 bit definition */
109
-#define QUARK_X1000_SSCR0_DSS		(0x1F << 0)	/* Data Size Select (mask) */
109
+#define QUARK_X1000_SSCR0_DSS		GENMASK(4, 0)	/* Data Size Select (mask) */
110110 #define QUARK_X1000_SSCR0_DataSize(x)	((x) - 1)	/* Data Size Select [4..32] */
111
-#define QUARK_X1000_SSCR0_FRF		(0x3 << 5)	/* FRame Format (mask) */
111
+#define QUARK_X1000_SSCR0_FRF		GENMASK(6, 5)	/* FRame Format (mask) */
112112 #define QUARK_X1000_SSCR0_Motorola	(0x0 << 5)	/* Motorola's Serial Peripheral Interface (SPI) */
113113 
114114 #define RX_THRESH_QUARK_X1000_DFLT	1
115115 #define TX_THRESH_QUARK_X1000_DFLT	16
116116 
117
-#define QUARK_X1000_SSSR_TFL_MASK	(0x1F << 8)	/* Transmit FIFO Level mask */
118
-#define QUARK_X1000_SSSR_RFL_MASK	(0x1F << 13)	/* Receive FIFO Level mask */
117
+#define QUARK_X1000_SSSR_TFL_MASK	GENMASK(12, 8)	/* Transmit FIFO Level mask */
118
+#define QUARK_X1000_SSSR_RFL_MASK	GENMASK(17, 13)	/* Receive FIFO Level mask */
119119 
120
-#define QUARK_X1000_SSCR1_TFT	(0x1F << 6)	/* Transmit FIFO Threshold (mask) */
120
+#define QUARK_X1000_SSCR1_TFT	GENMASK(10, 6)	/* Transmit FIFO Threshold (mask) */
121121 #define QUARK_X1000_SSCR1_TxTresh(x) (((x) - 1) << 6)	/* level [1..32] */
122
-#define QUARK_X1000_SSCR1_RFT	(0x1F << 11)	/* Receive FIFO Threshold (mask) */
122
+#define QUARK_X1000_SSCR1_RFT	GENMASK(15, 11)	/* Receive FIFO Threshold (mask) */
123123 #define QUARK_X1000_SSCR1_RxTresh(x) (((x) - 1) << 11)	/* level [1..32] */
124
-#define QUARK_X1000_SSCR1_STRF	(1 << 17)	/* Select FIFO or EFWR */
125
-#define QUARK_X1000_SSCR1_EFWR	(1 << 16)	/* Enable FIFO Write/Read */
124
+#define QUARK_X1000_SSCR1_EFWR	BIT(16)		/* Enable FIFO Write/Read */
125
+#define QUARK_X1000_SSCR1_STRF	BIT(17)		/* Select FIFO or EFWR */
126126 
127127 /* extra bits in PXA255, PXA26x and PXA27x SSP ports */
128128 #define SSCR0_TISSP		(1 << 4)	/* TI Sync Serial Protocol */
129129 #define SSCR0_PSP		(3 << 4)	/* PSP - Programmable Serial Protocol */
130
-#define SSCR1_TTELP		(1 << 31)	/* TXD Tristate Enable Last Phase */
131
-#define SSCR1_TTE		(1 << 30)	/* TXD Tristate Enable */
132
-#define SSCR1_EBCEI		(1 << 29)	/* Enable Bit Count Error interrupt */
133
-#define SSCR1_SCFR		(1 << 28)	/* Slave Clock free Running */
134
-#define SSCR1_ECRA		(1 << 27)	/* Enable Clock Request A */
135
-#define SSCR1_ECRB		(1 << 26)	/* Enable Clock request B */
136
-#define SSCR1_SCLKDIR		(1 << 25)	/* Serial Bit Rate Clock Direction */
137
-#define SSCR1_SFRMDIR		(1 << 24)	/* Frame Direction */
138
-#define SSCR1_RWOT		(1 << 23)	/* Receive Without Transmit */
139
-#define SSCR1_TRAIL		(1 << 22)	/* Trailing Byte */
140
-#define SSCR1_TSRE		(1 << 21)	/* Transmit Service Request Enable */
141
-#define SSCR1_RSRE		(1 << 20)	/* Receive Service Request Enable */
142
-#define SSCR1_TINTE		(1 << 19)	/* Receiver Time-out Interrupt enable */
143
-#define SSCR1_PINTE		(1 << 18)	/* Peripheral Trailing Byte Interrupt Enable */
144
-#define SSCR1_IFS		(1 << 16)	/* Invert Frame Signal */
145
-#define SSCR1_STRF		(1 << 15)	/* Select FIFO or EFWR */
146
-#define SSCR1_EFWR		(1 << 14)	/* Enable FIFO Write/Read */
147130 
148
-#define SSSR_BCE		(1 << 23)	/* Bit Count Error */
149
-#define SSSR_CSS		(1 << 22)	/* Clock Synchronisation Status */
150
-#define SSSR_TUR		(1 << 21)	/* Transmit FIFO Under Run */
151
-#define SSSR_EOC		(1 << 20)	/* End Of Chain */
152
-#define SSSR_TINT		(1 << 19)	/* Receiver Time-out Interrupt */
153
-#define SSSR_PINT		(1 << 18)	/* Peripheral Trailing Byte Interrupt */
131
+#define SSCR1_EFWR		BIT(14)		/* Enable FIFO Write/Read */
132
+#define SSCR1_STRF		BIT(15)		/* Select FIFO or EFWR */
133
+#define SSCR1_IFS		BIT(16)		/* Invert Frame Signal */
134
+#define SSCR1_PINTE		BIT(18)		/* Peripheral Trailing Byte Interrupt Enable */
135
+#define SSCR1_TINTE		BIT(19)		/* Receiver Time-out Interrupt enable */
136
+#define SSCR1_RSRE		BIT(20)		/* Receive Service Request Enable */
137
+#define SSCR1_TSRE		BIT(21)		/* Transmit Service Request Enable */
138
+#define SSCR1_TRAIL		BIT(22)		/* Trailing Byte */
139
+#define SSCR1_RWOT		BIT(23)		/* Receive Without Transmit */
140
+#define SSCR1_SFRMDIR		BIT(24)		/* Frame Direction */
141
+#define SSCR1_SCLKDIR		BIT(25)		/* Serial Bit Rate Clock Direction */
142
+#define SSCR1_ECRB		BIT(26)		/* Enable Clock request B */
143
+#define SSCR1_ECRA		BIT(27)		/* Enable Clock Request A */
144
+#define SSCR1_SCFR		BIT(28)		/* Slave Clock free Running */
145
+#define SSCR1_EBCEI		BIT(29)		/* Enable Bit Count Error interrupt */
146
+#define SSCR1_TTE		BIT(30)		/* TXD Tristate Enable */
147
+#define SSCR1_TTELP		BIT(31)		/* TXD Tristate Enable Last Phase */
154148 
149
+#define SSSR_PINT		BIT(18)		/* Peripheral Trailing Byte Interrupt */
150
+#define SSSR_TINT		BIT(19)		/* Receiver Time-out Interrupt */
151
+#define SSSR_EOC		BIT(20)		/* End Of Chain */
152
+#define SSSR_TUR		BIT(21)		/* Transmit FIFO Under Run */
153
+#define SSSR_CSS		BIT(22)		/* Clock Synchronisation Status */
154
+#define SSSR_BCE		BIT(23)		/* Bit Count Error */
155155 
156156 #define SSPSP_SCMODE(x)		((x) << 0)	/* Serial Bit Rate Clock Mode */
157
-#define SSPSP_SFRMP		(1 << 2)	/* Serial Frame Polarity */
158
-#define SSPSP_ETDS		(1 << 3)	/* End of Transfer data State */
157
+#define SSPSP_SFRMP		BIT(2)		/* Serial Frame Polarity */
158
+#define SSPSP_ETDS		BIT(3)		/* End of Transfer data State */
159159 #define SSPSP_STRTDLY(x)	((x) << 4)	/* Start Delay */
160160 #define SSPSP_DMYSTRT(x)	((x) << 7)	/* Dummy Start */
161161 #define SSPSP_SFRMDLY(x)	((x) << 9)	/* Serial Frame Delay */
162162 #define SSPSP_SFRMWDTH(x)	((x) << 16)	/* Serial Frame Width */
163163 #define SSPSP_DMYSTOP(x)	((x) << 23)	/* Dummy Stop */
164
-#define SSPSP_FSRT		(1 << 25)	/* Frame Sync Relative Timing */
164
+#define SSPSP_FSRT		BIT(25)		/* Frame Sync Relative Timing */
165165 
166166 /* PXA3xx */
167167 #define SSPSP_EDMYSTRT(x)	((x) << 26)     /* Extended Dummy Start */
168168 #define SSPSP_EDMYSTOP(x)	((x) << 28)     /* Extended Dummy Stop */
169169 #define SSPSP_TIMING_MASK	(0x7f8001f0)
170170 
171
-#define SSACD_SCDB		(1 << 3)	/* SSPSYSCLK Divider Bypass */
172
-#define SSACD_ACPS(x)		((x) << 4)	/* Audio clock PLL select */
173171 #define SSACD_ACDS(x)		((x) << 0)	/* Audio clock divider select */
174172 #define SSACD_ACDS_1		(0)
175173 #define SSACD_ACDS_2		(1)
....@@ -177,17 +175,23 @@
177175 #define SSACD_ACDS_8		(3)
178176 #define SSACD_ACDS_16		(4)
179177 #define SSACD_ACDS_32		(5)
178
+#define SSACD_SCDB		BIT(3)		/* SSPSYSCLK Divider Bypass */
180179 #define SSACD_SCDB_4X		(0)
181180 #define SSACD_SCDB_1X		(1)
182
-#define SSACD_SCDX8		(1 << 7)	/* SYSCLK division ratio select */
181
+#define SSACD_ACPS(x)		((x) << 4)	/* Audio clock PLL select */
182
+#define SSACD_SCDX8		BIT(7)		/* SYSCLK division ratio select */
183183 
184184 /* LPSS SSP */
185185 #define SSITF			0x44		/* TX FIFO trigger level */
186
+#define SSITF_TxHiThresh(x)	(((x) - 1) << 0)
186187 #define SSITF_TxLoThresh(x)	(((x) - 1) << 8)
187
-#define SSITF_TxHiThresh(x)	((x) - 1)
188188 
189189 #define SSIRF			0x48		/* RX FIFO trigger level */
190190 #define SSIRF_RxThresh(x)	((x) - 1)
191
+
192
+/* LPT/WPT SSP */
193
+#define SSCR2		(0x40)	/* SSP Command / Status 2 */
194
+#define SSPSP2		(0x44)	/* SSP Programmable Serial Protocol 2 */
191195 
192196 enum pxa_ssp_type {
193197 	SSP_UNDEFINED = 0,
....@@ -196,6 +200,7 @@
196200 	PXA27x_SSP,
197201 	PXA3xx_SSP,
198202 	PXA168_SSP,
203
+	MMP2_SSP,
199204 	PXA910_SSP,
200205 	CE4100_SSP,
201206 	QUARK_X1000_SSP,
....@@ -208,7 +213,7 @@
208213 };
209214 
210215 struct ssp_device {
211
-	struct platform_device *pdev;
216
+	struct device	*dev;
212217 	struct list_head	node;
213218 
214219 	struct clk	*clk;
....@@ -217,7 +222,7 @@
217222 
218223 	const char	*label;
219224 	int		port_id;
220
-	int		type;
225
+	enum pxa_ssp_type type;
221226 	int		use_count;
222227 	int		irq;
223228