mk-rootfs.sh

hc

2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376

 kernel/drivers/watchdog/renesas_wdt.c
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@@ -1,15 +1,13 @@
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+// SPDX-License-Identifier: GPL-2.0
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 /*
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  * Watchdog driver for Renesas WDT watchdog
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  *
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  * Copyright (C) 2015-17 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
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  * Copyright (C) 2015-17 Renesas Electronics Corporation
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms of the GNU General Public License version 2 as published by
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- * the Free Software Foundation.
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  */
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 #include <linux/bitops.h>
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 #include <linux/clk.h>
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+#include <linux/delay.h>
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 #include <linux/io.h>
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 #include <linux/kernel.h>
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 #include <linux/module.h>
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@@ -51,7 +49,6 @@
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 	void __iomem *base;
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 	struct watchdog_device wdev;
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 	unsigned long clk_rate;
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-	u16 time_left;
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 	u8 cks;
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 };
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54
 
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@@ -74,6 +71,15 @@
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 	return 0;
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 }
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+static void rwdt_wait_cycles(struct rwdt_priv *priv, unsigned int cycles)
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+{
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+	unsigned int delay;
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+
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+	delay = DIV_ROUND_UP(cycles * 1000000, priv->clk_rate);
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+
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+	usleep_range(delay, 2 * delay);
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+}
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+
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 static int rwdt_start(struct watchdog_device *wdev)
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 {
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 	struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
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@@ -84,6 +90,8 @@
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 	/* Stop the timer before we modify any register */
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 	val = readb_relaxed(priv->base + RWTCSRA) & ~RWTCSRA_TME;
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 	rwdt_write(priv, val, RWTCSRA);
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+	/* Delay 2 cycles before setting watchdog counter */
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+	rwdt_wait_cycles(priv, 2);
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 	rwdt_init_timeout(wdev);
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 	rwdt_write(priv, priv->cks, RWTCSRA);
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@@ -102,6 +110,8 @@
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 	struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
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 	rwdt_write(priv, priv->cks, RWTCSRA);
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+	/* Delay 3 cycles before disabling module clock */
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+	rwdt_wait_cycles(priv, 3);
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 	pm_runtime_put(wdev->parent);
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 	return 0;
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@@ -155,7 +165,6 @@
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 		.data = (void *)1,	/* needs single CPU */
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 	}, {
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 		.soc_id = "r8a7792",
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-		.revision = "*",
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 		.data = (void *)0,	/* needs SMP disabled */
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 	},
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 	{ /* sentinel */ }
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@@ -180,34 +189,34 @@
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189
 
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 static int rwdt_probe(struct platform_device *pdev)
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 {
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+	struct device *dev = &pdev->dev;
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 	struct rwdt_priv *priv;
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-	struct resource *res;
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 	struct clk *clk;
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 	unsigned long clks_per_sec;
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 	int ret, i;
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+	u8 csra;
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198
 
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-	if (rwdt_blacklisted(&pdev->dev))
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+	if (rwdt_blacklisted(dev))
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 		return -ENODEV;
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201
 
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-	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
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+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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 	if (!priv)
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 		return -ENOMEM;
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-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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-	priv->base = devm_ioremap_resource(&pdev->dev, res);
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+	priv->base = devm_platform_ioremap_resource(pdev, 0);
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 	if (IS_ERR(priv->base))
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 		return PTR_ERR(priv->base);
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-	clk = devm_clk_get(&pdev->dev, NULL);
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+	clk = devm_clk_get(dev, NULL);
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 	if (IS_ERR(clk))
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 		return PTR_ERR(clk);
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-	pm_runtime_enable(&pdev->dev);
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-	pm_runtime_get_sync(&pdev->dev);
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+	pm_runtime_enable(dev);
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+	pm_runtime_get_sync(dev);
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 	priv->clk_rate = clk_get_rate(clk);
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-	priv->wdev.bootstatus = (readb_relaxed(priv->base + RWTCSRA) &
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-				RWTCSRA_WOVF) ? WDIOF_CARDRESET : 0;
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-	pm_runtime_put(&pdev->dev);
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+	csra = readb_relaxed(priv->base + RWTCSRA);
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+	priv->wdev.bootstatus = csra & RWTCSRA_WOVF ? WDIOF_CARDRESET : 0;
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+	pm_runtime_put(dev);
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220
 
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 	if (!priv->clk_rate) {
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 		ret = -ENOENT;
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@@ -223,14 +232,14 @@
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 	}
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 	if (i < 0) {
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-		dev_err(&pdev->dev, "Can't find suitable clock divider\n");
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+		dev_err(dev, "Can't find suitable clock divider\n");
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 		ret = -ERANGE;
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 		goto out_pm_disable;
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 	}
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-	priv->wdev.info = &rwdt_ident,
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-	priv->wdev.ops = &rwdt_ops,
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-	priv->wdev.parent = &pdev->dev;
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+	priv->wdev.info = &rwdt_ident;
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+	priv->wdev.ops = &rwdt_ops;
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+	priv->wdev.parent = dev;
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 	priv->wdev.min_timeout = 1;
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 	priv->wdev.max_timeout = DIV_BY_CLKS_PER_SEC(priv, 65536);
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 	priv->wdev.timeout = min(priv->wdev.max_timeout, RWDT_DEFAULT_TIMEOUT);
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@@ -242,9 +251,14 @@
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 	watchdog_stop_on_unregister(&priv->wdev);
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 	/* This overrides the default timeout only if DT configuration was found */
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-	ret = watchdog_init_timeout(&priv->wdev, 0, &pdev->dev);
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-	if (ret)
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-		dev_warn(&pdev->dev, "Specified timeout value invalid, using default\n");
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+	watchdog_init_timeout(&priv->wdev, 0, dev);
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+
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+	/* Check if FW enabled the watchdog */
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+	if (csra & RWTCSRA_TME) {
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+		/* Ensure properly initialized dividers */
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+		rwdt_start(&priv->wdev);
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+		set_bit(WDOG_HW_RUNNING, &priv->wdev.status);
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+	}
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 	ret = watchdog_register_device(&priv->wdev);
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 	if (ret < 0)
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@@ -253,7 +267,7 @@
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 	return 0;
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  out_pm_disable:
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-	pm_runtime_disable(&pdev->dev);
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+	pm_runtime_disable(dev);
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 	return ret;
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 }
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@@ -271,10 +285,9 @@
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 {
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 	struct rwdt_priv *priv = dev_get_drvdata(dev);
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-	if (watchdog_active(&priv->wdev)) {
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-		priv->time_left = readw(priv->base + RWTCNT);
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+	if (watchdog_active(&priv->wdev))
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 		rwdt_stop(&priv->wdev);
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-	}
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+
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 	return 0;
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 }
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@@ -282,10 +295,9 @@
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 {
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 	struct rwdt_priv *priv = dev_get_drvdata(dev);
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-	if (watchdog_active(&priv->wdev)) {
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+	if (watchdog_active(&priv->wdev))
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 		rwdt_start(&priv->wdev);
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-		rwdt_write(priv, priv->time_left, RWTCNT);
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-	}
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+
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 	return 0;
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 }
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