forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376 
 kernel/drivers/w1/masters/omap_hdq.c
....@@ -38,12 +38,6 @@
3838 #define OMAP_HDQ_INT_STATUS_TXCOMPLETE		BIT(2)
3939 #define OMAP_HDQ_INT_STATUS_RXCOMPLETE		BIT(1)
4040 #define OMAP_HDQ_INT_STATUS_TIMEOUT		BIT(0)
41
-#define OMAP_HDQ_SYSCONFIG			0x14
42
-#define OMAP_HDQ_SYSCONFIG_SOFTRESET		BIT(1)
43
-#define OMAP_HDQ_SYSCONFIG_AUTOIDLE		BIT(0)
44
-#define OMAP_HDQ_SYSCONFIG_NOIDLE		0x0
45
-#define OMAP_HDQ_SYSSTATUS			0x18
46
-#define OMAP_HDQ_SYSSTATUS_RESETDONE		BIT(0)
4741 
4842 #define OMAP_HDQ_FLAG_CLEAR			0
4943 #define OMAP_HDQ_FLAG_SET			1
....@@ -60,19 +54,11 @@
6054 struct hdq_data {
6155 	struct device		*dev;
6256 	void __iomem		*hdq_base;
63
-	/* lock status update */
57
+	/* lock read/write/break operations */
6458 	struct  mutex		hdq_mutex;
65
-	int			hdq_usecount;
59
+	/* interrupt status and a lock for it */
6660 	u8			hdq_irqstatus;
67
-	/* device lock */
6861 	spinlock_t		hdq_spinlock;
69
-	/*
70
-	 * Used to control the call to omap_hdq_get and omap_hdq_put.
71
-	 * HDQ Protocol: Write the CMD|REG_address first, followed by
72
-	 * the data wrire or read.
73
-	 */
74
-	int			init_trans;
75
-	int                     rrw;
7662 	/* mode: 0-HDQ 1-W1 */
7763 	int                     mode;
7864 
....@@ -97,15 +83,6 @@
9783 	__raw_writel(new_val, hdq_data->hdq_base + offset);
9884 
9985 	return new_val;
100
-}
101
-
102
-static void hdq_disable_interrupt(struct hdq_data *hdq_data, u32 offset,
103
-				  u32 mask)
104
-{
105
-	u32 ie;
106
-
107
-	ie = readl(hdq_data->hdq_base + offset);
108
-	writel(ie & mask, hdq_data->hdq_base + offset);
10986 }
11087 
11188 /*
....@@ -142,21 +119,38 @@
142119 	return ret;
143120 }
144121 
122
+/* Clear saved irqstatus after using an interrupt */
123
+static u8 hdq_reset_irqstatus(struct hdq_data *hdq_data, u8 bits)
124
+{
125
+	unsigned long irqflags;
126
+	u8 status;
127
+
128
+	spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
129
+	status = hdq_data->hdq_irqstatus;
130
+	/* this is a read-modify-write */
131
+	hdq_data->hdq_irqstatus &= ~bits;
132
+	spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
133
+
134
+	return status;
135
+}
136
+
145137 /* write out a byte and fill *status with HDQ_INT_STATUS */
146138 static int hdq_write_byte(struct hdq_data *hdq_data, u8 val, u8 *status)
147139 {
148140 	int ret;
149141 	u8 tmp_status;
150
-	unsigned long irqflags;
142
+
143
+	ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
144
+	if (ret < 0) {
145
+		ret = -EINTR;
146
+		goto rtn;
147
+	}
148
+
149
+	if (hdq_data->hdq_irqstatus)
150
+		dev_err(hdq_data->dev, "TX irqstatus not cleared (%02x)\n",
151
+			hdq_data->hdq_irqstatus);
151152 
152153 	*status = 0;
153
-
154
-	spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
155
-	/* clear interrupt flags via a dummy read */
156
-	hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
157
-	/* ISR loads it with new INT_STATUS */
158
-	hdq_data->hdq_irqstatus = 0;
159
-	spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
160154 
161155 	hdq_reg_out(hdq_data, OMAP_HDQ_TX_DATA, val);
162156 
....@@ -165,14 +159,15 @@
165159 		OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO);
166160 	/* wait for the TXCOMPLETE bit */
167161 	ret = wait_event_timeout(hdq_wait_queue,
168
-		hdq_data->hdq_irqstatus, OMAP_HDQ_TIMEOUT);
162
+		(hdq_data->hdq_irqstatus & OMAP_HDQ_INT_STATUS_TXCOMPLETE),
163
+		OMAP_HDQ_TIMEOUT);
164
+	*status = hdq_reset_irqstatus(hdq_data, OMAP_HDQ_INT_STATUS_TXCOMPLETE);
169165 	if (ret == 0) {
170166 		dev_dbg(hdq_data->dev, "TX wait elapsed\n");
171167 		ret = -ETIMEDOUT;
172168 		goto out;
173169 	}
174170 
175
-	*status = hdq_data->hdq_irqstatus;
176171 	/* check irqstatus */
177172 	if (!(*status & OMAP_HDQ_INT_STATUS_TXCOMPLETE)) {
178173 		dev_dbg(hdq_data->dev, "timeout waiting for"
....@@ -191,6 +186,8 @@
191186 	}
192187 
193188 out:
189
+	mutex_unlock(&hdq_data->hdq_mutex);
190
+rtn:
194191 	return ret;
195192 }
196193 
....@@ -201,7 +198,7 @@
201198 	unsigned long irqflags;
202199 
203200 	spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
204
-	hdq_data->hdq_irqstatus = hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
201
+	hdq_data->hdq_irqstatus |= hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
205202 	spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
206203 	dev_dbg(hdq_data->dev, "hdq_isr: %x\n", hdq_data->hdq_irqstatus);
207204 
....@@ -237,47 +234,11 @@
237234 	slave_found(master_dev, id);
238235 }
239236 
240
-static int _omap_hdq_reset(struct hdq_data *hdq_data)
241
-{
242
-	int ret;
243
-	u8 tmp_status;
244
-
245
-	hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG,
246
-		    OMAP_HDQ_SYSCONFIG_SOFTRESET);
247
-	/*
248
-	 * Select HDQ/1W mode & enable clocks.
249
-	 * It is observed that INT flags can't be cleared via a read and GO/INIT
250
-	 * won't return to zero if interrupt is disabled. So we always enable
251
-	 * interrupt.
252
-	 */
253
-	hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
254
-		OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
255
-		OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
256
-
257
-	/* wait for reset to complete */
258
-	ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_SYSSTATUS,
259
-		OMAP_HDQ_SYSSTATUS_RESETDONE, OMAP_HDQ_FLAG_SET, &tmp_status);
260
-	if (ret)
261
-		dev_dbg(hdq_data->dev, "timeout waiting HDQ reset, %x",
262
-				tmp_status);
263
-	else {
264
-		hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
265
-			OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
266
-			OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK |
267
-			hdq_data->mode);
268
-		hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG,
269
-			OMAP_HDQ_SYSCONFIG_AUTOIDLE);
270
-	}
271
-
272
-	return ret;
273
-}
274
-
275237 /* Issue break pulse to the device */
276238 static int omap_hdq_break(struct hdq_data *hdq_data)
277239 {
278240 	int ret = 0;
279241 	u8 tmp_status;
280
-	unsigned long irqflags;
281242 
282243 	ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
283244 	if (ret < 0) {
....@@ -286,12 +247,9 @@
286247 		goto rtn;
287248 	}
288249 
289
-	spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
290
-	/* clear interrupt flags via a dummy read */
291
-	hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
292
-	/* ISR loads it with new INT_STATUS */
293
-	hdq_data->hdq_irqstatus = 0;
294
-	spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
250
+	if (hdq_data->hdq_irqstatus)
251
+		dev_err(hdq_data->dev, "break irqstatus not cleared (%02x)\n",
252
+			hdq_data->hdq_irqstatus);
295253 
296254 	/* set the INIT and GO bit */
297255 	hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS,
....@@ -301,18 +259,19 @@
301259 
302260 	/* wait for the TIMEOUT bit */
303261 	ret = wait_event_timeout(hdq_wait_queue,
304
-		hdq_data->hdq_irqstatus, OMAP_HDQ_TIMEOUT);
262
+		(hdq_data->hdq_irqstatus & OMAP_HDQ_INT_STATUS_TIMEOUT),
263
+		OMAP_HDQ_TIMEOUT);
264
+	tmp_status = hdq_reset_irqstatus(hdq_data, OMAP_HDQ_INT_STATUS_TIMEOUT);
305265 	if (ret == 0) {
306266 		dev_dbg(hdq_data->dev, "break wait elapsed\n");
307267 		ret = -EINTR;
308268 		goto out;
309269 	}
310270 
311
-	tmp_status = hdq_data->hdq_irqstatus;
312271 	/* check irqstatus */
313272 	if (!(tmp_status & OMAP_HDQ_INT_STATUS_TIMEOUT)) {
314273 		dev_dbg(hdq_data->dev, "timeout waiting for TIMEOUT, %x\n",
315
-				tmp_status);
274
+			tmp_status);
316275 		ret = -ETIMEDOUT;
317276 		goto out;
318277 	}
....@@ -357,7 +316,7 @@
357316 		goto rtn;
358317 	}
359318 
360
-	if (!hdq_data->hdq_usecount) {
319
+	if (pm_runtime_suspended(hdq_data->dev)) {
361320 		ret = -EINVAL;
362321 		goto out;
363322 	}
....@@ -371,12 +330,15 @@
371330 		 */
372331 		wait_event_timeout(hdq_wait_queue,
373332 				   (hdq_data->hdq_irqstatus
374
-				    & OMAP_HDQ_INT_STATUS_RXCOMPLETE),
333
+				    & (OMAP_HDQ_INT_STATUS_RXCOMPLETE |
334
+				       OMAP_HDQ_INT_STATUS_TIMEOUT)),
375335 				   OMAP_HDQ_TIMEOUT);
376
-
336
+		status = hdq_reset_irqstatus(hdq_data,
337
+					     OMAP_HDQ_INT_STATUS_RXCOMPLETE |
338
+					     OMAP_HDQ_INT_STATUS_TIMEOUT);
377339 		hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, 0,
378340 			OMAP_HDQ_CTRL_STATUS_DIR);
379
-		status = hdq_data->hdq_irqstatus;
341
+
380342 		/* check irqstatus */
381343 		if (!(status & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) {
382344 			dev_dbg(hdq_data->dev, "timeout waiting for"
....@@ -384,6 +346,8 @@
384346 			ret = -ETIMEDOUT;
385347 			goto out;
386348 		}
349
+	} else { /* interrupt had occurred before hdq_read_byte was called */
350
+		hdq_reset_irqstatus(hdq_data, OMAP_HDQ_INT_STATUS_RXCOMPLETE);
387351 	}
388352 	/* the data is ready. Read it in! */
389353 	*val = hdq_reg_in(hdq_data, OMAP_HDQ_RX_DATA);
....@@ -392,80 +356,6 @@
392356 rtn:
393357 	return ret;
394358 
395
-}
396
-
397
-/* Enable clocks and set the controller to HDQ/1W mode */
398
-static int omap_hdq_get(struct hdq_data *hdq_data)
399
-{
400
-	int ret = 0;
401
-
402
-	ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
403
-	if (ret < 0) {
404
-		ret = -EINTR;
405
-		goto rtn;
406
-	}
407
-
408
-	if (OMAP_HDQ_MAX_USER == hdq_data->hdq_usecount) {
409
-		dev_dbg(hdq_data->dev, "attempt to exceed the max use count");
410
-		ret = -EINVAL;
411
-		goto out;
412
-	} else {
413
-		hdq_data->hdq_usecount++;
414
-		try_module_get(THIS_MODULE);
415
-		if (1 == hdq_data->hdq_usecount) {
416
-
417
-			pm_runtime_get_sync(hdq_data->dev);
418
-
419
-			/* make sure HDQ/1W is out of reset */
420
-			if (!(hdq_reg_in(hdq_data, OMAP_HDQ_SYSSTATUS) &
421
-				OMAP_HDQ_SYSSTATUS_RESETDONE)) {
422
-				ret = _omap_hdq_reset(hdq_data);
423
-				if (ret)
424
-					/* back up the count */
425
-					hdq_data->hdq_usecount--;
426
-			} else {
427
-				/* select HDQ/1W mode & enable clocks */
428
-				hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
429
-					OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
430
-					OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK |
431
-					hdq_data->mode);
432
-				hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG,
433
-					OMAP_HDQ_SYSCONFIG_NOIDLE);
434
-				hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
435
-			}
436
-		}
437
-	}
438
-
439
-out:
440
-	mutex_unlock(&hdq_data->hdq_mutex);
441
-rtn:
442
-	return ret;
443
-}
444
-
445
-/* Disable clocks to the module */
446
-static int omap_hdq_put(struct hdq_data *hdq_data)
447
-{
448
-	int ret = 0;
449
-
450
-	ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
451
-	if (ret < 0)
452
-		return -EINTR;
453
-
454
-	hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG,
455
-		    OMAP_HDQ_SYSCONFIG_AUTOIDLE);
456
-	if (0 == hdq_data->hdq_usecount) {
457
-		dev_dbg(hdq_data->dev, "attempt to decrement use count"
458
-			" when it is zero");
459
-		ret = -EINVAL;
460
-	} else {
461
-		hdq_data->hdq_usecount--;
462
-		module_put(THIS_MODULE);
463
-		if (0 == hdq_data->hdq_usecount)
464
-			pm_runtime_put_sync(hdq_data->dev);
465
-	}
466
-	mutex_unlock(&hdq_data->hdq_mutex);
467
-
468
-	return ret;
469359 }
470360 
471361 /*
....@@ -482,7 +372,12 @@
482372 		  OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK;
483373 	u8 mask = ctrl | OMAP_HDQ_CTRL_STATUS_DIR;
484374 
485
-	omap_hdq_get(_hdq);
375
+	err = pm_runtime_get_sync(hdq_data->dev);
376
+	if (err < 0) {
377
+		pm_runtime_put_noidle(hdq_data->dev);
378
+
379
+		return err;
380
+	}
486381 
487382 	err = mutex_lock_interruptible(&hdq_data->hdq_mutex);
488383 	if (err < 0) {
....@@ -490,7 +385,6 @@
490385 		goto rtn;
491386 	}
492387 
493
-	hdq_data->hdq_irqstatus = 0;
494388 	/* read id_bit */
495389 	hdq_reg_merge(_hdq, OMAP_HDQ_CTRL_STATUS,
496390 		      ctrl | OMAP_HDQ_CTRL_STATUS_DIR, mask);
....@@ -498,13 +392,15 @@
498392 				 (hdq_data->hdq_irqstatus
499393 				  & OMAP_HDQ_INT_STATUS_RXCOMPLETE),
500394 				 OMAP_HDQ_TIMEOUT);
395
+	/* Must clear irqstatus for another RXCOMPLETE interrupt */
396
+	hdq_reset_irqstatus(hdq_data, OMAP_HDQ_INT_STATUS_RXCOMPLETE);
397
+
501398 	if (err == 0) {
502399 		dev_dbg(hdq_data->dev, "RX wait elapsed\n");
503400 		goto out;
504401 	}
505402 	id_bit = (hdq_reg_in(_hdq, OMAP_HDQ_RX_DATA) & 0x01);
506403 
507
-	hdq_data->hdq_irqstatus = 0;
508404 	/* read comp_bit */
509405 	hdq_reg_merge(_hdq, OMAP_HDQ_CTRL_STATUS,
510406 		      ctrl | OMAP_HDQ_CTRL_STATUS_DIR, mask);
....@@ -512,6 +408,9 @@
512408 				 (hdq_data->hdq_irqstatus
513409 				  & OMAP_HDQ_INT_STATUS_RXCOMPLETE),
514410 				 OMAP_HDQ_TIMEOUT);
411
+	/* Must clear irqstatus for another RXCOMPLETE interrupt */
412
+	hdq_reset_irqstatus(hdq_data, OMAP_HDQ_INT_STATUS_RXCOMPLETE);
413
+
515414 	if (err == 0) {
516415 		dev_dbg(hdq_data->dev, "RX wait elapsed\n");
517416 		goto out;
....@@ -538,6 +437,9 @@
538437 				 (hdq_data->hdq_irqstatus
539438 				  & OMAP_HDQ_INT_STATUS_TXCOMPLETE),
540439 				 OMAP_HDQ_TIMEOUT);
440
+	/* Must clear irqstatus for another TXCOMPLETE interrupt */
441
+	hdq_reset_irqstatus(hdq_data, OMAP_HDQ_INT_STATUS_TXCOMPLETE);
442
+
541443 	if (err == 0) {
542444 		dev_dbg(hdq_data->dev, "TX wait elapsed\n");
543445 		goto out;
....@@ -549,16 +451,30 @@
549451 out:
550452 	mutex_unlock(&hdq_data->hdq_mutex);
551453 rtn:
552
-	omap_hdq_put(_hdq);
454
+	pm_runtime_mark_last_busy(hdq_data->dev);
455
+	pm_runtime_put_autosuspend(hdq_data->dev);
456
+
553457 	return ret;
554458 }
555459 
556460 /* reset callback */
557461 static u8 omap_w1_reset_bus(void *_hdq)
558462 {
559
-	omap_hdq_get(_hdq);
560
-	omap_hdq_break(_hdq);
561
-	omap_hdq_put(_hdq);
463
+	struct hdq_data *hdq_data = _hdq;
464
+	int err;
465
+
466
+	err = pm_runtime_get_sync(hdq_data->dev);
467
+	if (err < 0) {
468
+		pm_runtime_put_noidle(hdq_data->dev);
469
+
470
+		return err;
471
+	}
472
+
473
+	omap_hdq_break(hdq_data);
474
+
475
+	pm_runtime_mark_last_busy(hdq_data->dev);
476
+	pm_runtime_put_autosuspend(hdq_data->dev);
477
+
562478 	return 0;
563479 }
564480 
....@@ -569,37 +485,19 @@
569485 	u8 val = 0;
570486 	int ret;
571487 
572
-	/* First write to initialize the transfer */
573
-	if (hdq_data->init_trans == 0)
574
-		omap_hdq_get(hdq_data);
488
+	ret = pm_runtime_get_sync(hdq_data->dev);
489
+	if (ret < 0) {
490
+		pm_runtime_put_noidle(hdq_data->dev);
575491 
576
-	ret = hdq_read_byte(hdq_data, &val);
577
-	if (ret) {
578
-		ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
579
-		if (ret < 0) {
580
-			dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
581
-			return -EINTR;
582
-		}
583
-		hdq_data->init_trans = 0;
584
-		mutex_unlock(&hdq_data->hdq_mutex);
585
-		omap_hdq_put(hdq_data);
586492 		return -1;
587493 	}
588494 
589
-	hdq_disable_interrupt(hdq_data, OMAP_HDQ_CTRL_STATUS,
590
-			      ~OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
495
+	ret = hdq_read_byte(hdq_data, &val);
496
+	if (ret)
497
+		val = -1;
591498 
592
-	/* Write followed by a read, release the module */
593
-	if (hdq_data->init_trans) {
594
-		ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
595
-		if (ret < 0) {
596
-			dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
597
-			return -EINTR;
598
-		}
599
-		hdq_data->init_trans = 0;
600
-		mutex_unlock(&hdq_data->hdq_mutex);
601
-		omap_hdq_put(hdq_data);
602
-	}
499
+	pm_runtime_mark_last_busy(hdq_data->dev);
500
+	pm_runtime_put_autosuspend(hdq_data->dev);
603501 
604502 	return val;
605503 }
....@@ -611,9 +509,12 @@
611509 	int ret;
612510 	u8 status;
613511 
614
-	/* First write to initialize the transfer */
615
-	if (hdq_data->init_trans == 0)
616
-		omap_hdq_get(hdq_data);
512
+	ret = pm_runtime_get_sync(hdq_data->dev);
513
+	if (ret < 0) {
514
+		pm_runtime_put_noidle(hdq_data->dev);
515
+
516
+		return;
517
+	}
617518 
618519 	/*
619520 	 * We need to reset the slave before
....@@ -623,31 +524,15 @@
623524 	if (byte == W1_SKIP_ROM)
624525 		omap_hdq_break(hdq_data);
625526 
626
-	ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
627
-	if (ret < 0) {
628
-		dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
629
-		return;
630
-	}
631
-	hdq_data->init_trans++;
632
-	mutex_unlock(&hdq_data->hdq_mutex);
633
-
634527 	ret = hdq_write_byte(hdq_data, byte, &status);
635528 	if (ret < 0) {
636529 		dev_dbg(hdq_data->dev, "TX failure:Ctrl status %x\n", status);
637
-		return;
530
+		goto out_err;
638531 	}
639532 
640
-	/* Second write, data transferred. Release the module */
641
-	if (hdq_data->init_trans > 1) {
642
-		omap_hdq_put(hdq_data);
643
-		ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
644
-		if (ret < 0) {
645
-			dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
646
-			return;
647
-		}
648
-		hdq_data->init_trans = 0;
649
-		mutex_unlock(&hdq_data->hdq_mutex);
650
-	}
533
+out_err:
534
+	pm_runtime_mark_last_busy(hdq_data->dev);
535
+	pm_runtime_put_autosuspend(hdq_data->dev);
651536 }
652537 
653538 static struct w1_bus_master omap_w1_master = {
....@@ -656,11 +541,39 @@
656541 	.reset_bus	= omap_w1_reset_bus,
657542 };
658543 
544
+static int __maybe_unused omap_hdq_runtime_suspend(struct device *dev)
545
+{
546
+	struct hdq_data *hdq_data = dev_get_drvdata(dev);
547
+
548
+	hdq_reg_out(hdq_data, 0, hdq_data->mode);
549
+	hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
550
+
551
+	return 0;
552
+}
553
+
554
+static int __maybe_unused omap_hdq_runtime_resume(struct device *dev)
555
+{
556
+	struct hdq_data *hdq_data = dev_get_drvdata(dev);
557
+
558
+	/* select HDQ/1W mode & enable clocks */
559
+	hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
560
+		    OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
561
+		    OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK |
562
+		    hdq_data->mode);
563
+	hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
564
+
565
+	return 0;
566
+}
567
+
568
+static const struct dev_pm_ops omap_hdq_pm_ops = {
569
+	SET_RUNTIME_PM_OPS(omap_hdq_runtime_suspend,
570
+			   omap_hdq_runtime_resume, NULL)
571
+};
572
+
659573 static int omap_hdq_probe(struct platform_device *pdev)
660574 {
661575 	struct device *dev = &pdev->dev;
662576 	struct hdq_data *hdq_data;
663
-	struct resource *res;
664577 	int ret, irq;
665578 	u8 rev;
666579 	const char *mode;
....@@ -674,26 +587,29 @@
674587 	hdq_data->dev = dev;
675588 	platform_set_drvdata(pdev, hdq_data);
676589 
677
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
678
-	hdq_data->hdq_base = devm_ioremap_resource(dev, res);
590
+	hdq_data->hdq_base = devm_platform_ioremap_resource(pdev, 0);
679591 	if (IS_ERR(hdq_data->hdq_base))
680592 		return PTR_ERR(hdq_data->hdq_base);
681593 
682
-	hdq_data->hdq_usecount = 0;
683
-	hdq_data->rrw = 0;
684594 	mutex_init(&hdq_data->hdq_mutex);
685595 
686
-	pm_runtime_enable(&pdev->dev);
687
-	ret = pm_runtime_get_sync(&pdev->dev);
688
-	if (ret < 0) {
689
-		dev_dbg(&pdev->dev, "pm_runtime_get_sync failed\n");
690
-		goto err_w1;
596
+	ret = of_property_read_string(pdev->dev.of_node, "ti,mode", &mode);
597
+	if (ret < 0 || !strcmp(mode, "hdq")) {
598
+		hdq_data->mode = 0;
599
+		omap_w1_master.search = omap_w1_search_bus;
600
+	} else {
601
+		hdq_data->mode = 1;
602
+		omap_w1_master.triplet = omap_w1_triplet;
691603 	}
692604 
693
-	ret = _omap_hdq_reset(hdq_data);
694
-	if (ret) {
695
-		dev_dbg(&pdev->dev, "reset failed\n");
696
-		goto err_irq;
605
+	pm_runtime_enable(&pdev->dev);
606
+	pm_runtime_use_autosuspend(&pdev->dev);
607
+	pm_runtime_set_autosuspend_delay(&pdev->dev, 300);
608
+	ret = pm_runtime_get_sync(&pdev->dev);
609
+	if (ret < 0) {
610
+		pm_runtime_put_noidle(&pdev->dev);
611
+		dev_dbg(&pdev->dev, "pm_runtime_get_sync failed\n");
612
+		goto err_w1;
697613 	}
698614 
699615 	rev = hdq_reg_in(hdq_data, OMAP_HDQ_REVISION);
....@@ -717,16 +633,8 @@
717633 
718634 	omap_hdq_break(hdq_data);
719635 
720
-	pm_runtime_put_sync(&pdev->dev);
721
-
722
-	ret = of_property_read_string(pdev->dev.of_node, "ti,mode", &mode);
723
-	if (ret < 0 || !strcmp(mode, "hdq")) {
724
-		hdq_data->mode = 0;
725
-		omap_w1_master.search = omap_w1_search_bus;
726
-	} else {
727
-		hdq_data->mode = 1;
728
-		omap_w1_master.triplet = omap_w1_triplet;
729
-	}
636
+	pm_runtime_mark_last_busy(&pdev->dev);
637
+	pm_runtime_put_autosuspend(&pdev->dev);
730638 
731639 	omap_w1_master.data = hdq_data;
732640 
....@@ -741,6 +649,7 @@
741649 err_irq:
742650 	pm_runtime_put_sync(&pdev->dev);
743651 err_w1:
652
+	pm_runtime_dont_use_autosuspend(&pdev->dev);
744653 	pm_runtime_disable(&pdev->dev);
745654 
746655 	return ret;
....@@ -748,22 +657,18 @@
748657 
749658 static int omap_hdq_remove(struct platform_device *pdev)
750659 {
751
-	struct hdq_data *hdq_data = platform_get_drvdata(pdev);
660
+	int active;
752661 
753
-	mutex_lock(&hdq_data->hdq_mutex);
754
-
755
-	if (hdq_data->hdq_usecount) {
756
-		dev_dbg(&pdev->dev, "removed when use count is not zero\n");
757
-		mutex_unlock(&hdq_data->hdq_mutex);
758
-		return -EBUSY;
759
-	}
760
-
761
-	mutex_unlock(&hdq_data->hdq_mutex);
762
-
763
-	/* remove module dependency */
764
-	pm_runtime_disable(&pdev->dev);
662
+	active = pm_runtime_get_sync(&pdev->dev);
663
+	if (active < 0)
664
+		pm_runtime_put_noidle(&pdev->dev);
765665 
766666 	w1_remove_master_device(&omap_w1_master);
667
+
668
+	pm_runtime_dont_use_autosuspend(&pdev->dev);
669
+	if (active >= 0)
670
+		pm_runtime_put_sync(&pdev->dev);
671
+	pm_runtime_disable(&pdev->dev);
767672 
768673 	return 0;
769674 }
....@@ -781,6 +686,7 @@
781686 	.driver = {
782687 		.name =	"omap_hdq",
783688 		.of_match_table = omap_hdq_dt_ids,
689
+		.pm = &omap_hdq_pm_ops,
784690 	},
785691 };
786692 module_platform_driver(omap_hdq_driver);