forked from ~ljy/RK356X_SDK_RELEASE

hc
2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376
kernel/drivers/thunderbolt/nhi_regs.h
....@@ -3,6 +3,7 @@
33 * Thunderbolt driver - NHI registers
44 *
55 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
6
+ * Copyright (C) 2018, Intel Corporation
67 */
78
89 #ifndef NHI_REGS_H_
....@@ -123,4 +124,41 @@
123124 #define REG_FW_STS_ICM_EN_INVERT BIT(1)
124125 #define REG_FW_STS_ICM_EN BIT(0)
125126
127
+/* ICL NHI VSEC registers */
128
+
129
+/* FW ready */
130
+#define VS_CAP_9 0xc8
131
+#define VS_CAP_9_FW_READY BIT(31)
132
+/* UUID */
133
+#define VS_CAP_10 0xcc
134
+#define VS_CAP_11 0xd0
135
+/* LTR */
136
+#define VS_CAP_15 0xe0
137
+#define VS_CAP_16 0xe4
138
+/* TBT2PCIe */
139
+#define VS_CAP_18 0xec
140
+#define VS_CAP_18_DONE BIT(0)
141
+/* PCIe2TBT */
142
+#define VS_CAP_19 0xf0
143
+#define VS_CAP_19_VALID BIT(0)
144
+#define VS_CAP_19_CMD_SHIFT 1
145
+#define VS_CAP_19_CMD_MASK GENMASK(7, 1)
146
+/* Force power */
147
+#define VS_CAP_22 0xfc
148
+#define VS_CAP_22_FORCE_POWER BIT(1)
149
+#define VS_CAP_22_DMA_DELAY_MASK GENMASK(31, 24)
150
+#define VS_CAP_22_DMA_DELAY_SHIFT 24
151
+
152
+/**
153
+ * enum icl_lc_mailbox_cmd - ICL specific LC mailbox commands
154
+ * @ICL_LC_GO2SX: Ask LC to enter Sx without wake
155
+ * @ICL_LC_GO2SX_NO_WAKE: Ask LC to enter Sx with wake
156
+ * @ICL_LC_PREPARE_FOR_RESET: Prepare LC for reset
157
+ */
158
+enum icl_lc_mailbox_cmd {
159
+ ICL_LC_GO2SX = 0x02,
160
+ ICL_LC_GO2SX_NO_WAKE = 0x03,
161
+ ICL_LC_PREPARE_FOR_RESET = 0x21,
162
+};
163
+
126164 #endif