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2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376 
 kernel/drivers/thermal/qoriq_thermal.c
....@@ -2,165 +2,206 @@
22 //
33 // Copyright 2016 Freescale Semiconductor, Inc.
44 
5
-#include <linux/module.h>
6
-#include <linux/platform_device.h>
5
+#include <linux/clk.h>
76 #include <linux/err.h>
87 #include <linux/io.h>
8
+#include <linux/module.h>
99 #include <linux/of.h>
10
-#include <linux/of_address.h>
10
+#include <linux/platform_device.h>
11
+#include <linux/regmap.h>
12
+#include <linux/sizes.h>
1113 #include <linux/thermal.h>
14
+#include <linux/units.h>
1215 
1316 #include "thermal_core.h"
17
+#include "thermal_hwmon.h"
1418 
15
-#define SITES_MAX	16
19
+#define SITES_MAX		16
20
+#define TMR_DISABLE		0x0
21
+#define TMR_ME			0x80000000
22
+#define TMR_ALPF		0x0c000000
23
+#define TMR_ALPF_V2		0x03000000
24
+#define TMTMIR_DEFAULT	0x0000000f
25
+#define TIER_DISABLE	0x0
26
+#define TEUMR0_V2		0x51009c00
27
+#define TMSARA_V2		0xe
28
+#define TMU_VER1		0x1
29
+#define TMU_VER2		0x2
1630 
17
-/*
18
- * QorIQ TMU Registers
19
- */
20
-struct qoriq_tmu_site_regs {
21
-	u32 tritsr;		/* Immediate Temperature Site Register */
22
-	u32 tratsr;		/* Average Temperature Site Register */
23
-	u8 res0[0x8];
24
-};
25
-
26
-struct qoriq_tmu_regs {
27
-	u32 tmr;		/* Mode Register */
31
+#define REGS_TMR	0x000	/* Mode Register */
2832 #define TMR_DISABLE	0x0
2933 #define TMR_ME		0x80000000
3034 #define TMR_ALPF	0x0c000000
31
-	u32 tsr;		/* Status Register */
32
-	u32 tmtmir;		/* Temperature measurement interval Register */
35
+#define TMR_MSITE_ALL	GENMASK(15, 0)
36
+
37
+#define REGS_TMTMIR	0x008	/* Temperature measurement interval Register */
3338 #define TMTMIR_DEFAULT	0x0000000f
34
-	u8 res0[0x14];
35
-	u32 tier;		/* Interrupt Enable Register */
39
+
40
+#define REGS_V2_TMSR	0x008	/* monitor site register */
41
+
42
+#define REGS_V2_TMTMIR	0x00c	/* Temperature measurement interval Register */
43
+
44
+#define REGS_TIER	0x020	/* Interrupt Enable Register */
3645 #define TIER_DISABLE	0x0
37
-	u32 tidr;		/* Interrupt Detect Register */
38
-	u32 tiscr;		/* Interrupt Site Capture Register */
39
-	u32 ticscr;		/* Interrupt Critical Site Capture Register */
40
-	u8 res1[0x10];
41
-	u32 tmhtcrh;		/* High Temperature Capture Register */
42
-	u32 tmhtcrl;		/* Low Temperature Capture Register */
43
-	u8 res2[0x8];
44
-	u32 tmhtitr;		/* High Temperature Immediate Threshold */
45
-	u32 tmhtatr;		/* High Temperature Average Threshold */
46
-	u32 tmhtactr;	/* High Temperature Average Crit Threshold */
47
-	u8 res3[0x24];
48
-	u32 ttcfgr;		/* Temperature Configuration Register */
49
-	u32 tscfgr;		/* Sensor Configuration Register */
50
-	u8 res4[0x78];
51
-	struct qoriq_tmu_site_regs site[SITES_MAX];
52
-	u8 res5[0x9f8];
53
-	u32 ipbrr0;		/* IP Block Revision Register 0 */
54
-	u32 ipbrr1;		/* IP Block Revision Register 1 */
55
-	u8 res6[0x310];
56
-	u32 ttr0cr;		/* Temperature Range 0 Control Register */
57
-	u32 ttr1cr;		/* Temperature Range 1 Control Register */
58
-	u32 ttr2cr;		/* Temperature Range 2 Control Register */
59
-	u32 ttr3cr;		/* Temperature Range 3 Control Register */
60
-};
46
+
47
+
48
+#define REGS_TTCFGR	0x080	/* Temperature Configuration Register */
49
+#define REGS_TSCFGR	0x084	/* Sensor Configuration Register */
50
+
51
+#define REGS_TRITSR(n)	(0x100 + 16 * (n)) /* Immediate Temperature
52
+					    * Site Register
53
+					    */
54
+#define TRITSR_V	BIT(31)
55
+#define REGS_V2_TMSAR(n)	(0x304 + 16 * (n))	/* TMU monitoring
56
+						* site adjustment register
57
+						*/
58
+#define REGS_TTRnCR(n)	(0xf10 + 4 * (n)) /* Temperature Range n
59
+					   * Control Register
60
+					   */
61
+#define REGS_IPBRR(n)		(0xbf8 + 4 * (n)) /* IP Block Revision
62
+						   * Register n
63
+						   */
64
+#define REGS_V2_TEUMR(n)	(0xf00 + 4 * (n))
6165 
6266 /*
6367  * Thermal zone data
6468  */
65
-struct qoriq_tmu_data {
66
-	struct thermal_zone_device *tz;
67
-	struct qoriq_tmu_regs __iomem *regs;
68
-	int sensor_id;
69
-	bool little_endian;
69
+struct qoriq_sensor {
70
+	int				id;
7071 };
7172 
72
-static void tmu_write(struct qoriq_tmu_data *p, u32 val, void __iomem *addr)
73
-{
74
-	if (p->little_endian)
75
-		iowrite32(val, addr);
76
-	else
77
-		iowrite32be(val, addr);
78
-}
73
+struct qoriq_tmu_data {
74
+	int ver;
75
+	struct regmap *regmap;
76
+	struct clk *clk;
77
+	struct qoriq_sensor	sensor[SITES_MAX];
78
+};
7979 
80
-static u32 tmu_read(struct qoriq_tmu_data *p, void __iomem *addr)
80
+static struct qoriq_tmu_data *qoriq_sensor_to_data(struct qoriq_sensor *s)
8181 {
82
-	if (p->little_endian)
83
-		return ioread32(addr);
84
-	else
85
-		return ioread32be(addr);
82
+	return container_of(s, struct qoriq_tmu_data, sensor[s->id]);
8683 }
8784 
8885 static int tmu_get_temp(void *p, int *temp)
8986 {
87
+	struct qoriq_sensor *qsensor = p;
88
+	struct qoriq_tmu_data *qdata = qoriq_sensor_to_data(qsensor);
9089 	u32 val;
91
-	struct qoriq_tmu_data *data = p;
90
+	/*
91
+	 * REGS_TRITSR(id) has the following layout:
92
+	 *
93
+	 * For TMU Rev1:
94
+	 * 31  ... 7 6 5 4 3 2 1 0
95
+	 *  V          TEMP
96
+	 *
97
+	 * Where V bit signifies if the measurement is ready and is
98
+	 * within sensor range. TEMP is an 8 bit value representing
99
+	 * temperature in Celsius.
92100 
93
-	val = tmu_read(data, &data->regs->site[data->sensor_id].tritsr);
94
-	*temp = (val & 0xff) * 1000;
101
+	 * For TMU Rev2:
102
+	 * 31  ... 8 7 6 5 4 3 2 1 0
103
+	 *  V          TEMP
104
+	 *
105
+	 * Where V bit signifies if the measurement is ready and is
106
+	 * within sensor range. TEMP is an 9 bit value representing
107
+	 * temperature in KelVin.
108
+	 */
109
+	if (regmap_read_poll_timeout(qdata->regmap,
110
+				     REGS_TRITSR(qsensor->id),
111
+				     val,
112
+				     val & TRITSR_V,
113
+				     USEC_PER_MSEC,
114
+				     10 * USEC_PER_MSEC))
115
+		return -ENODATA;
116
+
117
+	if (qdata->ver == TMU_VER1)
118
+		*temp = (val & GENMASK(7, 0)) * MILLIDEGREE_PER_DEGREE;
119
+	else
120
+		*temp = kelvin_to_millicelsius(val & GENMASK(8, 0));
95121 
96122 	return 0;
97123 }
98124 
99
-static int qoriq_tmu_get_sensor_id(void)
125
+static const struct thermal_zone_of_device_ops tmu_tz_ops = {
126
+	.get_temp = tmu_get_temp,
127
+};
128
+
129
+static int qoriq_tmu_register_tmu_zone(struct device *dev,
130
+				       struct qoriq_tmu_data *qdata)
100131 {
101
-	int ret, id;
102
-	struct of_phandle_args sensor_specs;
103
-	struct device_node *np, *sensor_np;
132
+	int id;
104133 
105
-	np = of_find_node_by_name(NULL, "thermal-zones");
106
-	if (!np)
107
-		return -ENODEV;
108
-
109
-	sensor_np = of_get_next_child(np, NULL);
110
-	ret = of_parse_phandle_with_args(sensor_np, "thermal-sensors",
111
-			"#thermal-sensor-cells",
112
-			0, &sensor_specs);
113
-	if (ret) {
114
-		of_node_put(np);
115
-		of_node_put(sensor_np);
116
-		return ret;
117
-	}
118
-
119
-	if (sensor_specs.args_count >= 1) {
120
-		id = sensor_specs.args[0];
121
-		WARN(sensor_specs.args_count > 1,
122
-				"%s: too many cells in sensor specifier %d\n",
123
-				sensor_specs.np->name, sensor_specs.args_count);
134
+	if (qdata->ver == TMU_VER1) {
135
+		regmap_write(qdata->regmap, REGS_TMR,
136
+			     TMR_MSITE_ALL | TMR_ME | TMR_ALPF);
124137 	} else {
125
-		id = 0;
138
+		regmap_write(qdata->regmap, REGS_V2_TMSR, TMR_MSITE_ALL);
139
+		regmap_write(qdata->regmap, REGS_TMR, TMR_ME | TMR_ALPF_V2);
126140 	}
127141 
128
-	of_node_put(np);
129
-	of_node_put(sensor_np);
142
+	for (id = 0; id < SITES_MAX; id++) {
143
+		struct thermal_zone_device *tzd;
144
+		struct qoriq_sensor *sensor = &qdata->sensor[id];
145
+		int ret;
130146 
131
-	return id;
147
+		sensor->id = id;
148
+
149
+		tzd = devm_thermal_zone_of_sensor_register(dev, id,
150
+							   sensor,
151
+							   &tmu_tz_ops);
152
+		ret = PTR_ERR_OR_ZERO(tzd);
153
+		if (ret) {
154
+			if (ret == -ENODEV)
155
+				continue;
156
+
157
+			regmap_write(qdata->regmap, REGS_TMR, TMR_DISABLE);
158
+			return ret;
159
+		}
160
+
161
+		if (devm_thermal_add_hwmon_sysfs(tzd))
162
+			dev_warn(dev,
163
+				 "Failed to add hwmon sysfs attributes\n");
164
+
165
+	}
166
+
167
+	return 0;
132168 }
133169 
134
-static int qoriq_tmu_calibration(struct platform_device *pdev)
170
+static int qoriq_tmu_calibration(struct device *dev,
171
+				 struct qoriq_tmu_data *data)
135172 {
136173 	int i, val, len;
137174 	u32 range[4];
138175 	const u32 *calibration;
139
-	struct device_node *np = pdev->dev.of_node;
140
-	struct qoriq_tmu_data *data = platform_get_drvdata(pdev);
176
+	struct device_node *np = dev->of_node;
141177 
142
-	if (of_property_read_u32_array(np, "fsl,tmu-range", range, 4)) {
143
-		dev_err(&pdev->dev, "missing calibration range.\n");
144
-		return -ENODEV;
178
+	len = of_property_count_u32_elems(np, "fsl,tmu-range");
179
+	if (len < 0 || len > 4) {
180
+		dev_err(dev, "invalid range data.\n");
181
+		return len;
182
+	}
183
+
184
+	val = of_property_read_u32_array(np, "fsl,tmu-range", range, len);
185
+	if (val != 0) {
186
+		dev_err(dev, "failed to read range data.\n");
187
+		return val;
145188 	}
146189 
147190 	/* Init temperature range registers */
148
-	tmu_write(data, range[0], &data->regs->ttr0cr);
149
-	tmu_write(data, range[1], &data->regs->ttr1cr);
150
-	tmu_write(data, range[2], &data->regs->ttr2cr);
151
-	tmu_write(data, range[3], &data->regs->ttr3cr);
191
+	for (i = 0; i < len; i++)
192
+		regmap_write(data->regmap, REGS_TTRnCR(i), range[i]);
152193 
153194 	calibration = of_get_property(np, "fsl,tmu-calibration", &len);
154195 	if (calibration == NULL || len % 8) {
155
-		dev_err(&pdev->dev, "invalid calibration data.\n");
196
+		dev_err(dev, "invalid calibration data.\n");
156197 		return -ENODEV;
157198 	}
158199 
159200 	for (i = 0; i < len; i += 8, calibration += 2) {
160201 		val = of_read_number(calibration, 1);
161
-		tmu_write(data, val, &data->regs->ttcfgr);
202
+		regmap_write(data->regmap, REGS_TTCFGR, val);
162203 		val = of_read_number(calibration + 1, 1);
163
-		tmu_write(data, val, &data->regs->tscfgr);
204
+		regmap_write(data->regmap, REGS_TSCFGR, val);
164205 	}
165206 
166207 	return 0;
....@@ -168,132 +209,166 @@
168209 
169210 static void qoriq_tmu_init_device(struct qoriq_tmu_data *data)
170211 {
212
+	int i;
213
+
171214 	/* Disable interrupt, using polling instead */
172
-	tmu_write(data, TIER_DISABLE, &data->regs->tier);
215
+	regmap_write(data->regmap, REGS_TIER, TIER_DISABLE);
173216 
174217 	/* Set update_interval */
175
-	tmu_write(data, TMTMIR_DEFAULT, &data->regs->tmtmir);
218
+
219
+	if (data->ver == TMU_VER1) {
220
+		regmap_write(data->regmap, REGS_TMTMIR, TMTMIR_DEFAULT);
221
+	} else {
222
+		regmap_write(data->regmap, REGS_V2_TMTMIR, TMTMIR_DEFAULT);
223
+		regmap_write(data->regmap, REGS_V2_TEUMR(0), TEUMR0_V2);
224
+		for (i = 0; i < SITES_MAX; i++)
225
+			regmap_write(data->regmap, REGS_V2_TMSAR(i), TMSARA_V2);
226
+	}
176227 
177228 	/* Disable monitoring */
178
-	tmu_write(data, TMR_DISABLE, &data->regs->tmr);
229
+	regmap_write(data->regmap, REGS_TMR, TMR_DISABLE);
179230 }
180231 
181
-static const struct thermal_zone_of_device_ops tmu_tz_ops = {
182
-	.get_temp = tmu_get_temp,
232
+static const struct regmap_range qoriq_yes_ranges[] = {
233
+	regmap_reg_range(REGS_TMR, REGS_TSCFGR),
234
+	regmap_reg_range(REGS_TTRnCR(0), REGS_TTRnCR(3)),
235
+	regmap_reg_range(REGS_V2_TEUMR(0), REGS_V2_TEUMR(2)),
236
+	regmap_reg_range(REGS_V2_TMSAR(0), REGS_V2_TMSAR(15)),
237
+	regmap_reg_range(REGS_IPBRR(0), REGS_IPBRR(1)),
238
+	/* Read only registers below */
239
+	regmap_reg_range(REGS_TRITSR(0), REGS_TRITSR(15)),
183240 };
241
+
242
+static const struct regmap_access_table qoriq_wr_table = {
243
+	.yes_ranges	= qoriq_yes_ranges,
244
+	.n_yes_ranges	= ARRAY_SIZE(qoriq_yes_ranges) - 1,
245
+};
246
+
247
+static const struct regmap_access_table qoriq_rd_table = {
248
+	.yes_ranges	= qoriq_yes_ranges,
249
+	.n_yes_ranges	= ARRAY_SIZE(qoriq_yes_ranges),
250
+};
251
+
252
+static void qoriq_tmu_action(void *p)
253
+{
254
+	struct qoriq_tmu_data *data = p;
255
+
256
+	regmap_write(data->regmap, REGS_TMR, TMR_DISABLE);
257
+	clk_disable_unprepare(data->clk);
258
+}
184259 
185260 static int qoriq_tmu_probe(struct platform_device *pdev)
186261 {
187262 	int ret;
263
+	u32 ver;
188264 	struct qoriq_tmu_data *data;
189265 	struct device_node *np = pdev->dev.of_node;
190
-	u32 site;
266
+	struct device *dev = &pdev->dev;
267
+	const bool little_endian = of_property_read_bool(np, "little-endian");
268
+	const enum regmap_endian format_endian =
269
+		little_endian ? REGMAP_ENDIAN_LITTLE : REGMAP_ENDIAN_BIG;
270
+	const struct regmap_config regmap_config = {
271
+		.reg_bits		= 32,
272
+		.val_bits		= 32,
273
+		.reg_stride		= 4,
274
+		.rd_table		= &qoriq_rd_table,
275
+		.wr_table		= &qoriq_wr_table,
276
+		.val_format_endian	= format_endian,
277
+		.max_register		= SZ_4K,
278
+	};
279
+	void __iomem *base;
191280 
192
-	if (!np) {
193
-		dev_err(&pdev->dev, "Device OF-Node is NULL");
194
-		return -ENODEV;
195
-	}
196
-
197
-	data = devm_kzalloc(&pdev->dev, sizeof(struct qoriq_tmu_data),
281
+	data = devm_kzalloc(dev, sizeof(struct qoriq_tmu_data),
198282 			    GFP_KERNEL);
199283 	if (!data)
200284 		return -ENOMEM;
201285 
202
-	platform_set_drvdata(pdev, data);
203
-
204
-	data->little_endian = of_property_read_bool(np, "little-endian");
205
-
206
-	data->sensor_id = qoriq_tmu_get_sensor_id();
207
-	if (data->sensor_id < 0) {
208
-		dev_err(&pdev->dev, "Failed to get sensor id\n");
209
-		ret = -ENODEV;
210
-		goto err_iomap;
286
+	base = devm_platform_ioremap_resource(pdev, 0);
287
+	ret = PTR_ERR_OR_ZERO(base);
288
+	if (ret) {
289
+		dev_err(dev, "Failed to get memory region\n");
290
+		return ret;
211291 	}
212292 
213
-	data->regs = of_iomap(np, 0);
214
-	if (!data->regs) {
215
-		dev_err(&pdev->dev, "Failed to get memory region\n");
216
-		ret = -ENODEV;
217
-		goto err_iomap;
293
+	data->regmap = devm_regmap_init_mmio(dev, base, &regmap_config);
294
+	ret = PTR_ERR_OR_ZERO(data->regmap);
295
+	if (ret) {
296
+		dev_err(dev, "Failed to init regmap (%d)\n", ret);
297
+		return ret;
218298 	}
299
+
300
+	data->clk = devm_clk_get_optional(dev, NULL);
301
+	if (IS_ERR(data->clk))
302
+		return PTR_ERR(data->clk);
303
+
304
+	ret = clk_prepare_enable(data->clk);
305
+	if (ret) {
306
+		dev_err(dev, "Failed to enable clock\n");
307
+		return ret;
308
+	}
309
+
310
+	ret = devm_add_action_or_reset(dev, qoriq_tmu_action, data);
311
+	if (ret)
312
+		return ret;
313
+
314
+	/* version register offset at: 0xbf8 on both v1 and v2 */
315
+	ret = regmap_read(data->regmap, REGS_IPBRR(0), &ver);
316
+	if (ret) {
317
+		dev_err(&pdev->dev, "Failed to read IP block version\n");
318
+		return ret;
319
+	}
320
+	data->ver = (ver >> 8) & 0xff;
219321 
220322 	qoriq_tmu_init_device(data);	/* TMU initialization */
221323 
222
-	ret = qoriq_tmu_calibration(pdev);	/* TMU calibration */
324
+	ret = qoriq_tmu_calibration(dev, data);	/* TMU calibration */
223325 	if (ret < 0)
224
-		goto err_tmu;
326
+		return ret;
225327 
226
-	data->tz = devm_thermal_zone_of_sensor_register(&pdev->dev,
227
-							data->sensor_id,
228
-							data, &tmu_tz_ops);
229
-	if (IS_ERR(data->tz)) {
230
-		ret = PTR_ERR(data->tz);
231
-		dev_err(&pdev->dev,
232
-			"Failed to register thermal zone device %d\n", ret);
233
-		goto err_tmu;
328
+	ret = qoriq_tmu_register_tmu_zone(dev, data);
329
+	if (ret < 0) {
330
+		dev_err(dev, "Failed to register sensors\n");
331
+		return ret;
234332 	}
235333 
236
-	/* Enable monitoring */
237
-	site = 0x1 << (15 - data->sensor_id);
238
-	tmu_write(data, site | TMR_ME | TMR_ALPF, &data->regs->tmr);
239
-
240
-	return 0;
241
-
242
-err_tmu:
243
-	iounmap(data->regs);
244
-
245
-err_iomap:
246
-	platform_set_drvdata(pdev, NULL);
247
-
248
-	return ret;
249
-}
250
-
251
-static int qoriq_tmu_remove(struct platform_device *pdev)
252
-{
253
-	struct qoriq_tmu_data *data = platform_get_drvdata(pdev);
254
-
255
-	/* Disable monitoring */
256
-	tmu_write(data, TMR_DISABLE, &data->regs->tmr);
257
-
258
-	iounmap(data->regs);
259
-	platform_set_drvdata(pdev, NULL);
334
+	platform_set_drvdata(pdev, data);
260335 
261336 	return 0;
262337 }
263338 
264
-#ifdef CONFIG_PM_SLEEP
265
-static int qoriq_tmu_suspend(struct device *dev)
339
+static int __maybe_unused qoriq_tmu_suspend(struct device *dev)
266340 {
267
-	u32 tmr;
341
+	struct qoriq_tmu_data *data = dev_get_drvdata(dev);
342
+	int ret;
343
+
344
+	ret = regmap_update_bits(data->regmap, REGS_TMR, TMR_ME, 0);
345
+	if (ret)
346
+		return ret;
347
+
348
+	clk_disable_unprepare(data->clk);
349
+
350
+	return 0;
351
+}
352
+
353
+static int __maybe_unused qoriq_tmu_resume(struct device *dev)
354
+{
355
+	int ret;
268356 	struct qoriq_tmu_data *data = dev_get_drvdata(dev);
269357 
270
-	/* Disable monitoring */
271
-	tmr = tmu_read(data, &data->regs->tmr);
272
-	tmr &= ~TMR_ME;
273
-	tmu_write(data, tmr, &data->regs->tmr);
274
-
275
-	return 0;
276
-}
277
-
278
-static int qoriq_tmu_resume(struct device *dev)
279
-{
280
-	u32 tmr;
281
-	struct qoriq_tmu_data *data = dev_get_drvdata(dev);
358
+	ret = clk_prepare_enable(data->clk);
359
+	if (ret)
360
+		return ret;
282361 
283362 	/* Enable monitoring */
284
-	tmr = tmu_read(data, &data->regs->tmr);
285
-	tmr |= TMR_ME;
286
-	tmu_write(data, tmr, &data->regs->tmr);
287
-
288
-	return 0;
363
+	return regmap_update_bits(data->regmap, REGS_TMR, TMR_ME, TMR_ME);
289364 }
290
-#endif
291365 
292366 static SIMPLE_DEV_PM_OPS(qoriq_tmu_pm_ops,
293367 			 qoriq_tmu_suspend, qoriq_tmu_resume);
294368 
295369 static const struct of_device_id qoriq_tmu_match[] = {
296370 	{ .compatible = "fsl,qoriq-tmu", },
371
+	{ .compatible = "fsl,imx8mq-tmu", },
297372 	{},
298373 };
299374 MODULE_DEVICE_TABLE(of, qoriq_tmu_match);
....@@ -305,7 +380,6 @@
305380 		.of_match_table	= qoriq_tmu_match,
306381 	},
307382 	.probe	= qoriq_tmu_probe,
308
-	.remove	= qoriq_tmu_remove,
309383 };
310384 module_platform_driver(qoriq_tmu);
311385