forked from ~ljy/RK356X_SDK_RELEASE
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hc
2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376 
 kernel/drivers/spi/spi-imx.c
....@@ -8,25 +8,31 @@
88 #include <linux/dmaengine.h>
99 #include <linux/dma-mapping.h>
1010 #include <linux/err.h>
11
-#include <linux/gpio.h>
1211 #include <linux/interrupt.h>
1312 #include <linux/io.h>
1413 #include <linux/irq.h>
1514 #include <linux/kernel.h>
1615 #include <linux/module.h>
16
+#include <linux/pinctrl/consumer.h>
1717 #include <linux/platform_device.h>
18
+#include <linux/pm_runtime.h>
1819 #include <linux/slab.h>
1920 #include <linux/spi/spi.h>
2021 #include <linux/spi/spi_bitbang.h>
2122 #include <linux/types.h>
2223 #include <linux/of.h>
2324 #include <linux/of_device.h>
24
-#include <linux/of_gpio.h>
25
+#include <linux/property.h>
2526 
2627 #include <linux/platform_data/dma-imx.h>
27
-#include <linux/platform_data/spi-imx.h>
2828 
2929 #define DRIVER_NAME "spi_imx"
30
+
31
+static bool use_dma = true;
32
+module_param(use_dma, bool, 0644);
33
+MODULE_PARM_DESC(use_dma, "Enable usage of DMA when available (default)");
34
+
35
+#define MXC_RPM_TIMEOUT		2000 /* 2000ms */
3036 
3137 #define MXC_CSPIRXDATA		0x00
3238 #define MXC_CSPITXDATA		0x04
....@@ -39,8 +45,8 @@
3945 #define MXC_INT_TE	(1 << 1) /* Transmit FIFO empty interrupt */
4046 #define MXC_INT_RDR	BIT(4) /* Receive date threshold interrupt */
4147 
42
-/* The maximum  bytes that a sdma BD can transfer.*/
43
-#define MAX_SDMA_BD_BYTES  (1 << 15)
48
+/* The maximum bytes that a sdma BD can transfer. */
49
+#define MAX_SDMA_BD_BYTES (1 << 15)
4450 #define MX51_ECSPI_CTRL_MAX_BURST	512
4551 /* The maximum bytes that IMX53_ECSPI can transfer in slave mode.*/
4652 #define MX53_MAX_TRANSFER_BYTES		512
....@@ -59,11 +65,14 @@
5965 
6066 struct spi_imx_devtype_data {
6167 	void (*intctrl)(struct spi_imx_data *, int);
62
-	int (*config)(struct spi_device *);
68
+	int (*prepare_message)(struct spi_imx_data *, struct spi_message *);
69
+	int (*prepare_transfer)(struct spi_imx_data *, struct spi_device *);
6370 	void (*trigger)(struct spi_imx_data *);
6471 	int (*rx_available)(struct spi_imx_data *);
6572 	void (*reset)(struct spi_imx_data *);
73
+	void (*setup_wml)(struct spi_imx_data *);
6674 	void (*disable)(struct spi_imx_data *);
75
+	void (*disable_dma)(struct spi_imx_data *);
6776 	bool has_dmamode;
6877 	bool has_slavemode;
6978 	unsigned int fifo_size;
....@@ -84,7 +93,6 @@
8493 	unsigned long spi_clk;
8594 	unsigned int spi_bus_clk;
8695 
87
-	unsigned int speed_hz;
8896 	unsigned int bits_per_word;
8997 	unsigned int spi_drctl;
9098 
....@@ -216,7 +224,9 @@
216224 			 struct spi_transfer *transfer)
217225 {
218226 	struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
219
-	unsigned int bytes_per_word, i;
227
+
228
+	if (!use_dma || master->fallback)
229
+		return false;
220230 
221231 	if (!master->dma_rx)
222232 		return false;
....@@ -224,14 +234,9 @@
224234 	if (spi_imx->slave_mode)
225235 		return false;
226236 
227
-	bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word);
237
+	if (transfer->len < spi_imx->devtype_data->fifo_size)
238
+		return false;
228239 
229
-	for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) {
230
-		if (!(transfer->len % (i * bytes_per_word)))
231
-			break;
232
-	}
233
-
234
-	spi_imx->wml = i;
235240 	spi_imx->dynamic_burst = 0;
236241 
237242 	return true;
....@@ -261,7 +266,7 @@
261266 #define MX51_ECSPI_INT_RREN		(1 <<  3)
262267 #define MX51_ECSPI_INT_RDREN		(1 <<  4)
263268 
264
-#define MX51_ECSPI_DMA      0x14
269
+#define MX51_ECSPI_DMA		0x14
265270 #define MX51_ECSPI_DMA_TX_WML(wml)	((wml) & 0x3f)
266271 #define MX51_ECSPI_DMA_RX_WML(wml)	(((wml) & 0x3f) << 16)
267272 #define MX51_ECSPI_DMA_RXT_WML(wml)	(((wml) & 0x3f) << 24)
....@@ -429,8 +434,7 @@
429434 	unsigned int pre, post;
430435 	unsigned int fin = spi_imx->spi_clk;
431436 
432
-	if (unlikely(fspi > fin))
433
-		return 0;
437
+	fspi = min(fspi, fin);
434438 
435439 	post = fls(fin) - fls(fspi);
436440 	if (fin > fspi << post)
....@@ -482,6 +486,11 @@
482486 	writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
483487 }
484488 
489
+static void mx51_disable_dma(struct spi_imx_data *spi_imx)
490
+{
491
+	writel(0, spi_imx->base + MX51_ECSPI_DMA);
492
+}
493
+
485494 static void mx51_ecspi_disable(struct spi_imx_data *spi_imx)
486495 {
487496 	u32 ctrl;
....@@ -491,11 +500,14 @@
491500 	writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
492501 }
493502 
494
-static int mx51_ecspi_config(struct spi_device *spi)
503
+static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx,
504
+				      struct spi_message *msg)
495505 {
496
-	struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
506
+	struct spi_device *spi = msg->spi;
507
+	struct spi_transfer *xfer;
497508 	u32 ctrl = MX51_ECSPI_CTRL_ENABLE;
498
-	u32 clk = spi_imx->speed_hz, delay, reg;
509
+	u32 min_speed_hz = ~0U;
510
+	u32 testreg, delay;
499511 	u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
500512 
501513 	/* set Master or Slave mode */
....@@ -510,19 +522,21 @@
510522 	if (spi->mode & SPI_READY)
511523 		ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl);
512524 
513
-	/* set clock speed */
514
-	ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->speed_hz, &clk);
515
-	spi_imx->spi_bus_clk = clk;
516
-
517525 	/* set chip select to use */
518526 	ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select);
519527 
520
-	if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
521
-		ctrl |= (spi_imx->slave_burst * 8 - 1)
522
-			<< MX51_ECSPI_CTRL_BL_OFFSET;
528
+	/*
529
+	 * The ctrl register must be written first, with the EN bit set other
530
+	 * registers must not be written to.
531
+	 */
532
+	writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
533
+
534
+	testreg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
535
+	if (spi->mode & SPI_LOOP)
536
+		testreg |= MX51_ECSPI_TESTREG_LBC;
523537 	else
524
-		ctrl |= (spi_imx->bits_per_word - 1)
525
-			<< MX51_ECSPI_CTRL_BL_OFFSET;
538
+		testreg &= ~MX51_ECSPI_TESTREG_LBC;
539
+	writel(testreg, spi_imx->base + MX51_ECSPI_TESTREG);
526540 
527541 	/*
528542 	 * eCSPI burst completion by Chip Select signal in Slave mode
....@@ -546,23 +560,11 @@
546560 		cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
547561 		cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
548562 	}
563
+
549564 	if (spi->mode & SPI_CS_HIGH)
550565 		cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
551566 	else
552567 		cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
553
-
554
-	if (spi_imx->usedma)
555
-		ctrl |= MX51_ECSPI_CTRL_SMC;
556
-
557
-	/* CTRL register always go first to bring out controller from reset */
558
-	writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
559
-
560
-	reg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
561
-	if (spi->mode & SPI_LOOP)
562
-		reg |= MX51_ECSPI_TESTREG_LBC;
563
-	else
564
-		reg &= ~MX51_ECSPI_TESTREG_LBC;
565
-	writel(reg, spi_imx->base + MX51_ECSPI_TESTREG);
566568 
567569 	writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
568570 
....@@ -576,25 +578,68 @@
576578 	 * be asserted before the SCLK polarity changes, which would disrupt
577579 	 * the SPI communication as the device on the other end would consider
578580 	 * the change of SCLK polarity as a clock tick already.
581
+	 *
582
+	 * Because spi_imx->spi_bus_clk is only set in bitbang prepare_message
583
+	 * callback, iterate over all the transfers in spi_message, find the
584
+	 * one with lowest bus frequency, and use that bus frequency for the
585
+	 * delay calculation. In case all transfers have speed_hz == 0, then
586
+	 * min_speed_hz is ~0 and the resulting delay is zero.
579587 	 */
580
-	delay = (2 * 1000000) / clk;
588
+	list_for_each_entry(xfer, &msg->transfers, transfer_list) {
589
+		if (!xfer->speed_hz)
590
+			continue;
591
+		min_speed_hz = min(xfer->speed_hz, min_speed_hz);
592
+	}
593
+
594
+	delay = (2 * 1000000) / min_speed_hz;
581595 	if (likely(delay < 10))	/* SCLK is faster than 100 kHz */
582596 		udelay(delay);
583597 	else			/* SCLK is _very_ slow */
584598 		usleep_range(delay, delay + 10);
585599 
600
+	return 0;
601
+}
602
+
603
+static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
604
+				       struct spi_device *spi)
605
+{
606
+	u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
607
+	u32 clk;
608
+
609
+	/* Clear BL field and set the right value */
610
+	ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
611
+	if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
612
+		ctrl |= (spi_imx->slave_burst * 8 - 1)
613
+			<< MX51_ECSPI_CTRL_BL_OFFSET;
614
+	else
615
+		ctrl |= (spi_imx->bits_per_word - 1)
616
+			<< MX51_ECSPI_CTRL_BL_OFFSET;
617
+
618
+	/* set clock speed */
619
+	ctrl &= ~(0xf << MX51_ECSPI_CTRL_POSTDIV_OFFSET |
620
+		  0xf << MX51_ECSPI_CTRL_PREDIV_OFFSET);
621
+	ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->spi_bus_clk, &clk);
622
+	spi_imx->spi_bus_clk = clk;
623
+
624
+	if (spi_imx->usedma)
625
+		ctrl |= MX51_ECSPI_CTRL_SMC;
626
+
627
+	writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
628
+
629
+	return 0;
630
+}
631
+
632
+static void mx51_setup_wml(struct spi_imx_data *spi_imx)
633
+{
586634 	/*
587635 	 * Configure the DMA register: setup the watermark
588636 	 * and enable DMA request.
589637 	 */
590
-
591
-	writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml) |
638
+	writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) |
592639 		MX51_ECSPI_DMA_TX_WML(spi_imx->wml) |
593640 		MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
594641 		MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
595642 		MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
596
-
597
-	return 0;
598643 }
599644 
600645 static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
....@@ -661,13 +706,19 @@
661706 	writel(reg, spi_imx->base + MXC_CSPICTRL);
662707 }
663708 
664
-static int mx31_config(struct spi_device *spi)
709
+static int mx31_prepare_message(struct spi_imx_data *spi_imx,
710
+				struct spi_message *msg)
665711 {
666
-	struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
712
+	return 0;
713
+}
714
+
715
+static int mx31_prepare_transfer(struct spi_imx_data *spi_imx,
716
+				 struct spi_device *spi)
717
+{
667718 	unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
668719 	unsigned int clk;
669720 
670
-	reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->speed_hz, &clk) <<
721
+	reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) <<
671722 		MX31_CSPICTRL_DR_SHIFT;
672723 	spi_imx->spi_bus_clk = clk;
673724 
....@@ -684,7 +735,7 @@
684735 		reg |= MX31_CSPICTRL_POL;
685736 	if (spi->mode & SPI_CS_HIGH)
686737 		reg |= MX31_CSPICTRL_SSPOL;
687
-	if (!gpio_is_valid(spi->cs_gpio))
738
+	if (!spi->cs_gpiod)
688739 		reg |= (spi->chip_select) <<
689740 			(is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
690741 						  MX31_CSPICTRL_CS_SHIFT);
....@@ -702,8 +753,10 @@
702753 	writel(reg, spi_imx->base + MX31_CSPI_TESTREG);
703754 
704755 	if (spi_imx->usedma) {
705
-		/* configure DMA requests when RXFIFO is half full and
706
-		   when TXFIFO is half empty */
756
+		/*
757
+		 * configure DMA requests when RXFIFO is half full and
758
+		 * when TXFIFO is half empty
759
+		 */
707760 		writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN,
708761 			spi_imx->base + MX31_CSPI_DMAREG);
709762 	}
....@@ -757,14 +810,20 @@
757810 	writel(reg, spi_imx->base + MXC_CSPICTRL);
758811 }
759812 
760
-static int mx21_config(struct spi_device *spi)
813
+static int mx21_prepare_message(struct spi_imx_data *spi_imx,
814
+				struct spi_message *msg)
761815 {
762
-	struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
816
+	return 0;
817
+}
818
+
819
+static int mx21_prepare_transfer(struct spi_imx_data *spi_imx,
820
+				 struct spi_device *spi)
821
+{
763822 	unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
764823 	unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
765824 	unsigned int clk;
766825 
767
-	reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, spi_imx->speed_hz, max, &clk)
826
+	reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, spi_imx->spi_bus_clk, max, &clk)
768827 		<< MX21_CSPICTRL_DR_SHIFT;
769828 	spi_imx->spi_bus_clk = clk;
770829 
....@@ -776,7 +835,7 @@
776835 		reg |= MX21_CSPICTRL_POL;
777836 	if (spi->mode & SPI_CS_HIGH)
778837 		reg |= MX21_CSPICTRL_SSPOL;
779
-	if (!gpio_is_valid(spi->cs_gpio))
838
+	if (!spi->cs_gpiod)
780839 		reg |= spi->chip_select << MX21_CSPICTRL_CS_SHIFT;
781840 
782841 	writel(reg, spi_imx->base + MXC_CSPICTRL);
....@@ -826,13 +885,19 @@
826885 	writel(reg, spi_imx->base + MXC_CSPICTRL);
827886 }
828887 
829
-static int mx1_config(struct spi_device *spi)
888
+static int mx1_prepare_message(struct spi_imx_data *spi_imx,
889
+			       struct spi_message *msg)
830890 {
831
-	struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
891
+	return 0;
892
+}
893
+
894
+static int mx1_prepare_transfer(struct spi_imx_data *spi_imx,
895
+				struct spi_device *spi)
896
+{
832897 	unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
833898 	unsigned int clk;
834899 
835
-	reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->speed_hz, &clk) <<
900
+	reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) <<
836901 		MX1_CSPICTRL_DR_SHIFT;
837902 	spi_imx->spi_bus_clk = clk;
838903 
....@@ -860,7 +925,8 @@
860925 
861926 static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
862927 	.intctrl = mx1_intctrl,
863
-	.config = mx1_config,
928
+	.prepare_message = mx1_prepare_message,
929
+	.prepare_transfer = mx1_prepare_transfer,
864930 	.trigger = mx1_trigger,
865931 	.rx_available = mx1_rx_available,
866932 	.reset = mx1_reset,
....@@ -873,7 +939,8 @@
873939 
874940 static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
875941 	.intctrl = mx21_intctrl,
876
-	.config = mx21_config,
942
+	.prepare_message = mx21_prepare_message,
943
+	.prepare_transfer = mx21_prepare_transfer,
877944 	.trigger = mx21_trigger,
878945 	.rx_available = mx21_rx_available,
879946 	.reset = mx21_reset,
....@@ -887,7 +954,8 @@
887954 static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
888955 	/* i.mx27 cspi shares the functions with i.mx21 one */
889956 	.intctrl = mx21_intctrl,
890
-	.config = mx21_config,
957
+	.prepare_message = mx21_prepare_message,
958
+	.prepare_transfer = mx21_prepare_transfer,
891959 	.trigger = mx21_trigger,
892960 	.rx_available = mx21_rx_available,
893961 	.reset = mx21_reset,
....@@ -900,7 +968,8 @@
900968 
901969 static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
902970 	.intctrl = mx31_intctrl,
903
-	.config = mx31_config,
971
+	.prepare_message = mx31_prepare_message,
972
+	.prepare_transfer = mx31_prepare_transfer,
904973 	.trigger = mx31_trigger,
905974 	.rx_available = mx31_rx_available,
906975 	.reset = mx31_reset,
....@@ -914,7 +983,8 @@
914983 static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
915984 	/* i.mx35 and later cspi shares the functions with i.mx31 one */
916985 	.intctrl = mx31_intctrl,
917
-	.config = mx31_config,
986
+	.prepare_message = mx31_prepare_message,
987
+	.prepare_transfer = mx31_prepare_transfer,
918988 	.trigger = mx31_trigger,
919989 	.rx_available = mx31_rx_available,
920990 	.reset = mx31_reset,
....@@ -927,10 +997,13 @@
927997 
928998 static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
929999 	.intctrl = mx51_ecspi_intctrl,
930
-	.config = mx51_ecspi_config,
1000
+	.prepare_message = mx51_ecspi_prepare_message,
1001
+	.prepare_transfer = mx51_ecspi_prepare_transfer,
9311002 	.trigger = mx51_ecspi_trigger,
9321003 	.rx_available = mx51_ecspi_rx_available,
9331004 	.reset = mx51_ecspi_reset,
1005
+	.setup_wml = mx51_setup_wml,
1006
+	.disable_dma = mx51_disable_dma,
9341007 	.fifo_size = 64,
9351008 	.has_dmamode = true,
9361009 	.dynamic_burst = true,
....@@ -941,9 +1014,11 @@
9411014 
9421015 static struct spi_imx_devtype_data imx53_ecspi_devtype_data = {
9431016 	.intctrl = mx51_ecspi_intctrl,
944
-	.config = mx51_ecspi_config,
1017
+	.prepare_message = mx51_ecspi_prepare_message,
1018
+	.prepare_transfer = mx51_ecspi_prepare_transfer,
9451019 	.trigger = mx51_ecspi_trigger,
9461020 	.rx_available = mx51_ecspi_rx_available,
1021
+	.disable_dma = mx51_disable_dma,
9471022 	.reset = mx51_ecspi_reset,
9481023 	.fifo_size = 64,
9491024 	.has_dmamode = true,
....@@ -991,20 +1066,6 @@
9911066 };
9921067 MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
9931068 
994
-static void spi_imx_chipselect(struct spi_device *spi, int is_active)
995
-{
996
-	int active = is_active != BITBANG_CS_INACTIVE;
997
-	int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
998
-
999
-	if (spi->mode & SPI_NO_CS)
1000
-		return;
1001
-
1002
-	if (!gpio_is_valid(spi->cs_gpio))
1003
-		return;
1004
-
1005
-	gpio_set_value(spi->cs_gpio, dev_is_lowactive ^ active);
1006
-}
1007
-
10081069 static void spi_imx_set_burst_len(struct spi_imx_data *spi_imx, int n_bits)
10091070 {
10101071 	u32 ctrl;
....@@ -1049,7 +1110,7 @@
10491110 		if (!spi_imx->count)
10501111 			break;
10511112 		if (spi_imx->dynamic_burst &&
1052
-		    spi_imx->txfifo >=  DIV_ROUND_UP(spi_imx->remainder,
1113
+		    spi_imx->txfifo >= DIV_ROUND_UP(spi_imx->remainder,
10531114 						     fifo_words))
10541115 			break;
10551116 		spi_imx->tx(spi_imx);
....@@ -1138,13 +1199,21 @@
11381199 				 struct spi_transfer *t)
11391200 {
11401201 	struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1141
-	int ret;
11421202 
11431203 	if (!t)
11441204 		return 0;
11451205 
1206
+	if (!t->speed_hz) {
1207
+		if (!spi->max_speed_hz) {
1208
+			dev_err(&spi->dev, "no speed_hz provided!\n");
1209
+			return -EINVAL;
1210
+		}
1211
+		dev_dbg(&spi->dev, "using spi->max_speed_hz!\n");
1212
+		spi_imx->spi_bus_clk = spi->max_speed_hz;
1213
+	} else
1214
+		spi_imx->spi_bus_clk = t->speed_hz;
1215
+
11461216 	spi_imx->bits_per_word = t->bits_per_word;
1147
-	spi_imx->speed_hz  = t->speed_hz;
11481217 
11491218 	/*
11501219 	 * Initialize the functions for transfer. To transfer non byte-aligned
....@@ -1175,15 +1244,9 @@
11751244 	}
11761245 
11771246 	if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t))
1178
-		spi_imx->usedma = 1;
1247
+		spi_imx->usedma = true;
11791248 	else
1180
-		spi_imx->usedma = 0;
1181
-
1182
-	if (spi_imx->usedma) {
1183
-		ret = spi_imx_dma_configure(spi->master);
1184
-		if (ret)
1185
-			return ret;
1186
-	}
1249
+		spi_imx->usedma = false;
11871250 
11881251 	if (is_imx53_ecspi(spi_imx) && spi_imx->slave_mode) {
11891252 		spi_imx->rx = mx53_ecspi_rx_slave;
....@@ -1191,7 +1254,7 @@
11911254 		spi_imx->slave_burst = t->len;
11921255 	}
11931256 
1194
-	spi_imx->devtype_data->config(spi);
1257
+	spi_imx->devtype_data->prepare_transfer(spi_imx, spi);
11951258 
11961259 	return 0;
11971260 }
....@@ -1223,7 +1286,7 @@
12231286 	spi_imx->wml = spi_imx->devtype_data->fifo_size / 2;
12241287 
12251288 	/* Prepare for TX DMA: */
1226
-	master->dma_tx = dma_request_slave_channel_reason(dev, "tx");
1289
+	master->dma_tx = dma_request_chan(dev, "tx");
12271290 	if (IS_ERR(master->dma_tx)) {
12281291 		ret = PTR_ERR(master->dma_tx);
12291292 		dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
....@@ -1232,7 +1295,7 @@
12321295 	}
12331296 
12341297 	/* Prepare for RX : */
1235
-	master->dma_rx = dma_request_slave_channel_reason(dev, "rx");
1298
+	master->dma_rx = dma_request_chan(dev, "rx");
12361299 	if (IS_ERR(master->dma_rx)) {
12371300 		ret = PTR_ERR(master->dma_rx);
12381301 		dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
....@@ -1289,6 +1352,32 @@
12891352 	unsigned long timeout;
12901353 	struct spi_master *master = spi_imx->bitbang.master;
12911354 	struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
1355
+	struct scatterlist *last_sg = sg_last(rx->sgl, rx->nents);
1356
+	unsigned int bytes_per_word, i;
1357
+	int ret;
1358
+
1359
+	/* Get the right burst length from the last sg to ensure no tail data */
1360
+	bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word);
1361
+	for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) {
1362
+		if (!(sg_dma_len(last_sg) % (i * bytes_per_word)))
1363
+			break;
1364
+	}
1365
+	/* Use 1 as wml in case no available burst length got */
1366
+	if (i == 0)
1367
+		i = 1;
1368
+
1369
+	spi_imx->wml =  i;
1370
+
1371
+	ret = spi_imx_dma_configure(master);
1372
+	if (ret)
1373
+		goto dma_failure_no_start;
1374
+
1375
+	if (!spi_imx->devtype_data->setup_wml) {
1376
+		dev_err(spi_imx->dev, "No setup_wml()?\n");
1377
+		ret = -EINVAL;
1378
+		goto dma_failure_no_start;
1379
+	}
1380
+	spi_imx->devtype_data->setup_wml(spi_imx);
12921381 
12931382 	/*
12941383 	 * The TX DMA setup starts the transfer, so make sure RX is configured
....@@ -1297,8 +1386,10 @@
12971386 	desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
12981387 				rx->sgl, rx->nents, DMA_DEV_TO_MEM,
12991388 				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1300
-	if (!desc_rx)
1301
-		return -EINVAL;
1389
+	if (!desc_rx) {
1390
+		ret = -EINVAL;
1391
+		goto dma_failure_no_start;
1392
+	}
13021393 
13031394 	desc_rx->callback = spi_imx_dma_rx_callback;
13041395 	desc_rx->callback_param = (void *)spi_imx;
....@@ -1311,6 +1402,7 @@
13111402 				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
13121403 	if (!desc_tx) {
13131404 		dmaengine_terminate_all(master->dma_tx);
1405
+		dmaengine_terminate_all(master->dma_rx);
13141406 		return -EINVAL;
13151407 	}
13161408 
....@@ -1342,6 +1434,10 @@
13421434 	}
13431435 
13441436 	return transfer->len;
1437
+/* fallback to pio */
1438
+dma_failure_no_start:
1439
+	transfer->error |= SPI_TRANS_FAIL_NO_START;
1440
+	return ret;
13451441 }
13461442 
13471443 static int spi_imx_pio_transfer(struct spi_device *spi,
....@@ -1425,6 +1521,8 @@
14251521 {
14261522 	struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
14271523 
1524
+	transfer->effective_speed_hz = spi_imx->spi_bus_clk;
1525
+
14281526 	/* flush rxfifo before transfer */
14291527 	while (spi_imx->devtype_data->rx_available(spi_imx))
14301528 		readl(spi_imx->base + MXC_CSPIRXDATA);
....@@ -1434,23 +1532,14 @@
14341532 
14351533 	if (spi_imx->usedma)
14361534 		return spi_imx_dma_transfer(spi_imx, transfer);
1437
-	else
1438
-		return spi_imx_pio_transfer(spi, transfer);
1535
+
1536
+	return spi_imx_pio_transfer(spi, transfer);
14391537 }
14401538 
14411539 static int spi_imx_setup(struct spi_device *spi)
14421540 {
14431541 	dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
14441542 		 spi->mode, spi->bits_per_word, spi->max_speed_hz);
1445
-
1446
-	if (spi->mode & SPI_NO_CS)
1447
-		return 0;
1448
-
1449
-	if (gpio_is_valid(spi->cs_gpio))
1450
-		gpio_direction_output(spi->cs_gpio,
1451
-				      spi->mode & SPI_CS_HIGH ? 0 : 1);
1452
-
1453
-	spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
14541543 
14551544 	return 0;
14561545 }
....@@ -1465,17 +1554,20 @@
14651554 	struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
14661555 	int ret;
14671556 
1468
-	ret = clk_enable(spi_imx->clk_per);
1469
-	if (ret)
1470
-		return ret;
1471
-
1472
-	ret = clk_enable(spi_imx->clk_ipg);
1473
-	if (ret) {
1474
-		clk_disable(spi_imx->clk_per);
1557
+	ret = pm_runtime_get_sync(spi_imx->dev);
1558
+	if (ret < 0) {
1559
+		pm_runtime_put_noidle(spi_imx->dev);
1560
+		dev_err(spi_imx->dev, "failed to enable clock\n");
14751561 		return ret;
14761562 	}
14771563 
1478
-	return 0;
1564
+	ret = spi_imx->devtype_data->prepare_message(spi_imx, msg);
1565
+	if (ret) {
1566
+		pm_runtime_mark_last_busy(spi_imx->dev);
1567
+		pm_runtime_put_autosuspend(spi_imx->dev);
1568
+	}
1569
+
1570
+	return ret;
14791571 }
14801572 
14811573 static int
....@@ -1483,8 +1575,8 @@
14831575 {
14841576 	struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
14851577 
1486
-	clk_disable(spi_imx->clk_ipg);
1487
-	clk_disable(spi_imx->clk_per);
1578
+	pm_runtime_mark_last_busy(spi_imx->dev);
1579
+	pm_runtime_put_autosuspend(spi_imx->dev);
14881580 	return 0;
14891581 }
14901582 
....@@ -1503,20 +1595,14 @@
15031595 	struct device_node *np = pdev->dev.of_node;
15041596 	const struct of_device_id *of_id =
15051597 			of_match_device(spi_imx_dt_ids, &pdev->dev);
1506
-	struct spi_imx_master *mxc_platform_info =
1507
-			dev_get_platdata(&pdev->dev);
15081598 	struct spi_master *master;
15091599 	struct spi_imx_data *spi_imx;
15101600 	struct resource *res;
1511
-	int i, ret, irq, spi_drctl;
1601
+	int ret, irq, spi_drctl;
15121602 	const struct spi_imx_devtype_data *devtype_data = of_id ? of_id->data :
15131603 		(struct spi_imx_devtype_data *)pdev->id_entry->driver_data;
15141604 	bool slave_mode;
1515
-
1516
-	if (!np && !mxc_platform_info) {
1517
-		dev_err(&pdev->dev, "can't get the platform data\n");
1518
-		return -EINVAL;
1519
-	}
1605
+	u32 val;
15201606 
15211607 	slave_mode = devtype_data->has_slavemode &&
15221608 			of_property_read_bool(np, "spi-slave");
....@@ -1539,6 +1625,7 @@
15391625 
15401626 	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
15411627 	master->bus_num = np ? -1 : pdev->id;
1628
+	master->use_gpio_descriptors = true;
15421629 
15431630 	spi_imx = spi_master_get_devdata(master);
15441631 	spi_imx->bitbang.master = master;
....@@ -1547,28 +1634,17 @@
15471634 
15481635 	spi_imx->devtype_data = devtype_data;
15491636 
1550
-	/* Get number of chip selects, either platform data or OF */
1551
-	if (mxc_platform_info) {
1552
-		master->num_chipselect = mxc_platform_info->num_chipselect;
1553
-		if (mxc_platform_info->chipselect) {
1554
-			master->cs_gpios = devm_kcalloc(&master->dev,
1555
-				master->num_chipselect, sizeof(int),
1556
-				GFP_KERNEL);
1557
-			if (!master->cs_gpios)
1558
-				return -ENOMEM;
1637
+	/*
1638
+	 * Get number of chip selects from device properties. This can be
1639
+	 * coming from device tree or boardfiles, if it is not defined,
1640
+	 * a default value of 3 chip selects will be used, as all the legacy
1641
+	 * board files have <= 3 chip selects.
1642
+	 */
1643
+	if (!device_property_read_u32(&pdev->dev, "num-cs", &val))
1644
+		master->num_chipselect = val;
1645
+	else
1646
+		master->num_chipselect = 3;
15591647 
1560
-			for (i = 0; i < master->num_chipselect; i++)
1561
-				master->cs_gpios[i] = mxc_platform_info->chipselect[i];
1562
-		}
1563
-	} else {
1564
-		u32 num_cs;
1565
-
1566
-		if (!of_property_read_u32(np, "num-cs", &num_cs))
1567
-			master->num_chipselect = num_cs;
1568
-		/* If not preset, default value of 1 is used */
1569
-	}
1570
-
1571
-	spi_imx->bitbang.chipselect = spi_imx_chipselect;
15721648 	spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
15731649 	spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
15741650 	spi_imx->bitbang.master->setup = spi_imx_setup;
....@@ -1627,6 +1703,12 @@
16271703 	if (ret)
16281704 		goto out_put_per;
16291705 
1706
+	pm_runtime_set_autosuspend_delay(spi_imx->dev, MXC_RPM_TIMEOUT);
1707
+	pm_runtime_use_autosuspend(spi_imx->dev);
1708
+	pm_runtime_get_noresume(spi_imx->dev);
1709
+	pm_runtime_set_active(spi_imx->dev);
1710
+	pm_runtime_enable(spi_imx->dev);
1711
+
16301712 	spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
16311713 	/*
16321714 	 * Only validated on i.mx35 and i.mx6 now, can remove the constraint
....@@ -1635,10 +1717,10 @@
16351717 	if (spi_imx->devtype_data->has_dmamode) {
16361718 		ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master);
16371719 		if (ret == -EPROBE_DEFER)
1638
-			goto out_clk_put;
1720
+			goto out_runtime_pm_put;
16391721 
16401722 		if (ret < 0)
1641
-			dev_err(&pdev->dev, "dma setup error %d, use pio\n",
1723
+			dev_dbg(&pdev->dev, "dma setup error %d, use pio\n",
16421724 				ret);
16431725 	}
16441726 
....@@ -1649,36 +1731,23 @@
16491731 	master->dev.of_node = pdev->dev.of_node;
16501732 	ret = spi_bitbang_start(&spi_imx->bitbang);
16511733 	if (ret) {
1652
-		dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
1653
-		goto out_clk_put;
1734
+		dev_err_probe(&pdev->dev, ret, "bitbang start failed\n");
1735
+		goto out_bitbang_start;
16541736 	}
16551737 
1656
-	/* Request GPIO CS lines, if any */
1657
-	if (!spi_imx->slave_mode && master->cs_gpios) {
1658
-		for (i = 0; i < master->num_chipselect; i++) {
1659
-			if (!gpio_is_valid(master->cs_gpios[i]))
1660
-				continue;
1738
+	pm_runtime_mark_last_busy(spi_imx->dev);
1739
+	pm_runtime_put_autosuspend(spi_imx->dev);
16611740 
1662
-			ret = devm_gpio_request(&pdev->dev,
1663
-						master->cs_gpios[i],
1664
-						DRIVER_NAME);
1665
-			if (ret) {
1666
-				dev_err(&pdev->dev, "Can't get CS GPIO %i\n",
1667
-					master->cs_gpios[i]);
1668
-				goto out_spi_bitbang;
1669
-			}
1670
-		}
1671
-	}
1672
-
1673
-	dev_info(&pdev->dev, "probed\n");
1674
-
1675
-	clk_disable(spi_imx->clk_ipg);
1676
-	clk_disable(spi_imx->clk_per);
16771741 	return ret;
16781742 
1679
-out_spi_bitbang:
1680
-	spi_bitbang_stop(&spi_imx->bitbang);
1681
-out_clk_put:
1743
+out_bitbang_start:
1744
+	if (spi_imx->devtype_data->has_dmamode)
1745
+		spi_imx_sdma_exit(spi_imx);
1746
+out_runtime_pm_put:
1747
+	pm_runtime_dont_use_autosuspend(spi_imx->dev);
1748
+	pm_runtime_set_suspended(&pdev->dev);
1749
+	pm_runtime_disable(spi_imx->dev);
1750
+
16821751 	clk_disable_unprepare(spi_imx->clk_ipg);
16831752 out_put_per:
16841753 	clk_disable_unprepare(spi_imx->clk_per);
....@@ -1696,30 +1765,83 @@
16961765 
16971766 	spi_bitbang_stop(&spi_imx->bitbang);
16981767 
1699
-	ret = clk_enable(spi_imx->clk_per);
1700
-	if (ret)
1701
-		return ret;
1702
-
1703
-	ret = clk_enable(spi_imx->clk_ipg);
1704
-	if (ret) {
1705
-		clk_disable(spi_imx->clk_per);
1768
+	ret = pm_runtime_get_sync(spi_imx->dev);
1769
+	if (ret < 0) {
1770
+		pm_runtime_put_noidle(spi_imx->dev);
1771
+		dev_err(spi_imx->dev, "failed to enable clock\n");
17061772 		return ret;
17071773 	}
17081774 
17091775 	writel(0, spi_imx->base + MXC_CSPICTRL);
1710
-	clk_disable_unprepare(spi_imx->clk_ipg);
1711
-	clk_disable_unprepare(spi_imx->clk_per);
1776
+
1777
+	pm_runtime_dont_use_autosuspend(spi_imx->dev);
1778
+	pm_runtime_put_sync(spi_imx->dev);
1779
+	pm_runtime_disable(spi_imx->dev);
1780
+
17121781 	spi_imx_sdma_exit(spi_imx);
17131782 	spi_master_put(master);
17141783 
17151784 	return 0;
17161785 }
17171786 
1787
+static int __maybe_unused spi_imx_runtime_resume(struct device *dev)
1788
+{
1789
+	struct spi_master *master = dev_get_drvdata(dev);
1790
+	struct spi_imx_data *spi_imx;
1791
+	int ret;
1792
+
1793
+	spi_imx = spi_master_get_devdata(master);
1794
+
1795
+	ret = clk_prepare_enable(spi_imx->clk_per);
1796
+	if (ret)
1797
+		return ret;
1798
+
1799
+	ret = clk_prepare_enable(spi_imx->clk_ipg);
1800
+	if (ret) {
1801
+		clk_disable_unprepare(spi_imx->clk_per);
1802
+		return ret;
1803
+	}
1804
+
1805
+	return 0;
1806
+}
1807
+
1808
+static int __maybe_unused spi_imx_runtime_suspend(struct device *dev)
1809
+{
1810
+	struct spi_master *master = dev_get_drvdata(dev);
1811
+	struct spi_imx_data *spi_imx;
1812
+
1813
+	spi_imx = spi_master_get_devdata(master);
1814
+
1815
+	clk_disable_unprepare(spi_imx->clk_per);
1816
+	clk_disable_unprepare(spi_imx->clk_ipg);
1817
+
1818
+	return 0;
1819
+}
1820
+
1821
+static int __maybe_unused spi_imx_suspend(struct device *dev)
1822
+{
1823
+	pinctrl_pm_select_sleep_state(dev);
1824
+	return 0;
1825
+}
1826
+
1827
+static int __maybe_unused spi_imx_resume(struct device *dev)
1828
+{
1829
+	pinctrl_pm_select_default_state(dev);
1830
+	return 0;
1831
+}
1832
+
1833
+static const struct dev_pm_ops imx_spi_pm = {
1834
+	SET_RUNTIME_PM_OPS(spi_imx_runtime_suspend,
1835
+				spi_imx_runtime_resume, NULL)
1836
+	SET_SYSTEM_SLEEP_PM_OPS(spi_imx_suspend, spi_imx_resume)
1837
+};
1838
+
17181839 static struct platform_driver spi_imx_driver = {
17191840 	.driver = {
17201841 		   .name = DRIVER_NAME,
17211842 		   .of_match_table = spi_imx_dt_ids,
1722
-		   },
1843
+		   .pm = &imx_spi_pm,
1844
+	},
17231845 	.id_table = spi_imx_devtype,
17241846 	.probe = spi_imx_probe,
17251847 	.remove = spi_imx_remove,